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61. 发明申请

US20100025749A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20100025749A1
公开(公告)日：2010-02-04
申请号：US12534422
申请日：2009-08-03
申请人： Jong-Ryeol Yoo , Tai-Su Park , Jong-Hoon Kang , Dong-Chan Kim , Jeong-Do Ryu , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin
发明人： Jong-Ryeol Yoo , Tai-Su Park , Jong-Hoon Kang , Dong-Chan Kim , Jeong-Do Ryu , Seong-Hoon Jeong , Si-Young Choi , Yu-Gyun Shin
IPC分类号： H01L27/10 , H01L27/092
CPC分类号： H01L21/823842 , H01L21/823828 , H01L27/10873 , H01L27/10894
摘要： A semiconductor device may include an isolation layer, gate electrodes, an insulating interlayer, an impurity region, a capping layer and a plug. The isolation layer may be formed in the substrate. The gate electrodes may be formed on the substrate. The insulating interlayer may be formed on the gate electrodes. The insulating interlayer may have a contact hole between the gate electrodes. The impurity region may be in the substrate exposed through the contact hole. The capping layer may be on the impurity region. The plug may be on the capping layer. Thus, the impurities may not be lost from the impurity region. As a result, the device may have improved electrical characteristics and reliability because depletion may not be generated in the electrode layer
摘要翻译：半导体器件可以包括隔离层，栅电极，绝缘中间层，杂质区，封盖层和插塞。隔离层可以形成在衬底中。栅电极可以形成在衬底上。绝缘中间层可以形成在栅电极上。绝缘中间层可以在栅电极之间具有接触孔。杂质区域可能在通过接触孔暴露的衬底中。覆盖层可以在杂质区上。插头可能在封盖层上。因此，杂质可能不会从杂质区域中流失。结果，由于在电极层中可能不产生耗尽，所以器件可能具有改善的电特性和可靠性

62. 发明授权

US07494859B2 Semiconductor device having metal gate patterns and related method of manufacture 有权
标题翻译：具有金属栅极图案和相关制造方法的半导体器件
公开(公告)号：US07494859B2
公开(公告)日：2009-02-24
申请号：US11400243
申请日：2006-04-10
申请人： Hag-Ju Cho , Taek-Soo Jeon , Hye-Lan Lee , Sang-Bom Kang , Yu-Gyun Shin
发明人： Hag-Ju Cho , Taek-Soo Jeon , Hye-Lan Lee , Sang-Bom Kang , Yu-Gyun Shin
IPC分类号： H01L21/8238
CPC分类号： H01L29/513 , H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/4958 , H01L29/4975 , H01L29/517 , H01L29/518 , H01L29/78
摘要： A semiconductor device comprising a semiconductor substrate having a first impurity region and a second impurity region, a first gate pattern formed on the first impurity region, and a second gate pattern formed on the second impurity region is disclosed. The first gate pattern comprises a first gate insulation layer pattern, a metal layer pattern having a first thickness, and a first polysilicon layer pattern. The second gate pattern comprises a second gate insulation layer pattern, a metal silicide layer pattern having a second thickness smaller than the first thickness, and a second polysilicon layer pattern. The metal silicide layer pattern is formed from a material substantially the same as the material from which the metal layer pattern is formed. A method for manufacturing the semiconductor device is also disclosed.
摘要翻译：一种半导体器件，包括具有第一杂质区和第二杂质区的半导体衬底，形成在第一杂质区上的第一栅极图案和形成在第二杂质区上的第二栅极图案。第一栅极图案包括第一栅极绝缘层图案，具有第一厚度的金属层图案和第一多晶硅层图案。第二栅极图案包括第二栅极绝缘层图案，具有小于第一厚度的第二厚度的金属硅化物层图案和第二多晶硅层图案。金属硅化物层图案由与形成金属层图案的材料基本相同的材料形成。还公开了一种半导体器件的制造方法。

63. 发明申请

US20070215959A1 Semiconductor structures including accumulations of silicon boronide and related methods 审中-公开
标题翻译：半导体结构包括硅化硼的积累和相关方法
公开(公告)号：US20070215959A1
公开(公告)日：2007-09-20
申请号：US11713877
申请日：2007-03-05
申请人： Jin-Wook Lee , Chang-Woo Ryoo , Tai-Su Park , U-In Chung , Yu-Gyun Shin
发明人： Jin-Wook Lee , Chang-Woo Ryoo , Tai-Su Park , U-In Chung , Yu-Gyun Shin
IPC分类号： H01L29/94
CPC分类号： H01L29/4941 , H01L21/28061
摘要： A semiconductor device may include a semiconductor substrate, first and second source/drain regions on a surface of the semiconductor substrate, and a channel region on the surface of the semiconductor substrate with the channel region between the first and second source/drain regions. An insulating layer pattern may be on the channel region, a first conductive layer pattern may be on the insulating layer, and a second conductive layer pattern may be on the first conductive layer pattern. The insulating layer pattern may be between the first conductive layer pattern and the channel region, and the first conductive layer pattern may include boron doped polysilicon with a surface portion having an accumulation of silicon boronide. The first conductive layer pattern may be between the second conductive layer pattern and the insulating layer pattern, and the second conductive layer pattern may include tungsten. Related methods are also discussed.
摘要翻译：半导体器件可以包括半导体衬底，半导体衬底的表面上的第一和第二源极/漏极区域以及在第一和第二源极/漏极区域之间具有沟道区域的半导体衬底的表面上的沟道区域。绝缘层图案可以在沟道区上，第一导电层图案可以在绝缘层上，并且第二导电层图案可以在第一导电层图案上。绝缘层图案可以在第一导电层图案和沟道区之间，并且第一导电层图案可以包括硼掺杂多晶硅，表面部分具有硅化硼的积累。第一导电层图案可以在第二导电层图案和绝缘层图案之间，并且第二导电层图案可以包括钨。还讨论了相关方法。

64. 发明申请

US20070032008A1 MOS semiconductor devices having polysilicon gate electrodes and high dielectric constant gate dielectric layers and methods of manufacturing such devices 审中-公开
标题翻译：具有多晶硅栅电极和高介电常数栅介电层的MOS半导体器件及其制造方法
公开(公告)号：US20070032008A1
公开(公告)日：2007-02-08
申请号：US11494100
申请日：2006-07-27
申请人： Hye-Min Kim , Yu-Gyun Shin , In-Sang Jeon , Sang-Bom Kang , Hong-Bae Park , Beom-Jun Jin
发明人： Hye-Min Kim , Yu-Gyun Shin , In-Sang Jeon , Sang-Bom Kang , Hong-Bae Park , Beom-Jun Jin
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78
摘要： A semiconductor device includes a substrate divided into an NMOS region and a PMOS region, a first gate pattern formed on the PMOS region, and a second gate pattern formed on the NMOS region. The first gate pattern includes a first gate oxide layer pattern, a metal oxide layer pattern, a silicon nitride layer pattern and a first polysilicon layer pattern that are sequentially stacked. The second gate pattern includes a second oxide layer pattern and a second polysilicon layer pattern. Related methods are also provided.
摘要翻译：半导体器件包括分为NMOS区和PMOS区的衬底，形成在PMOS区上的第一栅极图案，以及形成在NMOS区上的第二栅极图案。第一栅极图案包括依次层叠的第一栅极氧化物层图案，金属氧化物层图案，氮化硅层图案和第一多晶硅层图案。第二栅极图案包括第二氧化物层图案和第二多晶硅层图案。还提供了相关方法。

65. 发明申请

US20060189055A1 Method of forming a composite layer, method of manufacturing a gate structure by using the method of forming the composite layer and method of manufacturing a capacitor by using the method of forming the composite layer 审中-公开
标题翻译：复合层的形成方法，通过使用复合层的形成方法制造栅极结构的方法以及使用形成复合层的方法制造电容器的方法
公开(公告)号：US20060189055A1
公开(公告)日：2006-08-24
申请号：US11356399
申请日：2006-02-16
申请人： Hong-Bae Park , Hag-Ju Cho , Yu-Gyun Shin , Sang-Bom Kang
发明人： Hong-Bae Park , Hag-Ju Cho , Yu-Gyun Shin , Sang-Bom Kang
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/0228 , H01L21/02181 , H01L21/022 , H01L21/02274 , H01L21/28194 , H01L21/28202 , H01L21/3141 , H01L21/31645 , H01L29/40114 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78
摘要： Methods of forming a composite layer, a gate structure and a capacitor are disclosed. In the methods, a first dielectric layer is atomic layer deposited on a substrate by using an oxidation gas and a first precursor gas that includes hafnium precursors. A second dielectric layer is then atomic layer deposited on the first dielectric layer by using a nitriding gas and a second precursor gas that includes hafnium precursors.
摘要翻译：公开了形成复合层，栅极结构和电容器的方法。在该方法中，第一电介质层通过使用氧化气体和包括铪前体的第一前体气体在原子层上沉积在衬底上。然后通过使用氮化气体和包括铪前体的第二前体气体将第二电介质层原子层沉积在第一介电层上。

66. 发明申请

US20060060929A1 Semiconductor transistors having surface insulation layers and methods of fabricating such transistors 失效
公开(公告)号：US20060060929A1
公开(公告)日：2006-03-23
申请号：US11215217
申请日：2005-08-30
申请人： Gyoung-Ho Buh , Yu-Gyun Shin , Sang-Yin Hyun , Guk-Hyon Yon
发明人： Gyoung-Ho Buh , Yu-Gyun Shin , Sang-Yin Hyun , Guk-Hyon Yon
IPC分类号： H01L29/94 , H01L29/76
CPC分类号： H01L29/4983 , H01L21/28194 , H01L21/28273 , H01L21/28282 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/78 , H01L29/7881 , H01L29/792
摘要： Semiconductor devices having a transistor and methods of fabricating such devices are disclosed. The device may include a gate pattern formed on a substrate, spacers formed on sidewalls of the gate pattern, a surface insulation layer that may contact the substrate is interposed between the spacers and the substrate. An inversion layer is provided in the surface region of the substrate under the surface insulation layer. The surface insulation layer is formed of a material generating large quantities of surface states at an interface between the substrate and the surface insulation layer.

67. 发明申请

US20050285162A1 Semiconductor devices having a stacked structure and methods of forming the same 审中-公开
标题翻译：具有堆叠结构的半导体器件及其形成方法
公开(公告)号：US20050285162A1
公开(公告)日：2005-12-29
申请号：US11159596
申请日：2005-06-23
申请人： Chul-Sung Kim , Jin-Hwa Heo , Yu-Gyun Shin , Bon-Young Koo , Dong-Chan Kim , Jeong-Do Ryu
发明人： Chul-Sung Kim , Jin-Hwa Heo , Yu-Gyun Shin , Bon-Young Koo , Dong-Chan Kim , Jeong-Do Ryu
IPC分类号： H01L21/8244 , H01L21/336 , H01L21/822 , H01L21/8234 , H01L27/06 , H01L29/78
CPC分类号： H01L27/0688 , H01L21/8221
摘要： Methods of forming a semiconductor device having stacked structures include forming a first semiconductor structure on a substrate and forming a first interlayer insulating layer on the substrate. The first interlayer insulating layer has a substantially level upper face. A semiconductor layer is formed on the first interlayer insulating layer and a first gate insulation layer is formed on the semiconductor layer at a processing temperature selected to control damage to the first semiconductor structure. A second semiconductor structure is formed on the first gate insulation layer.
摘要翻译：形成具有堆叠结构的半导体器件的方法包括在衬底上形成第一半导体结构并在衬底上形成第一层间绝缘层。第一层间绝缘层具有基本上平坦的上表面。在第一层间绝缘层上形成半导体层，在半导体层上形成第一栅极绝缘层，该处理温度被选择为控制第一半导体结构的损坏。在第一栅绝缘层上形成第二半导体结构。

68. 发明授权

US06930062B2 Methods of forming an oxide layer in a transistor having a recessed gate 失效
标题翻译：在具有凹入栅极的晶体管中形成氧化物层的方法
公开(公告)号：US06930062B2
公开(公告)日：2005-08-16
申请号：US10850690
申请日：2004-05-21
申请人： Sang-Jin Hyun , Yu-Gyun Shin , Bon-Young Koo , Sug-Hun Hong , Taek-Soo Jeon , Jeong-do Ryu
发明人： Sang-Jin Hyun , Yu-Gyun Shin , Bon-Young Koo , Sug-Hun Hong , Taek-Soo Jeon , Jeong-do Ryu
IPC分类号： H01L21/336 , H01L21/316 , H01L21/762 , H01L21/26
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/02337 , H01L21/31662 , H01L21/76235
摘要： A method of forming an oxide layer on a semiconductor substrate includes thermally oxidizing a surface of the substrate to form an oxide layer on the substrate, and then exposing the oxide layer to an ambient including predominantly oxygen radicals to thereby thicken the oxide layer. Related methods of fabricating a recessed gate transistor are also discussed.
摘要翻译：在半导体衬底上形成氧化物层的方法包括热氧化衬底的表面以在衬底上形成氧化物层，然后将氧化物层暴露于主要包含氧自由基的环境，从而使氧化物层变厚。还讨论了制造凹陷栅极晶体管的相关方法。

69. 发明授权

US6107143A Method for forming a trench isolation structure in an integrated circuit 有权
标题翻译：在集成电路中形成沟槽隔离结构的方法
公开(公告)号：US6107143A
公开(公告)日：2000-08-22
申请号：US150668
申请日：1998-09-10
申请人： Tai-Su Park , Han-Sin Lee , Yu-Gyun Shin
发明人： Tai-Su Park , Han-Sin Lee , Yu-Gyun Shin
IPC分类号： H01L21/76 , H01L21/762 , H01L27/08
CPC分类号： H01L21/76232
摘要： A method is provided for forming a trench isolation structure in an integrated circuit that has a better reliability and an acceptable time-dependent dielectric breakdown over a greater range of production. The manufacturing method involves etching a trench in a semiconductor substrate, forming a sidewall-insulating layer along the sidewall and bottom of the trench, and depositing a trench-insulating layer in the trench and over the semiconductor substrate. The sidewall-insulating layer is formed to have a lower etch rate than the trench-insulating layer. As a result of this difference in etch rates, the sidewall-insulating layer is not damaged too much during wet etching processes that take place during the later part of manufacture. This makes the interface between the substrate, sidewall-insulating layer, and gate oxide more reliable. The difference in etching rate can be obtained by keeping an annealing process used in later processing below a threshold temperature so that the etch rate of the trench-isolating layer does fall too low. The difference in etching rate can also be obtained by using different materials for the sidewall-isolating layer and the trench-isolating layer, or by using multiple annealing processes.
摘要翻译：提供了一种用于在集成电路中形成沟槽隔离结构的方法，该集成电路在更大的生产范围内具有更好的可靠性和可接受的时间依赖介电击穿。该制造方法包括蚀刻半导体衬底中的沟槽，沿着沟槽的侧壁和底部形成侧壁绝缘层，并且在沟槽中和半导体衬底上沉积沟槽绝缘层。侧壁绝缘层形成为具有比沟槽绝缘层低的蚀刻速率。由于这种蚀刻速率的差异，在制造后期部分的湿式蚀刻工艺期间，侧壁绝缘层不会受到太大损害。这使得衬底，侧壁绝缘层和栅极氧化物之间的界面更可靠。通过将后续处理中使用的退火处理保持在阈值温度以下，使得沟槽隔离层的蚀刻速率确实降低，可以获得蚀刻速率的差异。也可以通过使用用于侧壁隔离层和沟槽隔离层的不同材料或通过使用多个退火工艺来获得蚀刻速率的差异。

70. 发明授权

US6083808A Method for forming a trench isolation in a semiconductor device 有权
标题翻译：在半导体器件中形成沟槽隔离的方法
公开(公告)号：US6083808A
公开(公告)日：2000-07-04
申请号：US160094
申请日：1998-09-25
申请人： Yu-Gyun Shin , Han-Sin Lee , Tai-su Park , Moon-Han Park
发明人： Yu-Gyun Shin , Han-Sin Lee , Tai-su Park , Moon-Han Park
IPC分类号： H01L21/76 , H01L21/28 , H01L21/762
CPC分类号： H01L21/76224 , Y10S148/05
摘要： A method for forming a trench isolation in a semiconductor device is provided in which a first heat treatment process is conducted on a thermal oxide layer previously formed in a trench at temperature range from about 1000.degree. C. to 1200.degree. C. for about 1 to 8 hours so as to remove defects in a semiconductor substrate and oxygen impurities within the semiconductor substrate resulting from a step of forming the trench in the semiconductor substrate. As a result, a subsequent second heat treatment process for densifying a trench filling material such as a CVD oxide layer can be performed at lower temperature of about 1000.degree. C. to 1050.degree. C., as compared with the temperature of the first annealing of the thermal oxide layer, thereby reducing distortions of the semiconductor substrate and reducing current leakages.
摘要翻译：提供了一种在半导体器件中形成沟槽隔离的方法，其中对预先形成在沟槽中的热氧化层进行第一热处理工艺，温度范围为约1000℃至1200℃，约1至 8小时，以便从半导体衬底中形成沟槽的步骤得到半导体衬底中的缺陷和半导体衬底内的氧杂质。结果，与在第一次退火温度相比，可以在约1000℃至1050℃的较低温度下进行用于致密化CVD氧化物层的沟槽填充材料的随后的第二热处理工艺热氧化层，从而减少半导体衬底的变形并减少电流泄漏。

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