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61. 发明授权

US06498100B2 Method of manufacturing semiconductor devices 有权
公开(公告)号：US06498100B2
公开(公告)日：2002-12-24
申请号：US09996918
申请日：2001-11-30
申请人： Akio Nishida , Kikuo Kusukawa , Toshiaki Yamanaka , Natsuki Yokoyama , Shinichiro Kimura , Norio Suzuki , Osamu Tsuchiya , Atsushi Ogishima
发明人： Akio Nishida , Kikuo Kusukawa , Toshiaki Yamanaka , Natsuki Yokoyama , Shinichiro Kimura , Norio Suzuki , Osamu Tsuchiya , Atsushi Ogishima
IPC分类号： H01L21302
CPC分类号： H01L27/10894 , H01L21/31053 , H01L21/76229 , H01L21/823437 , H01L21/823481 , H01L27/10814
摘要： In a method of manufacturing a semiconductor device having a memory mat portion in which an active region and a field region are formed densely, after a polishing stopper film is deposited on a semiconductor substrate, there are formed grooves by etching a polishing stopper film of a field region and the semiconductor substrate. Then, after an insulating film is deposited so as to fill the grooves, then insulating film is partly removed from the memory mat portion by etching. Under this state, the insulating film is chemically mechanically polished until the polishing stopper film is exposed. The film thickness of the polishing stopper film on the active region can be reduced, and an electrical element isolation characteristic of the field region can be improved. At the same time, upon chemical mechanical polishing, a silicon substrate can be prevented from being exposed at the central portion of the memory mat portion and the insulating film can be prevented from being left on the silicon nitride film near the outer periphery, thereby making it possible to form elements having uniform electrical characteristics on all active regions of the memory mat portion.

62. 发明授权

US5012310A Semiconductor memory having stacked capacitor 失效
标题翻译：半导体存储器具有层叠电容
公开(公告)号：US5012310A
公开(公告)日：1991-04-30
申请号：US566315
申请日：1990-08-13
申请人： Shinichiro Kimura , Yoshifumi Kawamoto , Toru Kaga , Hideo Sunami
发明人： Shinichiro Kimura , Yoshifumi Kawamoto , Toru Kaga , Hideo Sunami
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10808
摘要： A megabit dynamic random access memory realizing high integration and high reliability is disclosed. The need for an allowance for photomask alignment which is carried out to produce a stacked capacitor memory cell is eliminated. The plate electrode of each memory cell is isolated from the corresponding data line in a memory array by means of an insulating film which is self-alignedly provided around the plate electrode.
摘要翻译：公开了一种实现高集成度和高可靠性的兆比特动态随机存取存储器。消除了对制造堆叠式电容器存储单元进行的光掩模对准的允许的需要。每个存储单元的平板电极通过绝缘膜与存储器阵列中的对应数据线隔离，该绝缘膜自行设置在平板电极周围。

63. 发明授权

US08334794B2 Input device and keyboard device having illumination function 失效
标题翻译：具有照明功能的输入装置和键盘装置
公开(公告)号：US08334794B2
公开(公告)日：2012-12-18
申请号：US12579903
申请日：2009-10-15
申请人： Kazutoshi Watanabe , Hideaki Nagakubo , Takenobu Kimura , Koichi Yamamoto , Katsuyuki Katayama , Naomi Sato , Naoya Akiyama , Shinichiro Kimura , Masahiro Ishida , Naoki Yamada , Keiji Takagi , Toshinobu Hosaka
发明人： Kazutoshi Watanabe , Hideaki Nagakubo , Takenobu Kimura , Koichi Yamamoto , Katsuyuki Katayama , Naomi Sato , Naoya Akiyama , Shinichiro Kimura , Masahiro Ishida , Naoki Yamada , Keiji Takagi , Toshinobu Hosaka
IPC分类号： H03M11/00
CPC分类号： G06F3/0202 , H01H13/83 , H01H2219/044 , H01H2219/056 , H01H2219/06 , H01H2219/062
摘要： An input device includes a plurality of manipulation portions; an input function portion manipulated by the manipulation portions to perform an input function; a light guiding sheet facing the rear side of the plurality of manipulation portions; and a light source applying light into the light guiding sheet, wherein a rear surface opposite to a front surface of the light guiding sheet facing the manipulation portions is provided with a plurality of concave portions which is depressed to the inside of the light guiding sheet, wherein each concave portion has a circular opening and an inner surface which is a smooth concave curve surface, and wherein light propagated through the inside of the light guiding sheet is reflected by the inner surface toward the inside of the light guiding sheet, and the light is applied from the front surface of the light guiding sheet to the manipulation portions.
摘要翻译：输入装置包括多个操作部分; 由操作部分操纵以输入功能的输入功能部分; 面向所述多个操作部的后侧的导光片; 以及向所述导光片施加光的光源，其中与所述导光片的面对所述操作部的前表面相对的后表面设置有多个凹陷部，所述凹部被压向所述导光片的内部，其特征在于，每个凹部具有圆形开口和内表面，该内表面是光滑的凹曲面，并且其中通过导光片的内部传播的光被内表面朝向导光片的内部反射，并且光从导光片的前表面施加到操作部。

64. 发明授权

US08183635B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08183635B2
公开(公告)日：2012-05-22
申请号：US12756451
申请日：2010-04-08
申请人： Nobuyuki Sugii , Ryuta Tsuchiya , Shinichiro Kimura , Takashi Ishigaki , Yusuke Morita , Hiroyuki Yoshimoto
发明人： Nobuyuki Sugii , Ryuta Tsuchiya , Shinichiro Kimura , Takashi Ishigaki , Yusuke Morita , Hiroyuki Yoshimoto
IPC分类号： H01L21/00
CPC分类号： H01L27/1203 , H01L21/76283
摘要： A technique to be applied to a semiconductor device for achieving low power consumption by improving a shape at a boundary portion of a shallow trench and an SOI layer of an SOI substrate. A position (SOI edge) at which a main surface of a silicon substrate and a line extended along a side surface of an SOI layer are crossed is recessed away from a shallow-trench isolation more than a position (STI edge) at which a line extended along a sidewall of a shallow trench and a line extended along the main surface of the silicon substrate are crossed, and a corner of the silicon substrate at the STI edge has a curved surface.
摘要翻译：通过改善在SOI衬底的浅沟槽和SOI层的边界部分的形状来实现低功耗的半导体器件的技术。硅衬底的主表面和沿着SOI层的侧表面延伸的线交叉的位置（SOI边缘）比浅沟槽隔离更远离位于（STI边缘）的位置（STI边缘），在该位置处沿着浅沟槽的侧壁延伸并且沿着硅衬底的主表面延伸的线交叉，并且在STI边缘处的硅衬底的拐角具有弯曲表面。

65. 发明授权

US07978212B2 Disk label printer 有权
标题翻译：磁盘标签打印机
公开(公告)号：US07978212B2
公开(公告)日：2011-07-12
申请号：US12141587
申请日：2008-06-18
申请人： Hiroyoshi Zama , Takashi Goto , Mitsuo Makino , Shinichi Sagawai , Mitsuaki Yamazaki , Eihin Setsu , Hisashi Hoshino , Tomohiro Osumi , Shinichiro Kimura
发明人： Hiroyoshi Zama , Takashi Goto , Mitsuo Makino , Shinichi Sagawai , Mitsuaki Yamazaki , Eihin Setsu , Hisashi Hoshino , Tomohiro Osumi , Shinichiro Kimura
IPC分类号： B41J2/32
CPC分类号： B41J3/4071
摘要： Disclosed is a disk label printer that includes a slot-in type optical disk driving mechanism and a printing mechanism integrated with each other, has a small size, and smoothly transfers optical disks. The disclosed disk label printer includes: a case that has a slot through which an optical disk is inserted or ejected formed therein; an optical disk driving mechanism that is provided in the case and writes and/or reads signals to and/or from the optical disk mounted to a disk mounting portion; and a printing mechanism that is provided in the case and includes a thermal head which prints a desired image on a label surface of the optical disk. The printing mechanism is provided on a transfer path of the optical disk toward the optical disk driving mechanism between the slot and the optical disk driving mechanism. The thermal head and a platen roller come into pressure contact with each other with the optical disk interposed therebetween on the transfer path, only when the optical disk is transferred during the driving of the printing mechanism. The thermal head and the platen roller are withdrawn from the transfer path so as to be separated from each other, when the optical disk is transferred during operations other than the driving of the printing mechanism.
摘要翻译：公开了一种包括插入式光盘驱动机构和彼此集成的打印机构的盘标签打印机，其尺寸小，并且平滑地传送光盘。所公开的盘标签打印机包括：具有插入或喷射光盘的槽，光盘驱动机构，其设置在所述壳体中，并向从所述盘安装部安装的光盘写入和/或读取信号; 以及设置在壳体中并且包括在光盘的标签表面上打印所需图像的热敏头的打印机构。打印机构设置在光盘的传送路径朝向光盘驱动机构的槽和光盘驱动机构之间。只有当在打印机构的驱动期间传送光盘时，热敏头和压纸辊彼此压力接触，光盘插入在传送路径上。当驱动印刷机构以外的操作期间传送光盘时，热敏头和压纸滚筒从传送路径中取出，以便彼此分开。

66. 发明授权

US07619911B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07619911B2
公开(公告)日：2009-11-17
申请号：US10579911
申请日：2003-11-21
申请人： Satoru Hanzawa , Junji Shigeta , Shinichiro Kimura , Takeshi Sakata , Riichiro Takemura , Kazuhiko Kajigaya
发明人： Satoru Hanzawa , Junji Shigeta , Shinichiro Kimura , Takeshi Sakata , Riichiro Takemura , Kazuhiko Kajigaya
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/043
摘要： In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP is connected to a match line HMLr precharged to a high voltage. Further, a match detector MDr is arranged on a match line LMLr precharged to a low voltage to discriminate a comparison signal voltage generated at the match line according to the comparison result of data. According to such memory array structure and operation, comparison operation can be performed at low power and at high speed while influence of search-line noise is avoided in a match line pair. Therefore, a low power content addressable memory which allows search operation at high speed can be realized.
摘要翻译：在使用存储电路STC和比较器CP的存储器单元构成的存储器阵列中，将栅电极连接到搜索线的晶体管的源电极或漏电极的一个电极，构成比较器CP连接到预充电到高电压的匹配线HMLr。此外，匹配检测器MDr布置在预充电到低电压的匹配线LMLr上，以根据数据的比较结果来识别在匹配线处产生的比较信号电压。根据这种存储器阵列结构和操作，可以在低功率和高速度下执行比较操作，同时在匹配线对中避免搜索线噪声的影响。因此，可以实现允许高速搜索操作的低功率内容可寻址存储器。

67. 发明授权

US07247890B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07247890B2
公开(公告)日：2007-07-24
申请号：US10931119
申请日：2004-09-01
申请人： Tomoko Sekiguchi , Shinichiro Kimura , Renichi Yamada , Kikuo Watanabe , Hiroshi Miki , Kenichi Takeda
发明人： Tomoko Sekiguchi , Shinichiro Kimura , Renichi Yamada , Kikuo Watanabe , Hiroshi Miki , Kenichi Takeda
IPC分类号： H01L31/0328 , H01L29/80
CPC分类号： H01L29/66659 , H01L27/10855 , H01L27/10873 , H01L27/10894 , H01L29/1079 , H01L29/6656 , H01L29/7835
摘要： Disclosed is herein a semiconductor device having a DRAM with less scattering of threshold voltage of MISFET in a memory cell and having good charge retainability of a capacitor, and a manufacturing method of the semiconductor device. An anti-oxidation film is formed to the side wall of a gate electrode before light oxidation thereby suppressing the oxidation of the side wall for the gate electrode and decreasing scattering of the thickness of the film formed to the sidewall in an asymmetric diffusion region structure in which the impurity concentration of an n-type semiconductor region and a p-type semiconductor region on the side of the data line is made relatively higher than the impurity concentration in the n-type semiconductor region and p-type semiconductor region on the side of the capacitor, respectively.
摘要翻译：这里公开了具有在存储单元中具有MISFET阈值电压的较小散射并具有良好的电容保持性的DRAM的半导体器件，以及半导体器件的制造方法。在光氧化之前，在栅电极的侧壁上形成抗氧化膜，从而抑制栅电极的侧壁的氧化，并且在不对称扩散区域结构中减少形成在侧壁上的膜的厚度的散射使数据线一侧的n型半导体区域和p型半导体区域的杂质浓度比n型半导体区域和p型半导体区域的杂质浓度相对高于电容器。

68. 发明授权

US07196368B2 Semiconductor memory arrangements with crown shaped capacitor arrangements trenched in interlayer dielectric film 失效
标题翻译：具有冠状电容器布置的半导体存储器布置在层间绝缘膜中沟槽
公开(公告)号：US07196368B2
公开(公告)日：2007-03-27
申请号：US10914223
申请日：2004-08-10
申请人： Shinichiro Kimura , Toshiaki Yamanaka , Kiyoo Itoh , Takeshi Sakata , Tomonori Sekiguchi , Hideyuki Matsuoka
发明人： Shinichiro Kimura , Toshiaki Yamanaka , Kiyoo Itoh , Takeshi Sakata , Tomonori Sekiguchi , Hideyuki Matsuoka
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10852 , H01L27/108 , H01L27/10814 , H01L27/10817 , H01L27/10882 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L27/11502 , H01L27/11507 , H01L28/90
摘要： A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficultly of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.
摘要翻译：在由半导体衬底（1）上层叠的电介质膜（6,8,10和12）形成的沟槽中形成由存储电极（19），电容器电介质膜（20）和平板电极（21）构成的电容器）和埋入布线层（9和11）形成在电容器下面。由于电容器不是形成在半导体衬底中而是在其上形成，所以存在可以形成电容器的区域的空间，并且通过使用全局字线的布线层（9和11）难以形成布线，选择线。由于在周边电路区域与布线（34）的下表面接触的电介质膜（32）的上表面延伸到存储单元区域并与电容器（33）的一侧接触，外围电路区域和存储单元区域之间的台阶高度显着降低。

69. 发明授权

US06900492B2 Integrated circuit device with P-type gate memory cell having pedestal contact plug and peripheral circuit 失效
标题翻译：具有P型栅极存储单元的集成电路器件具有基座接触插头和外围电路
公开(公告)号：US06900492B2
公开(公告)日：2005-05-31
申请号：US10164008
申请日：2002-06-07
申请人： Norikatsu Takaura , Hideyuki Matsuoka , Shinichiro Kimura , Ryo Nagai , Satoru Yamada
发明人： Norikatsu Takaura , Hideyuki Matsuoka , Shinichiro Kimura , Ryo Nagai , Satoru Yamada
IPC分类号： H01L27/108 , H01L21/336 , H01L21/60 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L21/8246 , H01L27/115 , H01L29/49 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10894 , H01L21/76895 , H01L21/76897 , H01L21/823857 , H01L27/10814 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L27/10897 , H01L27/11502 , H01L27/11507 , H01L29/4941 , H01L29/6656
摘要： A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved.Each gate electrode in a memory cell area is formed of p type polycrystalline silicon, and a cap insulating film on each gate electrode and a sidewall film on the sidewall thereof are formed of a silicon oxide film. A polycrystalline silicon film formed on the gate electrodes and between the gate electrodes is polished by a CMP method, and thereby contact electrodes are formed. Also, sidewall films each composed of a laminated film of the silicon oxide film and the polycrystalline silicon film are formed on the sidewall of the gate electrodes in the logic circuit area, and these films are used as a mask to form semiconductor areas. As a result, it is possible to reduce the boron penetration and form contact electrodes in a self-alignment manner. In addition, the performance of the MISFET constituting the logic circuit can be improved.
摘要翻译： DRAM存储单元的刷新特性得到改善，并且在周边形成的构成逻辑电路的MISFET的性能得到改善。存储单元区域中的每个栅电极由p型多晶硅形成，并且每个栅电极上的帽绝缘膜和其侧壁上的侧壁膜由氧化硅膜形成。通过CMP方法对形成在栅电极和栅电极之间的多晶硅膜进行抛光，形成接触电极。此外，在逻辑电路区域中的栅电极的侧壁上形成各自由氧化硅膜和多晶硅膜的叠层膜构成的侧壁膜，并且将这些膜用作掩模以形成半导体区域。结果，可以以自对准的方式降低硼渗透并形成接触电极。此外，可以提高构成逻辑电路的MISFET的性能。

70. 发明授权

US06798005B2 Semiconductor memory device having large storage capacity and minimal step height between memory cell and peripheral circuits 有权
标题翻译：存储单元与外围电路之间存储容量大，步距高的半导体存储器件
公开(公告)号：US06798005B2
公开(公告)日：2004-09-28
申请号：US10206215
申请日：2002-07-29
申请人： Shinichiro Kimura , Toshiaki Yamanaka , Kiyoo Itoh , Takeshi Sakata , Tomonori Sekiguchi , Hideyuki Matsuoka
发明人： Shinichiro Kimura , Toshiaki Yamanaka , Kiyoo Itoh , Takeshi Sakata , Tomonori Sekiguchi , Hideyuki Matsuoka
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L27/108 , H01L27/10814 , H01L27/10817 , H01L27/10882 , H01L27/10885 , H01L27/10894 , H01L27/10897 , H01L27/11502 , H01L27/11507 , H01L28/90
摘要： A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficulty of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.
摘要翻译：在由半导体衬底（1）上层叠的电介质膜（6,8,10和12）形成的沟槽中形成由存储电极（19），电容器电介质膜（20）和平板电极（21）构成的电容器）和埋入布线层（9和11）形成在电容器下面。由于电容器不是形成在半导体衬底中而是在其上形成，因此通过使用用于全局字线的布线层（9和11），可以形成电容器并且难以形成布线的难度减小，随着在外围电路区域中与布线（34）的下表面接触的电介质膜（32）的上表面延伸到存储单元区域中并与电容器的侧面接触（33），外围电路区域和存储单元区域之间的台阶高度显着降低。

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