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61. 发明申请

US20050005193A1 Data recording/reproduction device and data recording/reproduction method 有权
标题翻译：数据记录/再现装置和数据记录/再现方法
公开(公告)号：US20050005193A1
公开(公告)日：2005-01-06
申请号：US10487606
申请日：2003-07-22
申请人： Toshiyuki Nakagawa , Keitarou Kondou , Hiroaki Eto , Yoshihide Shimpuku
发明人： Toshiyuki Nakagawa , Keitarou Kondou , Hiroaki Eto , Yoshihide Shimpuku
IPC分类号： G11B5/09 , G11B20/10 , G11B20/12 , G11B20/18 , H03M13/15 , H03M13/29 , H02H3/05
CPC分类号： G11B20/1833 , G11B20/1258 , G11B20/1866 , G11B2020/1222 , G11B2020/1232 , G11B2020/1238 , G11B2020/1267 , G11B2020/1294 , G11B2220/2516
摘要： In order to reproduce data in a stable manner by correction of random and burst errors of a wide range without lowering a transfer speed, C2 error correction for correcting an inter-sector error is carried out in addition to the conventional C1 error correction for correcting an error generated in a sector. The configuration of an error correction unit (or an ECC block) including C1 and C2 codes is formed as a track. That is to say, one track is used as the base of an ECC block unit. In this way, two ECC block units never exist in the same track.
摘要翻译：为了通过校正宽范围的随机和脉冲串错误而不降低传送速度来稳定地再现数据，除了用于校正传输速度的常规C1错误校正之外还执行用于校正扇区间误差的C2纠错扇区中产生的错误。包括C1和C2码的纠错单元（或ECC块）的配置被形成为轨道。也就是说，使用一个轨道作为ECC块单元的基础。以这种方式，两个ECC块单元永远不存在于同一个轨道中。

62. 发明授权

US06677866B2 Modulation apparatus/method, demodulation apparatus/method and program presenting medium 有权
标题翻译：调制装置/方法，解调装置/方法和程序呈现介质
公开(公告)号：US06677866B2
公开(公告)日：2004-01-13
申请号：US10263079
申请日：2002-10-02
申请人： Josephus A. H. M. Kahlman , Kornelis A. Schouhamer Immink , Gijsbert J. Van Den Enden , Toshiyuki Nakagawa , Yoshihide Shinpuku , Tatsuya Narahara , Kosuke Nakamura
发明人： Josephus A. H. M. Kahlman , Kornelis A. Schouhamer Immink , Gijsbert J. Van Den Enden , Toshiyuki Nakagawa , Yoshihide Shinpuku , Tatsuya Narahara , Kosuke Nakamura
IPC分类号： H03M700
CPC分类号： G11B20/1426 , G11B2020/1453 , H03M5/145
摘要： How to record and play back data at a high line density. A DSV control bit determining/inserting unit 11 inserts DSV control bits for execution of DSV control into an input data string and outputs the data string including the DSV control bits to a modulation unit 12. The modulation unit 12 converts the data string with a basic data length of 2 bits into variable length code with a basic code length of 3 bits in accordance with a conversion table and outputs the code resulting from the conversion to a NRZI encoding unit 13. The conversion table used by the modulation unit 12 includes substitution codes for limiting the number of consecutive appearances of a minimum run to a predetermined value and substitution codes for keeping a run length limit. In addition, the conversion table enforces a conversion rule, according to which the remainder of division of the “1” count of an element in a data string by 2 having a value of 0 or 1 shall always be equal to the remainder of division of the “1” count of an element in the code resulting from conversion of the data string by 2.
摘要翻译：如何以高线密度记录和播放数据。 DSV控制位确定/插入单元11将用于执行DSV控制的DSV控制位插入到输入数据串中，并将包括DSV控制位的数据串输出到调制单元12.调制单元12将数据串以基本 2比特的数据长度根据转换表具有3比特的基本码长度的可变长度码，并将从转换得到的码输出到NRZI编码单元13.调制单元12使用的转换表包括替换码用于将最小运行的连续出现次数限制为预定值，以及用于保持游程长度限制的替代代码。另外，转换表强制执行转换规则，根据该转换规则，数据串中的元素的“1”计数的余数除以2，值为0或1，其总和必须等于由数据字符串转换得到的代码中的元素的“1”计数为2。

63. 发明授权

US06359930B1 Modulation device and method and distribution medium 有权
标题翻译：调制装置及方法及配送介质
公开(公告)号：US06359930B1
公开(公告)日：2002-03-19
申请号：US09208125
申请日：1998-12-09
申请人： Toshiyuki Nakagawa , Yoshihide Shimpuku
发明人： Toshiyuki Nakagawa , Yoshihide Shimpuku
IPC分类号： H03M702
CPC分类号： H03M7/46 , G11B20/1426 , G11B2020/1457 , H03M5/145
摘要： A DSV bit is inserted in an input data string by a DSV bit determining insertion unit. A modulation unit has a conversion table, and the element of the conversion table comprises the element for determining uniquely, and has a conversion rule that residues obtained by dividing the number of “1” in the element of a data string and the number of “1” in the element of a code word string to be converted by 2 are identically 1 or 0 for both residues. A channel bit string is modulated according to the conversion table, and further NRZI modulated by an NRZI modulation unit. Thus, DSV control can be performed with reduced redundancy.
摘要翻译：通过DSV位确定插入单元将DSV位插入到输入数据串中。调制单元具有转换表，并且转换表的元素包括用于唯一地确定的元素，并且具有转换规则，即通过将数据串的元素中的“1”数除以“ 要转换为2的代码字串的元素中的“1”对于两个残差都相同地为1或0。根据转换表调制通道位串，并且由NRZI调制单元进一步调制NRZI。因此，可以以减少的冗余来执行DSV控制。

64. 发明授权

US06340938B1 Demodulating device, demodulating method and supply medium with predetermined error length 失效
标题翻译：解调装置，解调方式和预定误差长度的供电介质
公开(公告)号：US06340938B1
公开(公告)日：2002-01-22
申请号：US09378064
申请日：1999-08-20
申请人： Toshiyuki Nakagawa
发明人： Toshiyuki Nakagawa
IPC分类号： H03M500
CPC分类号： H03M5/00 , H03M7/00 , H03M7/40 , H03M7/46
摘要： A demodulating device of the present invention in which an error code/constraint length determining unit, a minimum run continuation restricting code detecting unit and a minimum run/maximum run compensating code detecting unit specify a constraint length of a code having a predetermined length including an error and inverse conversion units and an error data demodulation table demodulate the code based on the specified constraint length, thus reducing error propagation by a simpler constitution when bit shift error is caused.
摘要翻译：本发明的解调装置，其中错误代码/约束长度确定单元，最小运行延续限制代码检测单元和最小运行/最大运行补偿代码检测单元指定具有预定长度的代码的约束长度，包括错误和逆转换单元以及错误数据解调表基于指定的约束长度来解调代码，从而通过更简单的结构减少错误传播，当发生位移错误时。

65. 发明授权

US06275175B1 Device for encoding/decoding n-bit source words into corresponding m-bit channel words, and vice versa 失效
标题翻译：将n位源字编码/解码为相应的m位通道字的装置，反之亦然
公开(公告)号：US06275175B1
公开(公告)日：2001-08-14
申请号：US09702914
申请日：2000-10-27
申请人： Josephus A. H. M. Kahlman , Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara , Kousuke Nakamura
发明人： Josephus A. H. M. Kahlman , Toshiyuki Nakagawa , Yoshihide Shimpuku , Tatsuya Narahara , Kousuke Nakamura
IPC分类号： H03M700
CPC分类号： G11B20/1426 , H03M5/145
摘要： A device is disclosed for encoding a stream of databits of a binary source signal (S) into a stream of databits of a binary channel signal (C), wherein the bitstream of the source signal is divided into n-bit source words (x1, x2), which device comprises converting means (CM) adapted to convert said source words into corresponding m-bit channel words (y1, y2, y3). The converting means (CM) are further adapted to convert n-bit source words into corresponding m-bit channel words, such that the conversion for each n-bit source word is parity preserving (table I) (FIG. 1). The relations hold that m>n≧1, p≧1, and that p can vary. Preferably, m=n+1. The device is adapted to convert the 8-bit bit sequence ‘00010001’ in the source signal into the 12-bit bitsequence ‘100010010010’ and to convert the 8-bit bitsequence ‘10010001’ into the 12-bit bitsequence ‘000010010010’, in order to limit the repeated minimum transition runlength in the channel signal. Also other 8-bit sequences require a specific encoding into 12-bit bitsequences in order to limit the k-constraint of the channel signal to 7. Further, a decoding device is disclosed for decoding the channel signal obtained by means of the encoding device.
摘要翻译：公开了一种用于将二进制源信号（S）的数据位流编码成二进制信道信号（C）的数据位流的装置，其中源信号的比特流被划分为n位源字（x1， x2），该装置包括适于将所述源字转换成对应的m位通道字（y1，y2，y3）的转换装置（CM）。转换装置（CM）还适于将n位源字转换成相应的m位通道字，使得每个n位源字的转换是奇偶校验（表1）（图1）。关系认定m> n> = 1，p> = 1，p可以变化。优选地，m = n + 1。该装置适于将源信号中的8位比特序列“00010001”转换为12比特比特序列“100010010010”，并将8比特比特序列“10010001”转换为12 比特序列“000010010010”，以便限制信道信号中重复的最小过渡游程长度。而且其他8位序列还需要对12位比特序列进行特定编码，以将信道信号的k约束限制为7.此外，公开了一种解码装置，用于对通过编码装置获得的信道信号进行解码。

66. 发明授权

US6111833A Data decoder 失效
标题翻译：数据解码器
公开(公告)号：US6111833A
公开(公告)日：2000-08-29
申请号：US930162
申请日：1997-10-03
申请人： Toshiyuki Nakagawa , Hiroyuki Ino , Shunji Yoshimura , Shinichi Kai
发明人： Toshiyuki Nakagawa , Hiroyuki Ino , Shunji Yoshimura , Shinichi Kai
IPC分类号： G11B20/10 , G11B20/14 , G11B20/18 , H03M5/14 , H04L25/49 , G11B7/00
CPC分类号： H04L25/4906 , G11B20/10009 , G11B20/1426 , G11B20/18 , H03M5/145
摘要： In a data decoding apparatus of this invention, level of a reproduction RF signal 7a at the time of the binary level judgment of channel bit is temporarily stored into a RF signal level memory section 20. The portions which do not satisfy the conditions of the minimum run length and the maximum run length of the same symbols within the channel bit data train are respectively detected by a (d'-1) detecting section 16 and a (k'+1) detecting section 17. This data decoding apparatus comprises correction bit position detecting sections 18, 19 for outputting correction bit position designation signals on the basis of level of the RF signal at the time of the binary level judgment stored in the RF signal level memory section 20, and a bit data inversion correcting section 15 for inverting logic level of data at bit position designated on the basis of the correction bit position designation signals 18a, 18b, 19a, 19b. In the case where there exists any portion which does not satisfy the conditions of the minimum run length and/or the maximum run length of the same symbols within channel bit data obtained by binarizing a signal which has been read out from the recording medium, correction is implemented to the channel bit data, thereby making it possible to improve the bit error rate, and to ensure skew margin.
摘要翻译： PCT No.PCT / JP97 / 00336 Sec。 371日期1997年10月3日第 102（e）日期1997年10月3日PCT 1997年2月7日提交PCT公布。 WO97 / 29485 PCT公开号日期：1997年8月14日在本发明的数据解码装置中，通道位的二进制判定时的再现RF信号7a的电平临时存储到RF信号电平存储部20中。不满足的部分信道位数据序列中相同符号的最小游程长度和最大游程长度的条件分别由（d'-1）检测部分16和（k'+ 1）检测部分17检测。该数据解码装置包括校正位位置检测部分18,19，用于根据存储在RF信号电平存储部分20中的二进制电平判断时的RF信号的电平输出校正位位置指定信号，以及位数据反转校正部分15，用于反转基于校正位位置指定信号18a，18b，19a，19b指定的比特位置的数据的逻辑电平。在通过对从记录介质读出的信号进行二值化获得的通道位数据中存在不满足最小游程长度的条件和/或相同符号的最大游程长度的部分的情况下，被实现到通道位数据，从而使得可以提高误码率，并且确保倾斜余量。

67. 发明授权

US5986592A Encoder decoder device not using an A/D converter and method thereof 失效
标题翻译：不使用A / D转换器的编码器解码器装置及其方法
公开(公告)号：US5986592A
公开(公告)日：1999-11-16
申请号：US940828
申请日：1997-09-30
申请人： Toshiyuki Nakagawa , Shunji Yoshimura
发明人： Toshiyuki Nakagawa , Shunji Yoshimura
IPC分类号： H03M13/00
CPC分类号： H03M13/00
摘要： An encoder/decoder device for improving the bit error rate, speedily and at low cost without using an A/D converter circuit. A comparator compares the playback signal loaded from the disk with a specified reference level, places the signal in binary notation and sends the binary information to a memory. When the continuous length showing the quantity of zeroes placed between ones in succession is an error length which is shorter than a specified length 3T designated beforehand, an error length detection circuit detects this as a continuous length. A pattern detector circuit detects patterns in which the continuous length in front of error length 2T is 3T and the continuous length behind 2T is 4T or more, and further detects patterns in which the next continuous length after error length 2T is 3T and the continuous length in front of 2T is 4T or more. A position compensator circuit specifies the bit right after 2T as the correction position when a pattern greater than 3T-2T-4T is detected; and specifies the bit right before 2T when a pattern greater than 4T-2T-3T is detected. A processing circuit inverts the logic of the bits specified for position correction and outputs the result.
摘要翻译：一种用于在不使用A / D转换器电路的情况下快速且低成本地改善误码率的编码器/解码器装置。比较器将从磁盘加载的重放信号与指定的参考电平进行比较，将信号以二进制符号表示，并将二进制信息发送到存储器。当连续放置的零的数量的连续长度是比预先指定的指定长度3T短的误差长度时，误差长度检测电路将其检测为连续长度。模式检测电路检测错误长度2T前的连续长度为3T，2T后的连续长度为4T以上的图案，进一步检测误差长度2T后的下一连续长度为3T的图案，连续长度在2T以前是4T以上。当检测到大于3T-2T-4T的图案时，位置补偿器电路指定2T之后的位作为校正位置; 并且当检测到大于4T-2T-3T的模式时，指定位于2T之前的位。处理电路将指定用于位置校正的位的逻辑反相并输出结果。

68. 发明授权

US5781131A Data encoding method and data decoding method 失效
标题翻译：数据编码方法和数据解码方法
公开(公告)号：US5781131A
公开(公告)日：1998-07-14
申请号：US693083
申请日：1996-10-07
申请人： Yoshihide Shimpuku , Toshiyuki Nakagawa
发明人： Yoshihide Shimpuku , Toshiyuki Nakagawa
IPC分类号： G06T9/00 , G11B20/14 , H03M5/14 , H03M5/00
CPC分类号： G11B20/1426 , G06T9/005 , H03M5/145
摘要： A data encoding method for converting a (m i) bit based data word string into a (n i) bit based codeword string. The encoding method receives a (m i) bit based data word string by a shift register 1, decides a constraint length specifying the length of a data word which is to be converted by an encoder 2, and decides on which number of bits as counted from the leading end of the m bits falls the leading end bit of the data word which is to be converted. The encoding method selects, by a selector 3, one of a plurality of conversion tables constituting variable length tables and at least satisfying the minimum run length d, in accordance with the constraint length and the above results of decision. The encoding method also generates a codeword corresponding to the data word, now to be converted, in accordance with the selected conversion table. The encoding method assures a larger value of the product of the minimum length between transitions and the window margin, thus enabling data to be recorded to a higher density on an information recording medium.
摘要翻译： PCT No.PCT / JP95 / 02542 Sec。 371日期1996年10月7日第 102（e）日期1996年10月7日PCT 1995年12月12日PCT PCT。 WO96 / 19044 PCT公开号日期：1996年6月20日一种用于将（m i）位的数据字串转换成（n i）位的码字串的数据编码方法。编码方法由移位寄存器1接收（mi）比特数据字串，确定规定由编码器2转换的数据字的长度的约束长度，并且确定从哪个位数开始计数 m位的前导端落在要转换的数据字的前端。编码方法根据约束长度和上述判定结果，由选择器3选择构成可变长度表并且至少满足最小游程长度d的多个转换表中的一个。编码方法还根据所选择的转换表生成对应于数据字的码字，现在要被转换。编码方法确保了转换之间的最小长度与窗口边缘的乘积的较大值，从而使得能够在信息记录介质上更高密度地记录数据。

69. 发明授权

US07750828B2 Systems and methods for encoding and decoding data using selective substitution of conversion table 失效
标题翻译：使用转换表的选择性替换对数据进行编码和解码的系统和方法
公开(公告)号：US07750828B2
公开(公告)日：2010-07-06
申请号：US11789107
申请日：2007-04-23
申请人： Toshiyuki Nakagawa
发明人： Toshiyuki Nakagawa
IPC分类号： H03M7/00
CPC分类号： H03M5/145 , G11B20/1426 , G11B2020/1457
摘要： Systems and methods for encoding and decoding data utilize selective substitution of a conversion table for converting data having a basic data length of m bits into a variable length code (d, k; m, n) having a minimum run of d (d>0), a maximum run length of k and a basic codeword length of n bits, wherein the systems and methods use a basic conversion table and a substitute conversion table for converting the data. The selective substitution of the conversion table in a preferred exemplary embodiment is based on control information of a data string and/or a variable length code string.
摘要翻译：用于编码和解码数据的系统和方法利用转换表的选择性替换来将具有m位基本数据长度的数据转换为具有最小运行d（d> 0）的可变长度代码（d，k; m，n）），k的最大游程长度和n位的基本码字长度，其中系统和方法使用用于转换数据的基本转换表和替代转换表。在优选示例性实施例中，转换表的选择性替换基于数据串和/或可变长度代码串的控制信息。

70. 发明申请

US20100014860A1 COMMUNICATION APPARATUS AND COMMUNICATION METHOD 审中-公开
标题翻译：通信设备和通信方法
公开(公告)号：US20100014860A1
公开(公告)日：2010-01-21
申请号：US12502106
申请日：2009-07-13
申请人： Toshiyuki Nakagawa
发明人： Toshiyuki Nakagawa
IPC分类号： H04J14/00 , H04N7/173
CPC分类号： H04N21/26603 , H04N21/2389 , H04N21/2402 , H04N21/2407
摘要： A communication apparatus configured to transmit moving image data to a receiving apparatus via a network. The communication apparatus includes a coding unit configured to code the moving image data, a control information generation unit configured to determine a degree of importance of each packet of the moving image data coded by the coding unit and transmission quality of the network, and generate, for each packet, control information to control communication service quality according to the determined degree of importance and transmission quality, a packet generation unit configured to generate a packet based on the moving image data coded by the coding unit and the control information generated by the control information generation unit, and a communication control unit configured to transmit the packet generated by the packet generation unit.
摘要翻译：一种被配置为经由网络将运动图像数据发送到接收装置的通信装置。通信装置包括：编码单元，被配置为对运动图像数据进行编码;控制信息生成单元，被配置为确定由编码单元编码的运动图像数据的每个分组的重要程度和网络的传输质量，对于每个分组，根据确定的重要性和传输质量来控制通信服务质量的控制信息;分组生成单元，被配置为基于由编码单元编码的运动图像数据和由控制生成的控制信息生成分组信息生成单元，以及通信控制单元，被配置为发送由分组生成单元生成的分组。

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