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61. 发明申请

US20110287627A1 SEMICONDUCTOR TEST PAD STRUCTURES 有权
公开(公告)号：US20110287627A1
公开(公告)日：2011-11-24
申请号：US13197003
申请日：2011-08-03
申请人： Hsien-Wei Chen , Ying-Ju Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Ying-Ju Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng
IPC分类号： H01L21/768
CPC分类号： H01L22/34 , H01L24/05 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer.
摘要翻译：具有集成的模具隔离保护屏障的半导体测试焊盘互连结构。互连结构包括多个堆叠的金属层，每个层具有通过介电材料层与其它测试焊盘分离的导电测试焊盘。在一个实施例中，至少一个金属通孔条被嵌入到互连结构中，并将金属层中的每个测试焊盘电连接在一起。在一些实施例中，通孔棒基本上沿着由每个测试垫限定的整个第一侧面延伸。在其它实施例中，可以提供一对相对的通孔条，其布置在限定在半导体晶片上的划线带中的模切单切锯切线的相对侧上。

62. 发明授权

US08058151B2 Methods of die sawing 有权
标题翻译：模切方法
公开(公告)号：US08058151B2
公开(公告)日：2011-11-15
申请号：US12798587
申请日：2010-04-06
申请人： Shin-Puu Jeng , Hao-Yi Tsai
发明人： Shin-Puu Jeng , Hao-Yi Tsai
IPC分类号： H01L21/46 , H01L21/78 , H01L21/301
CPC分类号： H01L21/78 , B28D5/022
摘要： A structure includes a substrate having a plurality of scribe line areas surrounding a plurality of die areas. Each of the die areas includes at least one first conductive structure formed over the substrate. Each of the scribe line areas includes at least one active region and at least one non-active region. The active region includes a second conductive structure formed therein. The structure further includes at least one first passivation layer formed over the first conductive structure and second conductive structure, wherein at least a portion of the first passivation layer within the non-active region is removed, whereby die-sawing damage is reduced.
摘要翻译：一种结构包括具有围绕多个管芯区域的多个划线区域的衬底。每个管芯区域包括形成在衬底上的至少一个第一导电结构。每个划线区域包括至少一个有源区和至少一个非有源区。有源区包括形成在其中的第二导电结构。该结构还包括形成在第一导电结构和第二导电结构之上的至少一个第一钝化层，其中非活性区域内的第一钝化层的至少一部分被去除，从而降低模切锯损坏。

63. 发明授权

US08013333B2 Semiconductor test pad structures 有权
标题翻译：半导体测试板结构
公开(公告)号：US08013333B2
公开(公告)日：2011-09-06
申请号：US12267021
申请日：2008-11-07
申请人： Hsien-Wei Chen , Ying-Ju Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Ying-Ju Chen , Yu-Wen Liu , Hao-Yi Tsai , Shin-Puu Jeng
IPC分类号： H01L23/58
CPC分类号： H01L22/34 , H01L24/05 , H01L2924/14 , H01L2924/1461 , H01L2924/00
摘要： A semiconductor test pad interconnect structure with integrated die-separation protective barriers. The interconnect structure includes a plurality of stacked metal layers each having an electrically conductive test pad separated from other test pads by a dielectric material layer. In one embodiment, at least one metallic via bar is embedded into the interconnect structure and electrically interconnects each of the test pads in the metal layers together. The via bar extends substantially along an entire first side defined by each test pad in some embodiments. In other embodiments, a pair of opposing via bars may be provided that are arranged on opposite sides of a die singulation saw cut line defined in a scribe band on a semiconductor wafer.
摘要翻译：具有集成的模具隔离保护屏障的半导体测试焊盘互连结构。互连结构包括多个堆叠的金属层，每个层具有通过介电材料层与其它测试焊盘分离的导电测试焊盘。在一个实施例中，至少一个金属通孔条被嵌入到互连结构中，并将金属层中的每个测试焊盘电连接在一起。在一些实施例中，通孔棒基本上沿着由每个测试垫限定的整个第一侧面延伸。在其他实施例中，可以提供一对相对的通孔条，其布置在限定在半导体晶片上的划线带中的模切单切锯切线的相对侧上。

64. 发明申请

US20110127648A1 Heat Spreader Structures in Scribe Lines 有权
标题翻译：散热器结构在划线
公开(公告)号：US20110127648A1
公开(公告)日：2011-06-02
申请号：US13023151
申请日：2011-02-08
申请人： Hsien-Wei Chen , Yu-Wen Liu , Jyh-Cherng Sheu , Hao-Yi Tsai , Shin-Puu Jeng , Chen-Hua Yu , Shang-Yun Hou
发明人： Hsien-Wei Chen , Yu-Wen Liu , Jyh-Cherng Sheu , Hao-Yi Tsai , Shin-Puu Jeng , Chen-Hua Yu , Shang-Yun Hou
IPC分类号： H01L23/544 , H01L23/34
CPC分类号： H01L23/3677 , B23K26/364 , B23K26/40 , B23K2103/172 , H01L21/78 , H01L22/34 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a first chip including a first edge; and a second chip having a second edge facing the first edge. A scribe line is between and adjoining the first edge and the second edge. A heat spreader includes a portion in the scribe line, wherein the heat spreader includes a plurality of vias and a plurality of metal lines. The portion of the heat spreader in the scribe line has a second length at least close to, or greater than, a first length of the first edge.
摘要翻译：集成电路结构包括：第一芯片，包括第一边缘; 以及具有面向第一边缘的第二边缘的第二芯片。划线在第一边缘和第二边缘之间并相邻。散热器包括划线中的一部分，其中散热器包括多个通孔和多个金属线。散热器在划线中的部分具有至少接近或大于第一边缘的第一长度的第二长度。

65. 发明授权

US07936067B2 Backend interconnect scheme with middle dielectric layer having improved strength 有权
标题翻译：具有中等介电层的后端互连方案具有改进的强度
公开(公告)号：US07936067B2
公开(公告)日：2011-05-03
申请号：US12121541
申请日：2008-05-15
申请人： Hao-Yi Tsai , Yu-Wen Liu , Hsien-Wei Chen , Ying-Ju Chen , Shin-Puu Jeng
发明人： Hao-Yi Tsai , Yu-Wen Liu , Hsien-Wei Chen , Ying-Ju Chen , Shin-Puu Jeng
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76835 , H01L23/5222 , H01L23/5329 , H01L24/05 , H01L2224/02166 , H01L2224/05093 , H01L2224/05556 , H01L2924/14 , H01L2924/00
摘要： An integrated circuit structure includes a first, a second and a third metallization layer. The first metallization layer includes a first dielectric layer having a first k value; and first metal lines in the first dielectric layer. The second metallization layer is over the first metallization layer, and includes a second dielectric layer having a second k value greater than the first k value; and second metal lines in the second dielectric layer. The third metallization layer is over the second metallization layer, and includes a third dielectric layer having a third k value; and third metal lines in the third dielectric layer. The integrated circuit structure further includes a bottom passivation layer over the third metallization layer.
摘要翻译：集成电路结构包括第一，第二和第三金属化层。第一金属化层包括具有第一k值的第一介电层; 和第一介电层中的第一金属线。第二金属化层在第一金属化层之上，并且包括具有大于第一k值的第二k值的第二介电层; 和第二介电层中的第二金属线。第三金属化层在第二金属化层之上，并且包括具有第三k值的第三介电层; 和第三介电层中的第三金属线。集成电路结构还包括在第三金属化层上的底部钝化层。

66. 发明授权

US07906836B2 Heat spreader structures in scribe lines 有权
标题翻译：散热器结构在划线
公开(公告)号：US07906836B2
公开(公告)日：2011-03-15
申请号：US12347184
申请日：2008-12-31
申请人： Hsien-Wei Chen , Yu-Wen Liu , Jyh-Cherng Sheu , Hao-Yi Tsai , Shin-Puu Jeng , Chen-Hua Yu , Shang-Yun Hou
发明人： Hsien-Wei Chen , Yu-Wen Liu , Jyh-Cherng Sheu , Hao-Yi Tsai , Shin-Puu Jeng , Chen-Hua Yu , Shang-Yun Hou
IPC分类号： H01L23/34
CPC分类号： H01L23/3677 , B23K26/364 , B23K26/40 , B23K2103/172 , H01L21/78 , H01L22/34 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a first chip including a first edge; and a second chip having a second edge facing the first edge. A scribe line is between and adjoining the first edge and the second edge. A heat spreader includes a portion in the scribe line, wherein the heat spreader includes a plurality of vias and a plurality of metal lines. The portion of the heat spreader in the scribe line has a second length at least close to, or greater than, a first length of the first edge.
摘要翻译：集成电路结构包括：第一芯片，包括第一边缘; 以及具有面向第一边缘的第二边缘的第二芯片。划线在第一边缘和第二边缘之间并相邻。散热器包括划线中的一部分，其中散热器包括多个通孔和多个金属线。散热器在划线中的部分具有至少接近或大于第一边缘的第一长度的第二长度。

67. 发明授权

US07776627B2 Flexible structures for interconnect reliability test 有权
标题翻译：用于互连可靠性测试的柔性结构
公开(公告)号：US07776627B2
公开(公告)日：2010-08-17
申请号：US11971072
申请日：2008-01-08
申请人： Shin-Puu Jeng , Shang-Yun Hou , Hao-Yi Tsai , Anbiarshy N. F. Wu
发明人： Shin-Puu Jeng , Shang-Yun Hou , Hao-Yi Tsai , Anbiarshy N. F. Wu
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an integrated circuit structure includes forming a test wafer. The step of forming the test wafer includes providing a first semiconductor substrate; and forming a first plurality of unit blocks over the first semiconductor substrate. Each of the first plurality of unit blocks includes a plurality of connection block cells arranged as an array. Each of the connection block cells includes two connection blocks, and a metal line connecting the two connection blocks. The method further includes forming a plurality of unit block boundary lines separating the first plurality of unit blocks from each other; and forming a first plurality of metal lines connecting a portion of the first plurality of unit blocks.
摘要翻译：一种用于形成集成电路结构的方法包括形成测试晶片。形成测试晶片的步骤包括提供第一半导体衬底; 以及在所述第一半导体衬底上形成第一多个单元块。第一多个单元块中的每一个包括被排列成阵列的多个连接块单元。每个连接块单元包括两个连接块和连接两个连接块的金属线。该方法还包括形成将第一多个单元块彼此分离的多个单元块边界线; 以及形成连接所述第一多个单元块的一部分的第一多个金属线。

68. 发明申请

US20100187687A1 Underbump Metallization Structure 有权
标题翻译：底部金属化结构
公开(公告)号：US20100187687A1
公开(公告)日：2010-07-29
申请号：US12619503
申请日：2009-11-16
申请人： Yu-Wen Liu , Hao-Yi Tsai , Hsien-Wei Chen , Shin-Puu Jeng , Ying-Ju Chen , Shang-Yun Hou , Pei-Haw Tsao , Chen-Hua Yu
发明人： Yu-Wen Liu , Hao-Yi Tsai , Hsien-Wei Chen , Shin-Puu Jeng , Ying-Ju Chen , Shang-Yun Hou , Pei-Haw Tsao , Chen-Hua Yu
IPC分类号： H01L23/488 , H01L21/60
CPC分类号： H01L24/05 , H01L23/3157 , H01L24/03 , H01L24/11 , H01L24/13 , H01L2224/02125 , H01L2224/0215 , H01L2224/0345 , H01L2224/03462 , H01L2224/0401 , H01L2224/05018 , H01L2224/05027 , H01L2224/0508 , H01L2224/05096 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05541 , H01L2224/05552 , H01L2224/05553 , H01L2224/05557 , H01L2224/05558 , H01L2224/05566 , H01L2224/05569 , H01L2224/05572 , H01L2224/05573 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/1132 , H01L2224/11334 , H01L2224/1145 , H01L2224/11462 , H01L2224/11849 , H01L2224/13005 , H01L2224/13007 , H01L2224/13111 , H01L2224/13139 , H01L2224/13147 , H01L2924/00013 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/05042 , H01L2924/05442 , H01L2924/00014 , H01L2924/2064 , H01L2224/13099 , H01L2224/05099 , H01L2224/13599 , H01L2224/05599 , H01L2224/29099 , H01L2224/29599
摘要： A system and method for forming an underbump metallization (UBM) is presented. A preferred embodiment includes a raised UBM which extends through a passivation layer so as to make contact with a contact pad while retaining enough of the passivation layer between the contact pad and the UBM to adequately handle the peeling and shear stress that results from CTE mismatch and subsequent thermal processing. The UBM contact is preferably formed in either an octagonal ring shape or an array of contacts.
摘要翻译：提出了一种用于形成底部金属化（UBM）的系统和方法。优选实施例包括凸起的UBM，其延伸穿过钝化层以便与接触焊盘接触，同时在接触焊盘和UBM之间保留足够的钝化层以充分地处理由CTE失配引起的剥离和剪切应力，后续热处理。 UBM触点优选地形成为八边形环形或触点阵列。

69. 发明授权

US07679384B2 Parametric testline with increased test pattern areas 有权
标题翻译：参数测试线具有增加的测试图案区域
公开(公告)号：US07679384B2
公开(公告)日：2010-03-16
申请号：US11811135
申请日：2007-06-08
申请人： Hsien-Wei Chen , Shih-Hsun Hsu , Hao-Yi Tsai , Shin-Puu Jeng
发明人： Hsien-Wei Chen , Shih-Hsun Hsu , Hao-Yi Tsai , Shin-Puu Jeng
IPC分类号： G01R31/26
CPC分类号： G01R31/2884 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit parametric testline providing increased test pattern areas is disclosed. The testline comprises a dielectric layer over a substrate, a plurality of probe pads over the dielectric layer, and a first device under test (DUT) formed in the testline in a space underlying the probe pads. The testline may also include a second DUT, which is formed in a space underlying the probe pads overlying the first DUT in an overlaying configuration. The testline may further include a polygon shaped probe pad structure providing an increased test pattern area between adjacent probe pads.
摘要翻译：公开了一种提供增加的测试图案区域的集成电路参数测试线。测试线包括衬底上的电介质层，电介质层上的多个探针焊盘，以及形成在探针焊盘下方空间中的测试线中的第一被测器件（DUT）。测试线还可以包括第二DUT，其以覆盖配置形成在覆盖第一DUT的探针焊盘下方的空间中。测试线还可以包括多边形形状的探针焊盘结构，其提供相邻探针焊盘之间增加的测试图案区域。

70. 发明申请

US20100052065A1 NEW METHOD FOR MECHANICAL STRESS ENHANCEMENT IN SEMICONDUCTOR DEVICES 有权
标题翻译：用于半导体器件中的机械应力增强的新方法
公开(公告)号：US20100052065A1
公开(公告)日：2010-03-04
申请号：US12391821
申请日：2009-02-24
申请人： Carlos H. Diaz , Yi-Ming Sheu , Anson Wang , Kong-Beng Thei , Sheng-Chen Chung , Hao-Yi Tsai , Hsien-Wei Chen , Harry Hak-Lay Chuang , Shin-Puu Jeng
发明人： Carlos H. Diaz , Yi-Ming Sheu , Anson Wang , Kong-Beng Thei , Sheng-Chen Chung , Hao-Yi Tsai , Hsien-Wei Chen , Harry Hak-Lay Chuang , Shin-Puu Jeng
IPC分类号： H01L27/092
CPC分类号： H01L21/823807 , H01L21/823828 , H01L27/0207 , H01L29/165 , H01L29/66628 , H01L29/7848
摘要： The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate having an active region; at least one operational device on the active region, wherein the operational device include a strained channel; and at least one first dummy gate disposed at a side of the operational device and on the active region.
摘要翻译：本发明提供集成电路。集成电路包括具有有源区的半导体衬底; 所述活动区域上的至少一个操作装置，其中所述操作装置包括应变通道; 以及设置在所述操作装置的一侧和所述有源区域上的至少一个第一伪栅极。

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