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61. 发明授权

US06852652B1 Method of making relaxed silicon-germanium on glass via layer transfer 失效
标题翻译：通过层转移在玻璃上制备松弛的硅 - 锗的方法
公开(公告)号：US06852652B1
公开(公告)日：2005-02-08
申请号：US10674369
申请日：2003-09-29
申请人： Jer-Shen Maa , Jong-Jan Lee , Douglas J. Tweet , Steve Roy Droes
发明人： Jer-Shen Maa , Jong-Jan Lee , Douglas J. Tweet , Steve Roy Droes
IPC分类号： C23C14/48 , H01L21/00 , H01L21/02 , H01L21/20 , H01L21/336 , H01L21/762 , H01L27/12 , H01L29/786
CPC分类号： H01L21/76254 , Y10S438/933
摘要： A method of forming a silicon-germanium layer on an insulator includes preparing a silicon substrate; depositing a layer of silicon-germanium on the silicon substrate to form a silicon/silicon-germanium portion; implanting hydrogen ions in the silicon-germanium layer; preparing an insulator substrate; bonding the silicon/silicon-germanium portion to the insulator substrate with the silicon-germanium layer in contact with the insulator substrate to form a bonded entity; curing the bonded entity; and thermally annealing the bonded entity to split the bonded entity into a silicon/silicon germanium portion and a silicon-germanium-on-insulator portion and to relax the silicon germanium layers.
摘要翻译：在绝缘体上形成硅 - 锗层的方法包括制备硅衬底; 在硅衬底上沉积一层硅 - 锗以形成硅/硅 - 锗部分; 在硅 - 锗层中注入氢离子; 制备绝缘体基板; 将硅/锗锗部分接合到绝缘体衬底，硅 - 锗层与绝缘体衬底接触以形成键合实体; 养护保税实体; 以及对所述结合的实体进行热退火以将所述结合的实体分裂成硅/硅锗部分和绝缘体上的硅 - 锗部分并使所述硅锗层松弛。

62. 发明授权

US07405098B2 Smooth surface liquid phase epitaxial germanium 有权
标题翻译：光滑表面液相外延锗
公开(公告)号：US07405098B2
公开(公告)日：2008-07-29
申请号：US11339017
申请日：2006-01-25
申请人： Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet , David R. Evans , Allen Burmaster
发明人： Jong-Jan Lee , Jer-Shen Maa , Douglas J. Tweet , David R. Evans , Allen Burmaster
IPC分类号： H01L21/00 , H01L21/84 , H01L21/331 , H01L21/76 , H01L21/20 , H01L21/36
CPC分类号： C30B19/00 , C30B29/08 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02623 , H01L21/02639 , H01L21/30625 , H01L21/7624 , H01L27/14683 , H01L27/14689 , H01L29/16 , H01L29/78 , H01L31/028 , H01L31/105 , H01L31/1126 , H01L31/1136 , H01L31/1804 , H01L31/1808 , Y02E10/547 , Y02P70/521
摘要： A method is provided for forming a liquid phase epitaxial (LPE) germanium (Ge)-on-insulator (GOI) thin-film with a smooth surface. The method provides a silicon (Si) wafer, forms a silicon nitride insulator layer overlying the Si wafer, and selectively etches the silicon nitride insulator layer, forming a Si seed access region. Then, the method conformally deposits Ge overlying the silicon nitride insulator layer and Si seed access region, forming a Ge layer with a first surface roughness, and smoothes the Ge layer using a chemical-mechanical polish (CMP) process. Typically, the method encapsulates the Ge layer and anneals the Ge layer to form a LPE Ge layer. A Ge layer is formed with a second surface roughness, less than the first surface roughness. In some aspects, the method forms an active device in the LPE Ge layer.
摘要翻译：提供一种形成具有光滑表面的液相外延（LPE）锗（Ge） - 绝缘体（GOI）薄膜的方法。该方法提供硅（Si）晶片，形成覆盖Si晶片的氮化硅绝缘体层，并且选择性地蚀刻氮化硅绝缘体层，形成Si种子接入区域。然后，该方法共同沉积覆盖氮化硅绝缘体层和Si种子访问区域的Ge，形成具有第一表面粗糙度的Ge层，并且使用化学机械抛光（CMP）工艺平滑Ge层。通常，该方法封装Ge层并退火Ge层以形成LPE Ge层。 Ge层形成有小于第一表面粗糙度的第二表面粗糙度。在某些方面，该方法在LPE Ge层中形成有源器件。

63. 发明授权

US07030002B2 Low temperature anneal to reduce defects in hydrogen-implanted, relaxed SiGe layer 有权
标题翻译：低温退火以减少氢注入，弛豫SiGe层的缺陷
公开(公告)号：US07030002B2
公开(公告)日：2006-04-18
申请号：US10780929
申请日：2004-02-17
申请人： Douglas J. Tweet , Jong-Jan Lee , Jer-Shen Maa
发明人： Douglas J. Tweet , Jong-Jan Lee , Jer-Shen Maa
IPC分类号： H01L21/28 , H01L21/13205 , H01L21/00 , H01L21/84 , H01L21/36
CPC分类号： H01L21/02381 , H01L21/0245 , H01L21/02502 , H01L21/02532 , H01L21/02694 , H01L21/324 , H01L21/3247
摘要： A method of forming a SiGe layer having a relatively high Ge content includes preparing a silicon substrate; depositing a layer of SiGe to a thickness of between about 100 nm to 500 nm, wherein the Ge content of the SiGe layer is equal to or greater than 10%, implanting H2+ ions through the SiGe layer into the substrate at a dose of between about 2×1014 cm−2 to 2×1016 cm−2, at an energy of between about 20 keV to 100+ keV; low temperature thermal annealing at a temperature of between about 200° C. to 400° C. for between about ten minutes and ten hours; high temperature thermal annealing the substrate and SiGe layer, to relax the SiGe layer, in an inert atmosphere at a temperature of between about 650° C. to 1000° C. for between about 30 seconds and 30 minutes; and depositing a layer of silicon-based material on the relaxed SiGe layer to a thickness of between about 5 nm to 30 nm.
摘要翻译：形成Ge含量较高的SiGe层的方法包括制备硅衬底; 将SiGe层沉积至约100nm至500nm的厚度，其中SiGe层的Ge含量等于或大于10％，注入H 2 O + SUP +离子通过SiGe层以约2×10 14 cm -2至2×10 16 cm -3的剂量进入衬底，在约20keV至100eKeV之间的能量; 在约200℃至400℃的温度下进行约10分钟至10小时的低温热退火; 在惰性气氛中，在约650℃至1000℃的温度下，在约30秒至30分钟之间，使衬底和SiGe层进行高温热退火以使SiGe层松弛; 以及在松弛的SiGe层上沉积一层硅基材料至约5nm至30nm的厚度。

64. 发明授权

US07608874B2 Fully isolated photodiode stack 失效
标题翻译：全隔离光电二极管堆叠
公开(公告)号：US07608874B2
公开(公告)日：2009-10-27
申请号：US11657152
申请日：2007-01-24
申请人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L31/062 , H01L31/113
CPC分类号： H01L27/14647 , H01L27/1463 , H01L27/14689
摘要： An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, together with an associated fabrication method. The method provides a bulk silicon (Si) substrate. A plurality of color imager cells are formed, either in the Si substrate, or in a single epitaxial Si layer formed over the substrate. Each color imager cell includes a photodiode set with a first, second, and third photodiode formed as a stacked multi-junction structure. A U-shaped (in cross-section) well liner, fully isolates the photodiode set from adjacent photodiode sets in the array. For example, each photodiode is formed from a p doped Si layer physically interfaced to a first wall. A well bottom physically interfaces to the first wall, and the p doped Si layer of the third, bottom-most, photodiode is part of the well bottom. Then, the photodiode sets may be formed from an n/p/n/p/n/p or n/p/p−/p/p−/p layered structure.
摘要翻译：提供了完全隔离的多结互补金属氧化物半导体（CMOS）无滤膜彩色成像器单元的阵列，以及相关的制造方法。该方法提供体硅（Si）衬底。在Si衬底中或在衬底上形成的单个外延Si层中形成多个彩色成像器单元。每个彩色成像器单元包括具有形成为堆叠多结结构的第一，第二和第三光电二极管。 U形（横截面）井衬管，将阵列中的光电二极管组与相邻的光电二极管组完全隔离。例如，每个光电二极管由物理上与第一壁物理连接的p掺杂Si层形成。阱底部与第一壁物理接口，第三，最底部的光电二极管的p掺杂Si层是阱底部的一部分。然后，光电二极管组可以由n / p / n / p / n / p或n / p / p / p / p / p层叠结构形成。

65. 发明授权

US07651883B2 High energy implant photodiode stack 失效
标题翻译：高能注入光电二极管叠层
公开(公告)号：US07651883B2
公开(公告)日：2010-01-26
申请号：US11801320
申请日：2007-05-09
申请人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L21/00
CPC分类号： H01L27/14647 , H01L27/1463 , H01L27/14689
摘要： An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, with a corresponding fabrication process. The color imager cell array is formed from a bulk silicon (Si) substrate without an overlying epitaxial Si layer. A plurality of color imager cells are formed in the bulk Si substrate, where each color imager cell includes a photodiode set and a U-shaped well liner. The photodiode set includes first, second, and third photodiode formed as a stacked multi-junction structure, while the U-shaped well liner fully isolates the photodiode set from adjacent photodiode sets in the array. The U-shaped well liner includes a physically interfacing doped well liner bottom and first wall. The well liner bottom is interposed between the substrate and the photodiode set, and the first wall physically interfaces each doped layer of each photodiode in the photodiode set.
摘要翻译：提供了完全隔离的多结互补金属氧化物半导体（CMOS）无滤膜彩色成像器单元的阵列，具有相应的制造工艺。彩色成像器单元阵列由体硅（Si）衬底形成，而不具有上覆的外延Si层。在本体Si衬底中形成多个彩色成像器单元，其中每个彩色成像器单元包括光电二极管组和U形衬管。光电二极管组包括形成为堆叠多结结构的第一，第二和第三光电二极管，而U形阱衬套将光电二极管组与阵列中的相邻光电二极管组完全隔离。 U形井衬管包括物理接口掺杂的井筒底部和第一壁。阱衬底位于衬底和光电二极管组之间，并且第一壁物理地连接光电二极管组中每个光电二极管的每个掺杂层。

66. 发明申请

US20070218613A1 Fully isolated photodiode stack 失效
标题翻译：完全隔离的光电二极管堆叠
公开(公告)号：US20070218613A1
公开(公告)日：2007-09-20
申请号：US11657152
申请日：2007-01-24
申请人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L21/8234
CPC分类号： H01L27/14647 , H01L27/1463 , H01L27/14689
摘要： An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, together with an associated fabrication method. The method provides a bulk silicon (Si) substrate. A plurality of color imager cells are formed, either in the Si substrate, or in a single epitaxial Si layer formed over the substrate. Each color imager cell includes a photodiode set with a first, second, and third photodiode formed as a stacked multi-junction structure. A U-shaped (in cross-section) well liner, fully isolates the photodiode set from adjacent photodiode sets in the array. For example, each photodiode is formed from a p doped Si layer physically interfaced to a first wall. A well bottom physically interfaces to the first wall, and the p doped Si layer of the third, bottom-most, photodiode is part of the well bottom. Then, the photodiode sets may be formed from an n/p/n/p/n/p or n/p/p−/p/p−/p layered structure.
摘要翻译：提供了完全隔离的多结互补金属氧化物半导体（CMOS）无滤膜彩色成像器单元的阵列，以及相关的制造方法。该方法提供体硅（Si）衬底。在Si衬底中或在衬底上形成的单个外延Si层中形成多个彩色成像器单元。每个彩色成像器单元包括具有形成为堆叠多结结构的第一，第二和第三光电二极管。 U形（横截面）井衬管，将阵列中的光电二极管组与相邻的光电二极管组完全隔离。例如，每个光电二极管由物理上与第一壁物理连接的p掺杂Si层形成。阱底部与第一壁物理接口，第三，最底部的光电二极管的p掺杂Si层是阱底部的一部分。然后，光电二极管组可以由n / p / n / p / n / p或n / p / p / p / p / p层叠结构形成。

67. 发明申请

US20080277701A1 High energy implant photodiode stack 失效
标题翻译：高能注入光电二极管叠层
公开(公告)号：US20080277701A1
公开(公告)日：2008-11-13
申请号：US11801320
申请日：2007-05-09
申请人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
发明人： Jong-Jan Lee , Douglas J. Tweet , Sheng Teng Hsu
IPC分类号： H01L31/113 , H01L31/18
CPC分类号： H01L27/14647 , H01L27/1463 , H01L27/14689
摘要： An array of fully isolated multi-junction complimentary metal-oxide-semiconductor (CMOS) filterless color imager cells is provided, with a corresponding fabrication process. The color imager cell array is formed from a bulk silicon (Si) substrate without an overlying epitaxial Si layer. A plurality of color imager cells are formed in the bulk Si substrate, where each color imager cell includes a photodiode set and a U-shaped well liner. The photodiode set includes first, second, and third photodiode formed as a stacked multifunction structure, while the U-shaped well liner fully isolates the photodiode set from adjacent photodiode sets in the array. The U-shaped well liner includes a physically interfacing doped well liner bottom and first wall. The well liner bottom is interposed between the substrate and the photodiode set, and the first wall physically interfaces each doped layer of each photodiode in the photodiode set.
摘要翻译：提供了完全隔离的多结互补金属氧化物半导体（CMOS）无滤膜彩色成像器单元的阵列，具有相应的制造工艺。彩色成像器单元阵列由体硅（Si）衬底形成，而不具有上覆的外延Si层。在本体Si衬底中形成多个彩色成像器单元，其中每个彩色成像器单元包括光电二极管组和U形衬管。光电二极管组包括形成为堆叠的多功能结构的第一，第二和第三光电二极管，而U形阱衬套将光电二极管组与阵列中的相邻光电二极管组完全隔离。 U形井衬管包括物理接口掺杂的井筒底部和第一壁。阱衬底位于衬底和光电二极管组之间，并且第一壁物理地连接光电二极管组中每个光电二极管的每个掺杂层。

68. 发明授权

US06627510B1 Method of making self-aligned shallow trench isolation 有权
标题翻译：自对准浅沟槽隔离方法
公开(公告)号：US06627510B1
公开(公告)日：2003-09-30
申请号：US10112014
申请日：2002-03-29
申请人： David R. Evans , Sheng Teng Hsu , Bruce D. Ulrich , Douglas J. Tweet , Lisa H. Stecker
发明人： David R. Evans , Sheng Teng Hsu , Bruce D. Ulrich , Douglas J. Tweet , Lisa H. Stecker
IPC分类号： H01L21762
CPC分类号： H01L21/28194 , H01L21/76224 , H01L21/823481 , H01L29/517 , H01L29/518 , Y10S438/975
摘要： A modified STI process is provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. An alignment key may be formed by selectively etching the oxide layer. A third polysilicon layer may then be deposited and patterned using photoresist to form a gate structure. During patterning, exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer. A thin layer of the first polysilicon layer remains, to be carefully removed using a subsequent selective etch process.
摘要翻译：提供了一种改进的STI工艺，包括在衬底上形成第一多晶硅层。通过第一多晶硅层形成沟槽并进入衬底，并用氧化物层填充沟槽。在氧化物上沉积第二多晶硅层，使得沟槽内的第二多晶硅层的底部高于第一多晶硅层的底部，并且沟槽内的第二多晶硅层的顶部低于第一多晶硅的顶部层。然后可以使用CMP工艺将得到的结构平坦化。可以通过选择性地蚀刻氧化物层来形成对准键。然后可以使用光致抗蚀剂沉积和图案化第三多晶硅层以形成栅极结构。在图案化期间，蚀刻暴露的第二多晶硅层。在完成去除第二多晶硅层时检测到蚀刻停止。保留第一多晶硅层的薄层，使用随后的选择性蚀刻工艺小心地去除。

69. 发明授权

US07364989B2 Strain control of epitaxial oxide films using virtual substrates 有权
标题翻译：使用虚拟衬底的外延氧化膜的应变控制
公开(公告)号：US07364989B2
公开(公告)日：2008-04-29
申请号：US11174350
申请日：2005-07-01
申请人： Douglas J. Tweet , Yoshi Ono , David R. Evans , Sheng Teng Hsu
发明人： Douglas J. Tweet , Yoshi Ono , David R. Evans , Sheng Teng Hsu
IPC分类号： H01L21/20
CPC分类号： H01L21/02192 , H01L21/02197 , H01L21/0228 , H01L21/3147
摘要： A method of controlling strain in a single-crystal, epitaxial oxide film, includes preparing a silicon substrate; forming a silicon alloy layer taken from the group of silicon alloy layer consisting of Si1-xGex and Si1-yCy on the silicon substrate; adjusting the lattice constant of the silicon alloy layer by selecting the alloy material content to adjust and to select a type of strain for the silicon alloy layer; depositing a single-crystal, epitaxial oxide film, by atomic layer deposition, taken from the group of oxide films consisting of perovskite manganite materials, single crystal rare-earth oxides and perovskite oxides, not containing manganese; and rare earth binary and ternary oxides, on the silicon alloy layer; and completing a desired device.
摘要翻译：一种控制单晶外延氧化膜中的应变的方法包括制备硅衬底; 从由Si 1-x Ge x Si和Si 1-y C C组成的硅合金层组形成硅合金层 > y ; 通过选择合金材料含量来调整硅合金层的晶格常数，并选择一种用于硅合金层的应变; 从由不含锰的钙钛矿亚锰酸盐材料，单晶稀土氧化物和钙钛矿氧化物组成的氧化膜组中，通过原子层沉积法沉积单晶外延氧化膜; 和稀土二元和三元氧化物，在硅合金层上; 并完成所需的设备。

70. 发明授权

US06716691B1 Self-aligned shallow trench isolation process having improved polysilicon gate thickness control 有权
标题翻译：具有改进的多晶硅栅极厚度控制的自对准浅沟槽隔离工艺
公开(公告)号：US06716691B1
公开(公告)日：2004-04-06
申请号：US10606105
申请日：2003-06-25
申请人： David R. Evans , Sheng Teng Hsu , Bruce D. Ulrich , Douglas J. Tweet , Lisa H. Stecker
发明人： David R. Evans , Sheng Teng Hsu , Bruce D. Ulrich , Douglas J. Tweet , Lisa H. Stecker
IPC分类号： H01L218238
CPC分类号： H01L21/76224 , H01L21/28123 , H01L21/823878
摘要： A method of fabricating a CMOS have self-aligned shallow trench isolation, includes preparing a silicon substrate; forming a gate stack; depositing a layer of first polysilicon; trenching the substrate by shallow trench isolation to form a trench; filling the trench with oxide; depositing a second layer of polysilicon wherein the top surface of the second polysilicon layer is above the top surface of the first polysilicon layer; depositing a sacrificial oxide layer having a thickness of at least 1.5× that of the first polysilicon layer; CMP the sacrificial oxide layer to the level of the upper surface of the second polysilicon layer; depositing a third layer of polysilicon; patterning and etching the gate stack; implanting ions to form a source region, a drain region and the polysilicon gate; and completing the CMOS structure.
摘要翻译：制造CMOS的方法具有自对准浅沟槽隔离，包括制备硅衬底; 形成栅极叠层; 沉积第一多晶硅层; 通过浅沟槽隔离对衬底进行沟槽以形成沟槽; 用氧化物填充沟槽; 沉积第二多晶硅层，其中第二多晶硅层的顶表面在第一多晶硅层的顶表面之上; 沉积厚度至少为第一多晶硅层的1.5倍的牺牲氧化物层; 将牺牲氧化物层CMP CMP化为第二多晶硅层的上表面的水平; 沉积第三层多晶硅; 图案化和蚀刻栅极堆叠; 注入离子以形成源极区，漏极区和多晶硅栅; 并完成CMOS结构。

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