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61. 发明申请

US20070167008A1 Nanotip electrode non-volatile memory resistor cell 审中-公开
标题翻译：纳米电极非易失性存储电阻单元
公开(公告)号：US20070167008A1
公开(公告)日：2007-07-19
申请号：US11717818
申请日：2007-03-14
申请人： Sheng Hsu , Fengyan Zhang , Gregory Stecker , Robert Barrowcliff
发明人： Sheng Hsu , Fengyan Zhang , Gregory Stecker , Robert Barrowcliff
IPC分类号： H01L21/44
CPC分类号： H01L27/101 , H01L45/04 , H01L45/1233 , H01L45/1273 , H01L45/147 , H01L45/16 , H01L45/1675
摘要： A non-volatile memory resistor cell with a nanotip electrode, and corresponding fabrication method are provided. The method comprises: forming a first electrode with nanotips; forming a memory resistor material adjacent the nanotips; and, forming a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between the first and second electrodes. Typically, the nanotips are iridium oxide (IrOx) and have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. In one aspect, the substrate material can be silicon, silicon oxide, silicon nitride, or a noble metal. A metalorganic chemical vapor deposition (MOCVD) process is used to deposit Ir. The IrOx nanotips are grown from the deposited Ir.
摘要翻译：提供了具有纳米尖端电极的非易失性存储器电阻单元及相应的制造方法。该方法包括：形成具有纳米尖端的第一电极; 在所述纳米尖端附近形成记忆电阻材料; 并且形成与所述存储电阻材料相邻的第二电极，其中所述存储电阻材料置于所述第一和第二电极之间。通常，纳米针是氧化铱（IrOx），并且具有约50纳米或更小的尖端基底尺寸，在5至50nm范围内的尖端高度，以及每平方微米大于100纳米尖端的纳米密度密度。一方面，衬底材料可以是硅，氧化硅，氮化硅或贵金属。使用金属有机化学气相沉积（MOCVD）工艺沉积Ir。 IrOx纳米尖端从沉积的Ir生长。

62. 发明申请

US20070111368A1 Photovoltaic structure with a conductive nanowire array electrode 失效
标题翻译：具有导电纳米线阵列电极的光伏结构
公开(公告)号：US20070111368A1
公开(公告)日：2007-05-17
申请号：US11280423
申请日：2005-11-16
申请人： Fengyan Zhang , Robert Barrowcliff , Sheng Hsu
发明人： Fengyan Zhang , Robert Barrowcliff , Sheng Hsu
IPC分类号： H01L51/40 , H01L21/00
CPC分类号： H01L51/4213 , B82Y10/00 , H01L51/0046 , H01L51/0048 , H01L51/4226 , H01L51/4233 , H01L51/441 , Y02E10/52 , Y02E10/549
摘要： A photovoltaic (PV) structure is provided, along with a method for forming a PV structure with a conductive nanowire array electrode. The method comprises: forming a bottom electrode with conductive nanowires; forming a first semiconductor layer of a first dopant type (i.e., n-type) overlying the nanowires; forming a second semiconductor layer of a second dopant type, opposite of the first dopant type (i.e., p-type), overlying the first semiconductor layer; and, forming a top electrode overlying the second semiconductor layer. The first and second semiconductor layers can be a material such as a conductive polymer, a conjugated polymer with a fullerene derivative, and inorganic materials such as CdSe, CdS, Titania, or ZnO. The conductive nanowires can be a material such as IrO2, In2O3, SnO2, or indium tin oxide (ITO).
摘要翻译：提供光伏（PV）结构以及用于形成具有导电纳米线阵列电极的PV结构的方法。该方法包括：形成具有导电纳米线的底电极; 形成覆盖在纳米线上的第一掺杂剂型（即n型）的第一半导体层; 形成与所述第一掺杂剂类型（即，p型）相反的第二掺杂剂类型的第二半导体层，所述第二掺杂剂类型覆盖所述第一半导体层; 以及形成覆盖所述第二半导体层的顶部电极。第一和第二半导体层可以是诸如导电聚合物，具有富勒烯衍生物的共轭聚合物和诸如CdSe，CdS，二氧化钛或ZnO的无机材料的材料。导电纳米线可以是诸如IrO 2，In 2 O 3，SnO 2，或铟的材料氧化锡（ITO）。

63. 发明申请

US20070108502A1 Nanocrystal silicon quantum dot memory device 审中-公开
标题翻译：纳米晶硅量子点存储器件
公开(公告)号：US20070108502A1
公开(公告)日：2007-05-17
申请号：US11281955
申请日：2005-11-17
申请人： Tingkai Li , Sheng Hsu , Lisa Stecker
发明人： Tingkai Li , Sheng Hsu , Lisa Stecker
IPC分类号： H01L29/788 , H01L21/336 , G11C16/04
CPC分类号： H01L29/7881 , B82Y10/00 , G11C16/349 , G11C16/3495 , G11C2216/08 , H01L29/15 , H01L29/40114 , H01L29/42324 , H01L29/4925 , H01L29/66825
摘要： A nanocrystal silicon (Si) quantum dot memory device and associated fabrication method have been provided. The method comprises: forming a gate (tunnel) oxide layer overlying a Si substrate active layer; forming a nanocrystal Si memory film overlying the gate oxide layer, including a polycrystalline Si (poly-Si)/Si dioxide stack; forming a control Si oxide layer overlying the nanocrystal Si memory film; forming a gate electrode overlying the control oxide layer; and, forming source/drain regions in the Si active layer. In one aspect, the nanocrystal Si memory film is formed by depositing a layer of amorphous Si (a-Si) using a chemical vapor deposition (CVD) process, and thermally oxidizing a portion of the a-Si layer. Typically, the a-Si deposition and oxidation processes are repeated, forming a plurality of poly-Si/Si dioxide stacks (i.e., 2 to 5 poly-Si/Si dioxide stacks).
摘要翻译：已经提供了纳米晶体硅（Si）量子点存储器件和相关的制造方法。该方法包括：形成覆盖Si衬底有源层的栅极（隧道）氧化层; 形成覆盖栅极氧化物层的纳米晶Si记忆膜，包括多晶Si（多晶硅）/二氧化硅叠层; 形成覆盖在纳米晶Si记忆膜上的对照Si氧化物层; 形成覆盖所述控制氧化物层的栅电极; 并且在Si有源层中形成源/漏区。在一个方面，通过使用化学气相沉积（CVD）工艺沉积非晶硅层（a-Si）并热氧化a-Si层的一部分来形成纳米晶体Si记忆膜。通常，重复a-Si沉积和氧化过程，形成多个多Si /二氧化硅叠层（即2至5个多硅/二氧化硅叠层）。

64. 发明申请

US20070015330A1 Metal/semiconductor/metal (MSM) back-to-back Schottky diode 有权
标题翻译：金属/半导体/金属（MSM）背对背肖特基二极管
公开(公告)号：US20070015330A1
公开(公告)日：2007-01-18
申请号：US11435669
申请日：2006-05-17
申请人： Tingkai Li , Sheng Hsu , David Evans
发明人： Tingkai Li , Sheng Hsu , David Evans
IPC分类号： H01L21/8242
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.
摘要翻译：提供了用于从硅（Si）半导体形成金属/半导体/金属（MSM）背对背肖特基二极管的方法。该方法在底电极和顶电极之间沉积Si半导体层，并形成具有阈值电压，击穿电压和开/关电流比的MSM二极管。响应于控制Si半导体层厚度，该方法能够修改MSM二极管的阈值电压，击穿电压和导通/截止电流比。通常，响应于Si厚度的增加，阈值和击穿电压都增加。关于开/关电流比，存在最佳厚度。该方法能够使用化学气相沉积（CVD）或DC溅射形成非晶Si（a-Si）和多晶硅（polySi）半导体层。 Si半导体可以掺杂有V族施主材料，其降低阈值电压并增加击穿电压。

65. 发明申请

US20070015328A1 MSM binary switch memory device 有权
公开(公告)号：US20070015328A1
公开(公告)日：2007-01-18
申请号：US11184660
申请日：2005-07-18
申请人： Sheng Hsu , Tingkai Li
发明人： Sheng Hsu , Tingkai Li
IPC分类号： H01L21/8242
CPC分类号： H01L27/101 , G11C13/0007 , G11C2213/31 , H01L27/2409 , H01L27/2463 , H01L29/66143 , H01L29/872 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A metal/semiconductor/metal (MSM) binary switch memory device and fabrication process are provided. The device includes a memory resistor bottom electrode, a memory resistor material over the memory resistor bottom electrode, and a memory resistor top electrode over the memory resistor material. An MSM bottom electrode overlies the memory resistor top electrode, a semiconductor layer overlies the MSM bottom electrode, and an MSM top electrode overlies the semiconductor layer. The MSM bottom electrode can be a material such as Pt, Ir, Au, Ag, TiN, or Ti. The MSM top electrode can be a material such as Pt, Ir, Au, TiN, Ti, or Al. The semiconductor layer can be amorphous Si, ZnO2, or InO2.

66. 发明申请

US20060194403A1 PCMO thin film with controlled resistance characteristics 审中-公开
标题翻译： PCMO薄膜具有受控电阻特性
公开(公告)号：US20060194403A1
公开(公告)日：2006-08-31
申请号：US11378719
申请日：2006-03-17
申请人： Tingkai Li , Wei-Wei Zhuang , David Evans , Sheng Hsu
发明人： Tingkai Li , Wei-Wei Zhuang , David Evans , Sheng Hsu
IPC分类号： H01L21/20
CPC分类号： G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： PrCaMnO (PCMO) thin films with predetermined memory-resistance characteristics and associated formation processes have been provided. In one aspect the method comprises: forming a Pr3+1−xCa2+xMnO thin film composition, where 0.1
摘要翻译：已经提供了具有预定的记忆电阻特性和相关的形成过程的PrCaMnO（PCMO）薄膜。在一个方面，所述方法包括：形成Pr 3+ 1-x 2 Ca 2 O 3 x MnO薄膜组成，其中0.1 _0.78Mn^{4+</SUP>_0.22O^2-_{2.96 组合， Mn和O离子的比例变化如下：O 2 - （2.96）; Mn（3+）+（（1-x）+ 8％）; 和Mn 4+（x-8％）。在另一方面，该方法响应于晶体取向在PCMO膜中产生密度。例如，如果PCMO膜具有（110）取向，则在垂直于（110）取向的平面中产生在每平方英尺5至6.76个Mn原子的范围内的密度。}}

67. 发明申请

US20060180817A1 Silicon phosphor electroluminescence device with nanotip electrode 有权
标题翻译：具有纳米尖电极的硅荧光体电致发光器件
公开(公告)号：US20060180817A1
公开(公告)日：2006-08-17
申请号：US11061946
申请日：2005-02-17
申请人： Sheng Hsu , Fengyan Zhang , Gregory Stecker , Robert Barrowcliff
发明人： Sheng Hsu , Fengyan Zhang , Gregory Stecker , Robert Barrowcliff
IPC分类号： H01L27/15
CPC分类号： H05B33/145
摘要： An electroluminescence (EL) device and a method are provided for fabricating said device with a nanotip electrode. The method comprises: forming a bottom electrode with nanotips; forming a Si phosphor layer adjacent the nanotips; and, forming a transparent top electrode. The Si phosphor layer is interposed between the bottom and top electrodes. The nanotips may have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. Typically, the nanotips are formed from iridium oxide (IrOx) nanotips. A MOCVD process forms the Ir bottom electrode. The IrOx nanotips are grown from the Ir. In one aspect, the Si phosphor layer is a SRSO layer. In response to an SRSO annealing step, nanocrystalline SRSO is formed with nanocrystals having a size in the range of 1 to 10 nm.
摘要翻译：提供了一种电致发光（EL）器件和用于制造具有纳米尖端电极的所述器件的方法。该方法包括：形成具有纳米尖端的底部电极; 在所述纳米尖端附近形成Si磷光体层; 并形成透明的顶部电极。 Si荧光体层介于底部和顶部电极之间。纳米尖端可以具有约50纳米或更小的尖端基部尺寸，5至50nm范围内的尖端高度，以及每平方毫米大于100纳米尖端的纳米密度密度。通常，纳米尖端由氧化铱（IrOx）纳米尖端形成。 MOCVD工艺形成Ir底部电极。 IrOx纳米尖嘴从Ir生长。在一个方面，Si磷光体层是SRSO层。响应于SRSO退火步骤，形成具有1至10nm范围内的尺寸的纳米晶体的纳米晶SRSO。

68. 发明申请

US20060172555A1 Method to make silicon nanoparticle from silicon rich-oxide by DC reactive sputtering for electroluminescence application 审中-公开
标题翻译：通过用于电致发光应用的DC反应溅射从富硅氧化物制造硅纳米颗粒的方法
公开(公告)号：US20060172555A1
公开(公告)日：2006-08-03
申请号：US11049594
申请日：2005-02-01
申请人： Wei Gao , Tingkai Li , Yoshi Ono , Sheng Hsu
发明人： Wei Gao , Tingkai Li , Yoshi Ono , Sheng Hsu
IPC分类号： H01L21/31
CPC分类号： C23C14/5806 , C23C14/10
摘要： A method of forming a silicon-rich silicon oxide layer having nanometer sized silicon particles therein includes preparing a substrate; preparing a target; placing the substrate and the target in a sputtering chamber; setting the sputtering chamber parameters; depositing material from the target onto the substrate to form a silicon-rich silicon oxide layer; and annealing the substrate to form nanometer sized silicon particles therein.
摘要翻译：形成其中具有纳米尺寸硅颗粒的富硅氧化硅层的方法包括制备衬底; 准备一个目标将基板和靶放置在溅射室中; 设置溅射室参数; 将材料从靶材沉积到衬底上以形成富硅氧化硅层; 并对衬底退火以在其中形成纳米尺寸的硅颗粒。

69. 发明申请

US20060088974A1 METHOD OF AFFECTING RRAM CHARACTERISTICS BY DOPING PCMO THIN FILMS 有权
标题翻译：通过PCMO薄膜影响RRAM特性的方法
公开(公告)号：US20060088974A1
公开(公告)日：2006-04-27
申请号：US10971387
申请日：2004-10-21
申请人： Wei-Wei Zhuang , David Evans , Fengyan Zhang , Sheng Hsu
发明人： Wei-Wei Zhuang , David Evans , Fengyan Zhang , Sheng Hsu
IPC分类号： H01L21/20 , H01L21/00
CPC分类号： H01L45/1608 , C23C18/1216 , C23C18/1225 , C23C18/1283 , C23C18/1295 , H01L21/31691 , H01L28/20 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method of fabricating a doped-PCMO thin film layer includes preparing a PCMO precursor solution having a transition metal additive therein; and spin-coating the doped-PCMO spin-coating solution onto a wafer.
摘要翻译：制造掺杂PCMO薄膜层的方法包括制备其中具有过渡金属添加剂的PCMO前体溶液; 并将掺杂的PCMO旋涂溶液旋涂到晶片上。

70. 发明申请

US20060068099A1 Grading PrxCa1-xMnO3 thin films by metalorganic chemical vapor deposition 审中-公开
标题翻译：通过金属有机化学气相沉积法分级PrxCa1-xMnO3薄膜
公开(公告)号：US20060068099A1
公开(公告)日：2006-03-30
申请号：US10957304
申请日：2004-09-30
申请人： Tingkai Li , Lawrence Charneski , Wei-Wei Zhuang , David Evans , Sheng Hsu
发明人： Tingkai Li , Lawrence Charneski , Wei-Wei Zhuang , David Evans , Sheng Hsu
IPC分类号： C23C16/00
CPC分类号： C23C16/40 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1616
摘要： The present invention discloses a method to achieve grading PCMO thin film for use in RRAM memory devices since the contents of Ca, Mn and Pr in a PCMO film can have great influence on its switching property. By choosing precursors for Pr, Ca and Mn having different deposition rate behaviors with respect to deposition temperature or vaporizer temperature, PCMO thin film of grading Pr, Ca or Mn distribution can be achieved by varying that process condition during deposition. The present invention can also be broadly applied to the fabrication of any multicomponent grading thin film process by varying any of the deposition parameters after preparing multiple precursors to have different deposition rate behaviors with respect to that particular process parameter. The present invention starts with a proper selection of precursors in which the selected precursors have different deposition rates with respect to at least one deposition condition such as deposition temperature or vaporizer temperature. The precursors can then be arranged in different delivery systems, or can be pre-mixed in a proper ratio for use in a delivery system, or in any other combinations such as a mixture of two or three liquid precursors using a direct liquid injection and a separate gaseous precursor delivery system for gaseous process gas. Then by varying the appropriate deposition condition, a grading thin film can be achieved.
摘要翻译：本发明公开了一种用于RRAM存储器件中的PCMO薄膜分级的方法，因为PCMO薄膜中Ca，Mn和Pr的含量对其开关性能有很大的影响。通过选择相对于沉积温度或蒸发器温度具有不同沉积速率行为的Pr，Ca和Mn的前体，可以通过在沉积期间改变该工艺条件来实现分级Pr，Ca或Mn分布的PCMO薄膜。本发明还可以广泛地应用于任何多组分分级薄膜工艺的制造，其通过在制备多种前体之后改变任何沉积参数以相对于该特定工艺参数具有不同的沉积速率行为。本发明开始于适当选择前体，其中所选择的前体相对于至少一个沉积条件例如沉积温度或蒸发器温度具有不同的沉积速率。然后可将前体布置在不同的递送系统中，或者可以以适当的比例预先混合以用于递送系统，或者以任何其它组合例如使用直接液体注射的两种或三种液体前体的混合物用于气态工艺气体的单独的气态前体输送系统。然后通过改变适当的沉积条件，可以实现分级薄膜。

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