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61. 发明授权

US6031394A Low voltage CMOS circuit for on/off chip drive at high voltage 失效
标题翻译：低压CMOS电路用于高电压开/关芯片驱动
公开(公告)号：US6031394A
公开(公告)日：2000-02-29
申请号：US4565
申请日：1998-01-08
申请人： Hayden C. Cranford, Jr. , Stacy J. Garvin , Geoffrey B. Stephens
发明人： Hayden C. Cranford, Jr. , Stacy J. Garvin , Geoffrey B. Stephens
IPC分类号： H03K3/356 , H03K17/10 , H03K19/0175 , H03K19/00 , H03K19/003 , H03K19/094
CPC分类号： H03K3/356147 , H03K17/102
摘要： A low voltage CMOS circuit and method provide output current ability meeting multimode requirements of high voltage off-chip drivers while protecting the CMOS devices from various breakdown mechanisms. The circuit and method utilize intermediate voltages between two power rails and voltage division techniques to limit the voltages to acceptable limits for drain-to-source, gate-to-drain, and gate-to-source of CMOS devices in any chosen technology. The circuit comprises first and second CMOS cascode chains connected between a high voltage power rail, e.g 5 volt and a reference potential power rail, e.g. ground. Each CMOS cascode chain comprises first and second p-type MOS devices in series with first and second n-type MOS devices. An input circuit is coupled to a node at the midpoint of the first CMOS cascode chain. A bias voltage, typically 3.3 volts is connected to the NMOS devices in the first and CMOS cascode chains. A second bias voltage is coupled to the PMOS devices in the first and second CMOS cascode chains. An output is provided from the second CMOS cascode chain to a third CMOS cascode chain for purposes of providing sufficient pullup capability to drive an output circuit comprising a fourth CMOS cascode chain between the high and reference potentials without exceeding the breakdown mechanisms for any MOS device in the CMOS cascode chains.
摘要翻译：低电压CMOS电路和方法提供满足多电压芯片驱动器多模式要求的输出电流能力，同时保护CMOS器件免受各种故障机制的影响。电路和方法利用两个电源轨之间的中间电压和分压技术，将电压限制在任何所选技术中的CMOS器件的漏极到源极，栅极到漏极和栅极到源极的可接受的极限。该电路包括第一和第二CMOS共源共栅链，其连接在例如5伏的高压电源轨和参考电位电源轨之间。地面。每个CMOS共源共栅链包括与第一和第二n型MOS器件串联的第一和第二p型MOS器件。输入电路耦合到第一CMOS共源共栅链的中点的节点。通常3.3伏的偏置电压连接到第一和CMOS共源共栅链中的NMOS器件。第二偏置电压耦合到第一和第二CMOS共源共栅链中的PMOS器件。从第二CMOS共源共栅链提供输出到第三CMOS共源共栅链，目的是提供足够的上拉能力，以在不超过任何MOS器件的击穿机制的情况下驱动包括高参考电位和参考电位之间的第四CMOS共源共栅链的输出电路 CMOS共源共栅链。

62. 发明授权

US08798204B2 Serial link receiver for handling high speed transmissions 有权
标题翻译：用于处理高速传输的串行链路接收器
公开(公告)号：US08798204B2
公开(公告)日：2014-08-05
申请号：US13228512
申请日：2011-09-09
申请人： Minhan Chen , Hayden C. Cranford, Jr.
发明人： Minhan Chen , Hayden C. Cranford, Jr.
IPC分类号： H03K9/00 , H04B3/00
CPC分类号： H04L25/0276 , H04L25/0298
摘要： A serial link receiver comprises first and second input terminals for receiving positive and negative inputs of a serial data signal, first and second broadband matching T-coils coupled to the first and second input terminals, first and second AC/DC coupling networks coupled to the first and second broadband matching T-coils, and a common mode level shifter coupled to the outputs from the first and second AC/DC coupling networks. This receiver architecture combines the ability to have a wide bandwidth input and pass through data signals at both low and high frequencies. This AC and DC coupled front end also incorporates the feature of a common mode level shifting network to place the common mode of the signal at the optimum point for the first active amplifier stage.
摘要翻译：串行链路接收机包括用于接收串行数据信号的正和负输入的第一和第二输入端，耦合到第一和第二输入端的第一和第二宽带匹配T型线圈，耦合到第一和第二AC / DC耦合网络第一和第二宽带匹配T型线圈，以及耦合到来自第一和第二AC / DC耦合网络的输出的共模电平移位器。该接收机架构结合了具有宽带宽输入和通过低频和高频数据信号的能力。该AC和DC耦合前端还结合了共模电平转换网络的特征，以将信号的共模放置在第一有源放大器级的最佳点。

63. 发明授权

US08219040B2 Transmitter bandwidth optimization circuit 有权
标题翻译：发射机带宽优化电路
公开(公告)号：US08219040B2
公开(公告)日：2012-07-10
申请号：US11769128
申请日：2007-06-27
申请人： Louis L. Hsu , Hayden C. Cranford, Jr. , Joseph Natonio , James D. Rockrohr , Huihao Xu , Steven J. Zier
发明人： Louis L. Hsu , Hayden C. Cranford, Jr. , Joseph Natonio , James D. Rockrohr , Huihao Xu , Steven J. Zier
IPC分类号： H04B1/02
CPC分类号： H04L25/0286 , H04L25/0272
摘要： A method is provided for operating a transmitter integrated in a microelectronic element. In a calibration phase, a plurality of operational parameters are stored for controlling a frequency response of the transmitter under each of a plurality of corresponding operating conditions. Upon detecting an operating condition such as a temperature or power supply voltage level, the corresponding stored operational parameter is applied to the transmitter to control the frequency response.
摘要翻译：提供了一种用于操作集成在微电子元件中的发射器的方法。在校准阶段中，存储多个操作参数，用于在多个对应的操作条件中的每一个下控制发射机的频率响应。在检测到诸如温度或电源电压电平的操作条件时，将相应的存储的操作参数应用于发射机以控制频率响应。

64. 发明授权

US08054867B2 Apparatus for transmitting data and additional information simultaneously within a wire-based communication system 有权
标题翻译：用于在有线通信系统内同时发送数据和附加信息的装置
公开(公告)号：US08054867B2
公开(公告)日：2011-11-08
申请号：US12030478
申请日：2008-02-13
申请人： Hayden C. Cranford, Jr. , Martin Schmatz
发明人： Hayden C. Cranford, Jr. , Martin Schmatz
IPC分类号： H04B1/00
CPC分类号： H04B1/707 , H04L5/20 , H04L25/45
摘要： An apparatus is provided for transmitting data signals and additional information signals having partially overlapping frequency bands simultaneously within a wire based communication system over the same wired medium using a spread spectrum technique for modulating the additional information signals.
摘要翻译：提供了一种装置，用于使用用于调制附加信息信号的扩展频谱技术，在同一有线介质上，在有线通信系统内同时发送具有部分重叠频带的数据信号和附加信息信号。

65. 发明授权

US07983368B2 Systems and arrangements for clock and data recovery in communications 有权
标题翻译：通信中时钟和数据恢复的系统和安排
公开(公告)号：US07983368B2
公开(公告)日：2011-07-19
申请号：US11608948
申请日：2006-12-11
申请人： Hayden C. Cranford, Jr. , Daniel J. Friedman , Mounir Meghelli , Thomas H. Toifl
发明人： Hayden C. Cranford, Jr. , Daniel J. Friedman , Mounir Meghelli , Thomas H. Toifl
IPC分类号： H04L7/00
CPC分类号： H04L7/042 , H04L7/0004 , H04L7/0334
摘要： A sampling clock signal controller for receivers of digital data is disclosed. Specific bit patterns of a data waveform can be identified, and stored time samples of the waveform that correspond to the specific bit patterns can be analyzed to improve the timing of a sampling clock signal. These “time-amplitude” samples on known bit patterns can be utilized to determine if a sample on the data waveform should be taken before the center of the eye pattern, at the center of the eye pattern, or after the center of the eye pattern and by what time change. Accordingly, a single low power clock can be utilized to adjust the timing of the sample clock such that improved communication scan be achieved. Such a single clock system has reduced power requirements and increased accuracy.
摘要翻译：公开了一种用于数字数据接收机的采样时钟信号控制器。可以识别数据波形的特定位模式，并且可以分析对应于特定位模式的波形的存储时间采样以改善采样时钟信号的定时。可以利用已知位图案上的这些“时间幅度”采样来确定数据波形上的样本是否应在眼图的中心，眼图的中心之前或眼图的中心之后和什么时间改变。因此，可以利用单个低功率时钟来调整采样时钟的定时，从而实现改进的通信扫描。这种单一时钟系统降低了功率需求并提高了精度。

66. 发明授权

US07940846B2 Test circuit for serial link receiver 有权
标题翻译：串行链路接收机测试电路
公开(公告)号：US07940846B2
公开(公告)日：2011-05-10
申请号：US11621016
申请日：2007-01-08
申请人： Hayden C. Cranford, Jr. , Daniel P. Greenberg , Joseph M. Stevens , Westerfield J. Ficken
发明人： Hayden C. Cranford, Jr. , Daniel P. Greenberg , Joseph M. Stevens , Westerfield J. Ficken
IPC分类号： H04B3/00
CPC分类号： G01R31/31715
摘要： A test circuit for a serial link receiver includes a first current source coupled to a first input of the serial link receiver, and a second current source coupled to a second input of the serial link receiver. The first current source is symmetrically matched to the second current source. A first switch of the first current source is turned on to permit a charge-retaining mechanism thereof to be charged. A second switch of the first current source is turned on to permit the retained charge retained to be asserted on the first input. The charge turns on a control switch of the first current source, through which the charge is asserted on the first input. A charge-draining mechanism of the first current source is turned on to thereafter permit the charge to be drained in a controlled manner after the charge has been asserted.
摘要翻译：用于串行链路接收机的测试电路包括耦合到串行链路接收机的第一输入端的第一电流源和耦合到串行链路接收机的第二输入端的第二电流源。第一电流源与第二电流源对称地匹配。第一电流源的第一开关被接通以允许其电荷保持机构被充电。第一电流源的第二开关导通，以允许保留的保留电荷在第一输入上被断言。电荷打开第一个电流源的控制开关，电荷在第一个输入端被断言。接通第一电流源的电荷排放机构，之后允许电荷在电荷被断言之后以受控的方式排出。

67. 发明授权

US07698802B2 Method for manufacturing a calibration device 失效
标题翻译：校准装置的制造方法
公开(公告)号：US07698802B2
公开(公告)日：2010-04-20
申请号：US12028439
申请日：2008-02-08
申请人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Vernon R. Norman
发明人： Steven M. Clements , William P. Cornwell , Carrie E. Cox , Hayden C. Cranford, Jr. , Vernon R. Norman
IPC分类号： G01R31/28
CPC分类号： G01R35/007 , Y10T29/49004 , Y10T29/4913 , Y10T29/49147 , Y10T29/49155 , Y10T29/49169 , Y10T29/49174
摘要： A method for manufacturing a calibration device for an active circuit on a chip, comprises: providing an active circuit that is capable of exhibiting a desired electrical characteristic; and providing a calibration mechanism on-chip with the active circuit. The calibration mechanism generates a control output and comprises a device under test (DUT) configured as a replica of at least one segment of the active circuit, and which generates a test output that causes finite adjustments to the control output, based on a comparison of the electrical characteristics exhibited by the DUT with a known electrical characteristic. The method further comprises: attaching to each control input terminal of the active circuit a corresponding control output from the calibration mechanism. The control output of the calibration mechanism dynamically adjusts control input applied to devices of the active circuit to force the active circuit to exhibit the desired electrical characteristic.
摘要翻译：一种用于制造芯片上的有源电路的校准装置的方法，包括：提供能够呈现所需电特性的有源电路; 并且提供与有源电路片上的校准机制。所述校准机构产生控制输出，并且包括被配置为所述有源电路的至少一个段的复制品的被测器件（DUT），并且基于所述被测器件的比较，产生对所述控制输出进行有限调整的测试输出具有已知电特性的DUT所呈现的电特性。该方法还包括：将有源电路的每个控制输入端连接到校准机构的相应控制输出。校准机构的控制输出动态调整施加到有源电路的器件的控制输入，以迫使有源电路呈现所需的电特性。

68. 发明授权

US07394273B2 On-chip electromigration monitoring system 有权
标题翻译：片上电迁移监控系统
公开(公告)号：US07394273B2
公开(公告)日：2008-07-01
申请号：US11306985
申请日：2006-01-18
申请人： Louis L. Hsu , Hayden C. Cranford, Jr. , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
发明人： Louis L. Hsu , Hayden C. Cranford, Jr. , Oleg Gluschenkov , James S. Mason , Michael A. Sorna , Chih-Chao Yang
IPC分类号： G01R31/02
CPC分类号： G01R31/2858 , G01R31/2884 , G01R31/318533
摘要： A packaged semiconductor chip is provided which includes a semiconductor chip and a package element. The semiconductor chip includes a plurality of semiconductor devices and a plurality of conductive features disposed at an exterior face of the semiconductor chip. The package element has a plurality of external features conductively connected to the plurality of conductive features of the semiconductor chip. The semiconductor chip includes a monitored element including a conductive interconnect that conductively interconnects a first node of the semiconductor chip to a second node of the semiconductor chip. A detection circuit in the semiconductor chip is operable to compare a variable voltage drop across the monitored element with a reference voltage drop across a reference element on the chip at a plurality of different times during a lifetime of the packaged semiconductor chip so as to detect when the resistance of the monitored element is over threshold.
摘要翻译：提供一种封装的半导体芯片，其包括半导体芯片和封装元件。半导体芯片包括多个半导体器件和设置在半导体芯片的外表面处的多个导电特征。封装元件具有导电连接到半导体芯片的多个导电特征的多个外部特征。半导体芯片包括被监视的元件，该元件包括将半导体芯片的第一节点与半导体芯片的第二节点导电互连的导电互连。半导体芯片中的检测电路可操作以在封装的半导体芯片的寿命期间的多个不同时间将所监视的元件上的可变电压降与芯片上的参考元件上的参考电压降进行比较，以便检测何时被监测元件的电阻超过阈值。

69. 发明授权

US07289572B2 Method and system for scalable pre-driver to driver interface 有权
标题翻译：可扩展的预驱动程序到驱动程序接口的方法和系统
公开(公告)号：US07289572B2
公开(公告)日：2007-10-30
申请号：US10265755
申请日：2002-10-07
申请人： Hayden C. Cranford, Jr. , Westerfield J. Ficken
发明人： Hayden C. Cranford, Jr. , Westerfield J. Ficken
IPC分类号： H04L27/00
CPC分类号： H04L25/028 , H04L25/0272
摘要： A system and method for a predriver and driver interface having scalable output drive capability with corresponding scalable power is disclosed. The system includes a predriver to driver interface having a data source; a plurality of predrivers, each coupled to the data source and responsive to an enable signal, for driving a predriven data signal only when a corresponding enable signal is asserted and for consuming reduced power when the corresponding enable signal is deasserted; a plurality of drivers, each coupled to one of the plurality of predrivers to receive a corresponding predriven data signal from the corresponding predriver and responsive to the enable signal coupled to the corresponding predriver, for driving an output with the predriven data signal only when the corresponding enable signal is asserted and for consuming reduced power when the corresponding enable signal is deasserted; and a controller, coupled to the predrivers and the drivers, for selectively asserting the enable signals to provide variable output drive capability of the data source to the output while providing scalable power consumption.
摘要翻译：公开了一种具有可扩展输出驱动能力和相应的可扩展功率的预驱动器和驱动器接口的系统和方法。该系统包括具有数据源的驱动器接口的预驱动器; 每个耦合到数据源并且响应于使能信号的预驱动器，用于仅在相应的使能信号被断言时驱动预驱动数据信号，并且当相应的使能信号被无效时消耗降低的功率; 多个驱动器，每个驱动器耦合到所述多个预驱动器中的一个，以从相应的预驱动器接收相应的预驱动数据信号，并且响应于耦合到相应的预驱动器的使能信号，仅在相应的预驱动器驱动具有预驱动数据信号的输出时使能信号被断言并且当相应的使能信号被无效时消耗降低的功率; 以及耦合到预驱动器和驱动器的控制器，用于选择性地确定使能信号，以在提供可缩放功率消耗的同时向输出端提供数据源的可变输出驱动能力。

70. 发明授权

US07286947B1 Method and apparatus for determining jitter and pulse width from clock signal comparisons 失效
标题翻译：用于从时钟信号比较确定抖动和脉冲宽度的方法和装置
公开(公告)号：US07286947B1
公开(公告)日：2007-10-23
申请号：US11279651
申请日：2006-04-13
申请人： Hayden C. Cranford, Jr. , Fadi H. Gebara , Jeremy D. Schaub
发明人： Hayden C. Cranford, Jr. , Fadi H. Gebara , Jeremy D. Schaub
IPC分类号： G06F19/00
CPC分类号： G01R31/31709 , G01R31/31725
摘要： A method and apparatus for determining jitter and pulse width from clock signal comparisons provides a low cost and production-integrable mechanism for measuring a clock signal with a reference clock, both of unknown frequency. The measured clock signal is sampled at transitions of a reference clock and the sampled values are collected in a histogram according to a folding of the samples around a timebase which is either swept to detect a minimum jitter for the folded data or is obtained from direct frequency analysis for the sample set. The histogram for the correct estimated period is statistically analyzed to yield the pulse width, which is the difference between the peaks of the probability density function and jitter, which corresponds to width of the density function peaks. Frequency drift is corrected by adjusting the timebase used to fold the data across the sample set.
摘要翻译：用于从时钟信号比较确定抖动和脉冲宽度的方法和装置提供了一种低成本和可生产可集成的机制，用于测量具有未知频率的参考时钟的时钟信号。测量的时钟信号在参考时钟的转变时被采样，并且采样值被收集在直方图中，根据时基的周围样本的折叠，该时基被扫描以检测折叠数据的最小抖动，或者从直接频率获得分析样本集。统计分析正确估计周期的直方图以产生脉冲宽度，其是概率密度函数和抖动的峰值之间的差异，其对应于密度函数峰值的宽度。通过调整用于将样本集合中的数据折叠的时基来校正频率漂移。

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