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    • 63. 发明授权
    • Shielded integrated circuit capacitor connected to a lateral transistor
    • 屏蔽集成电路电容器
    • US06198123B1
    • 2001-03-06
    • US08924456
    • 1997-08-29
    • William J. LinderRobert S. Harguth
    • William J. LinderRobert S. Harguth
    • H01G428
    • H01L28/40
    • An integrated circuit (IC) capacitor offers reduced sensitivity to parasitic capacitance, reduced-size, and increased noise immunity, such as for use in digital-to-analog converters (DACs), analog-to-digital converters (ADCs), switched-capacitor filters, and other IC circuits. The capacitor includes a first polysilicon layer, a superjacent second polysilicon layer separated from the first polysilicon layer by an insulator, and an overlying metal layer separated from the second polysilicon layer by an insulator. The metal layer provides a shield that is connected to a known voltage, or to the first polysilicon layer. When connected to the first polysilicon layer, the overlying metal layer also provides additional parallel capacitance, thereby reducing the integrated circuit area of the capacitor. In one example, the overlying metal layer is a second metal layer that is also used, together with a first metal layer, for interconnecting IC components.
    • 集成电路(IC)电容器对寄生电容的灵敏度降低,尺寸减小,抗噪声能力增强,例如用于数/模转换器(DAC),模/数转换器(ADC) 电容滤波器和其他IC电路。 电容器包括第一多晶硅层,通过绝缘体与第一多晶硅层分离的相邻的第二多晶硅层,以及通过绝缘体与第二多晶硅层分离的上覆金属层。 金属层提供连接到已知电压的屏蔽,或者连接到第一多晶硅层。 当连接到第一多晶硅层时,上覆金属层还提供额外的并联电容,从而减小电容器的集成电路面积。 在一个示例中,上覆金属层是第二金属层,其也与第一金属层一起用于互连IC部件。
    • 64. 发明授权
    • Linear amplifier
    • 线性放大器
    • US5699014A
    • 1997-12-16
    • US627403
    • 1996-04-04
    • Paul A. HaefnerWilliam J. Linder
    • Paul A. HaefnerWilliam J. Linder
    • H03F1/32H03F3/45
    • H03F1/3211H03F1/3205H03F2200/162H03F2200/372
    • A low-noise, low-power complementary metal-oxide-semiconductor (CMOS) integrated circuit common source differential amplifier is disclosed which is capable of amplifying low amplitude cardiac signals such as those produced by atrial depolarization of the heart. The amplifier has a pair of large area p-channel input field-effect transistors (FETs) biased in weak inversion. The amplifier also has active load FETs biased in the nonsaturation (linear) region by means of a varying gate terminal voltage applied by a dynamic bias circuit. The gate terminal voltage is varied to match the temperature dependence of the output conductance of the load FETs to the temperature dependence of the transconductance of the input FETs. The gate terminal voltage also sets a dc bias point which uses the nonlinearity in the load FET output conductance to cancel nonlinearity in the input FET transconductance.
    • 公开了一种低噪声,低功率互补金属氧化物半导体(CMOS)集成电路公共源差分放大器,其能够放大低振幅心脏信号,例如通过心脏去极化产生的心脏信号。 放大器具有一对在弱反相中偏置的大面积p沟道输入场效应晶体管(FET)。 放大器还通过由动态偏置电路施加的变化的栅极端子电压而在非饱和(线性)区域中偏置有有源负载FET。 栅极端子电压变化以匹配负载FET的输出电导的温度依赖性与输入FET的跨导的温度依赖性。 栅极端子电压还设置直流偏置点,其使用负载FET输出电导中的非线性来消除输入FET跨导中的非线性。
    • 66. 发明授权
    • Phase locked loop with limited phase correction when in locked condition
    • 锁定环在锁定状态下进行有限的相位校正
    • US4543540A
    • 1985-09-24
    • US487941
    • 1983-04-25
    • William J. Linder
    • William J. Linder
    • H03L7/191H03L7/00
    • H03L7/191Y10S331/02
    • A phase locked loop provides limited phase correction when in lock in order to minimize the effects of noise in the periodic input signal to which the loop is locked. The phase locked loop includes a voltage controlled oscillator (VCO), a timing generation divider, a phase detector, a lock detector and an oscillator control circuit. The phase detector provides an output based upon the phase difference between rising edges of the input signal and a loop synthesized signal which is derived by the divider from an oscillator output signal. A window signal, which begins slightly before and ends slightly after an anticipated rising edge of the input signal, is also derived from the oscillator output signal. The lock detector provides a lock detect signal which indicates whether the loop is in lock. The oscillator control circuit provides an oscillator control voltage based upon the phase detector output signal, the window signal, and the lock detect signal. When the loop is in lock, changes to the oscillator control voltage based on the phase detector output are limited by the window signal. When the loop out of lock, full corrections to the oscillator control voltage based upon the phase detector output signal are permitted, so that the loop can rapidly regain the phase locked condition.
    • 锁相环在锁定时提供有限的相位校正,以便最小化环路锁定的周期性输入信号中噪声的影响。 锁相环包括压控振荡器(VCO),定时产生分频器,相位检测器,锁定检测器和振荡器控制电路。 相位检测器基于输入信号的上升沿之间的相位差和由分频器从振荡器输出信号导出的回路合成信号提供输出。 在输入信号的预期上升沿之后稍微开始并稍微结束的窗口信号也从振荡器输出信号导出。 锁定检测器提供一个锁定检测信号,指示环路是否处于锁定状态。 振荡器控制电路基于相位检测器输出信号,窗口信号和锁定检测信号提供振荡器控制电压。 当环路锁定时,基于相位检测器输出的振荡器控制电压的改变受到窗口信号的限制。 当环路锁定时,允许基于相位检测器输出信号对振荡器控制电压的全面校正,使得环路可以快速恢复锁相状态。