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61. 发明授权

US09397641B2 Apparatus and method for low power fully-interruptible latches and master-slave flip-flops 有权
公开(公告)号：US09397641B2
公开(公告)日：2016-07-19
申请号：US14711686
申请日：2015-05-13
申请人： Steven K. Hsu , Amit Agarwal , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Amit Agarwal , Ram K. Krishnamurthy
IPC分类号： H03K3/356 , H03K3/3562
CPC分类号： H03K3/35625 , H03K3/356104
摘要： Described is a latch which comprises: a first AND-OR-invert (AOI) logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply node. Described is a flip-flop which comprises: a first latch including: a first AOI logic gate; and a second AOI logic gate coupled to the first AOI logic gate, wherein the first and second AOI logic gates have respective first and second keeper devices coupled to a power supply, the first latch having an output node; and a second latch having an input node coupled to the output node of the first latch, the second latch having an output node to provide an output of the flip-flop.

62. 发明申请

US20140105303A1 Motion Estimation for Video Processing 审中-公开
标题翻译：视频处理的运动估计
公开(公告)号：US20140105303A1
公开(公告)日：2014-04-17
申请号：US13649560
申请日：2012-10-11
申请人： Himanshu Kaul , Mark A. Anders , Ram K. Krishnamurthy
发明人： Himanshu Kaul , Mark A. Anders , Ram K. Krishnamurthy
IPC分类号： H04N7/32
CPC分类号： H04N19/43 , H04N19/567
摘要： In accordance with some embodiments, the complexity of motion estimation algorithms that use Haar, SAD and Hadamard transforms may be reduced. In some embodiments, the number of summations may be reduced compared to existing techniques and some of the existing summations may be replaced with compare operations. In some embodiments, additions are replaced with compares in order to balance delay and area or energy or power considerations.
摘要翻译：根据一些实施例，可以减少使用Haar，SAD和Hadamard变换的运动估计算法的复杂度。在一些实施例中，与现有技术相比可以减少求和的数量，并且可以用比较操作来替换一些现有的求和。在一些实施例中，为了平衡延迟和面积或能量或功率考虑，用比较代替添加。

63. 发明申请

US20090168483A1 Ultra low voltage and minimum operating voltage tolerant register file 有权
公开(公告)号：US20090168483A1
公开(公告)日：2009-07-02
申请号：US12006238
申请日：2007-12-31
申请人： Steven K. Hsu , Amit Agarwal , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Amit Agarwal , Ram K. Krishnamurthy
IPC分类号： G11C5/06 , G11C7/00
CPC分类号： G11C11/419
摘要： Methods and apparatus relating ultra-low voltage memory bit cells are described. In an embodiment, an ultra-low voltage memory device is provided using redundant paths to data storage nodes controlled by complementary write word lines. Other embodiments are also described.

64. 发明授权

US07379491B2 Flop repeater circuit 有权
标题翻译：触发中继电路
公开(公告)号：US07379491B2
公开(公告)日：2008-05-27
申请号：US10744085
申请日：2003-12-24
申请人： Steven K. Hsu , Ram K. Krishnamurthy , Gian Gerosa
发明人： Steven K. Hsu , Ram K. Krishnamurthy , Gian Gerosa
IPC分类号： H04B3/36
CPC分类号： H04B3/36 , H03K3/35625
摘要： A system is provided that includes a clocking circuit to provide two repeater clock signals and a flop repeater circuit to receive the two repeater clock signals and an input data signal. The flop repeater circuit to provide an output data signal based on the two repeater clock signals. The flop repeater circuit including a plurality of transistors and inverters coupled together to function as a flip-flop circuit that passes data without any full transmission gates.
摘要翻译：提供了一种系统，其包括用于提供两个中继器时钟信号的时钟电路和用于接收两个中继器时钟信号的触发中继器电路和输入数据信号。触发中继器电路基于两个中继器时钟信号提供输出数据信号。包括耦合在一起的多个晶体管和反相器的触发中继器电路用作在没有任何完全传输门的情况下传递数据的触发器电路。

65. 发明授权

US07275204B2 Distributed ring control circuits for Viterbi traceback 有权
标题翻译：用于维特比回溯的分布式环形控制电路
公开(公告)号：US07275204B2
公开(公告)日：2007-09-25
申请号：US10954648
申请日：2004-09-30
申请人： Mark A. Anders , Sanu K. Matthew , Ram K. Krishnamurthy
发明人： Mark A. Anders , Sanu K. Matthew , Ram K. Krishnamurthy
IPC分类号： H03M13/41
CPC分类号： H03M13/6505 , H03M13/41 , H03M13/4169
摘要： Shift resister rings are used to provide column access in a traceback memory during Viterbi decoding.
摘要翻译：移位电阻环用于在维特比解码期间在追溯存储器中提供列访问。

66. 发明授权

US07099219B2 Multi read port bit line 有权
标题翻译：多读端口位线
公开(公告)号：US07099219B2
公开(公告)日：2006-08-29
申请号：US11018012
申请日：2004-12-20
申请人： Steven K. Hsu , Atul Maheshwari , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Atul Maheshwari , Ram K. Krishnamurthy
IPC分类号： G11C7/02 , G11C11/00 , G11C11/34 , G11C8/00
CPC分类号： G11C11/413 , G11C7/12 , G11C11/56
摘要： In some embodiment, a circuit is provided that comprises a bit line and bit cells coupled to the bit line. The bit line has an impedance. The bit cells, when operated, are each capable of adjusting the bit line impedance to indicate a stored bit value and a selected one of at least two read ports. Other embodiments are described or otherwise claimed herein.
摘要翻译：在一些实施例中，提供了包括位线和耦合到位线的位单元的电路。位线有阻抗。位单元在操作时都能够调整位线阻抗以指示存储的位值和至少两个读端口中选择的一个。在此描述或以其他方式要求保护的其它实施例。

67. 发明授权

US07057913B2 Low-power search line circuit encoding technique for content addressable memories 失效
标题翻译：用于内容可寻址存储器的低功耗搜索线电路编码技术
公开(公告)号：US07057913B2
公开(公告)日：2006-06-06
申请号：US10817941
申请日：2004-04-06
申请人： Steven K. Hsu , Ram K. Krishnamurthy
发明人： Steven K. Hsu , Ram K. Krishnamurthy
IPC分类号： G11C15/00
CPC分类号： G11C15/00 , G11C15/04
摘要： A circuit for searching a content addressable memory includes a driver which generates a plurality of search line values, different combinations of which are used to implement a one-hot encoding scheme for searching the memory. Two or more cells in the memory may be consecutive bit positions of a word, and the driver may be synchronously operated to generate the different combinations of values.
摘要翻译：用于搜索内容可寻址存储器的电路包括产生多个搜索线值的驱动器，其中不同的组合用于实现用于搜索存储器的单热编码方案。存储器中的两个或多个单元可以是字的连续位位置，并且可以同步地操作驱动器以产生不同的值组合。

68. 发明授权

US06919737B2 Voltage-level converter 失效
标题翻译：电压电平转换器
公开(公告)号：US06919737B2
公开(公告)日：2005-07-19
申请号：US10010737
申请日：2001-12-07
申请人： Atila Alvandpour , Ram K. Krishnamurthy
发明人： Atila Alvandpour , Ram K. Krishnamurthy
IPC分类号： H03K19/0185 , H03K19/0175
CPC分类号： H03K19/018521
摘要： A voltage-level converter and a method of converting a first logic voltage level to a second logic voltage level are described. In one embodiment, a voltage-level converter connects a first logic unit connected to a first supply voltage to a second logic unit connected to a second supply voltage. The voltage-level converter includes at least one transistor connected to the second supply voltage. The at least one transistor has a threshold voltage whose absolute value is greater-than-or-about-equal to the absolute value of the difference between the second supply voltage and the first supply voltage. In an alternative embodiment, a method for converting a first logic voltage level to a second logic voltage level includes transmitting a logic signal from a logic unit having an output voltage swing of between a first voltage level and a second voltage level, receiving the logic signal at a logic circuit having a pull-up transistor and an output voltage swing between a third voltage level and a fourth voltage level, and turning off the pull-up transistor when the logic signal has a value slightly greater than the difference between the third voltage level and the first voltage level.
摘要翻译：描述电压电平转换器和将第一逻辑电压电平转换到第二逻辑电压电平的方法。在一个实施例中，电压电平转换器将连接到第一电源电压的第一逻辑单元连接到与第二电源电压连接的第二逻辑单元。电压电平转换器包括连接到第二电源电压的至少一个晶体管。所述至少一个晶体管具有其绝对值大于或等于所述第二电源电压和所述第一电源电压之间的差的绝对值的阈值电压。在替代实施例中，用于将第一逻辑电压电平转换为第二逻辑电压电平的方法包括从具有在第一电压电平和第二电压电平之间的输出电压摆幅的逻辑单元传输逻辑信号，接收逻辑信号在具有上拉晶体管的逻辑电路和在第三电压电平和第四电压电平之间的输出电压摆幅，并且当所述逻辑信号具有略大于所述第三电压电平和第一电压电平。

69. 发明授权

US06614279B2 Clock receiver circuit for on-die salphasic clocking 有权
标题翻译：时钟接收器电路，用于片上相关时钟
公开(公告)号：US06614279B2
公开(公告)日：2003-09-02
申请号：US09941457
申请日：2001-08-29
申请人： Mark A. Anders , Ram K. Krishnamurthy , Krishnamurthy Soumyanath
发明人： Mark A. Anders , Ram K. Krishnamurthy , Krishnamurthy Soumyanath
IPC分类号： H03F345
CPC分类号： G06F1/10
摘要： A clock receiver circuit converts low amplitude, differential clock signal components received from a differential clock distribution medium into a full swing digital clock. The clock receiver circuit can be used as part of, for example, an on-die salphasic clock distribution system within a microelectronic device.
摘要翻译：时钟接收器电路将从差分时钟分配介质接收的低幅度差分时钟信号分量转换成全摆幅数字时钟。时钟接收器电路可以用作例如微电子器件内的管芯上的相关时钟分配系统的一部分。

70. 发明授权

US06590801B2 Current leakage reduction for loaded bit-lines in on-chip memory structures 有权
公开(公告)号：US06590801B2
公开(公告)日：2003-07-08
申请号：US10172106
申请日：2002-06-13
申请人： Atila Alvandpour , Ram K. Krishnamurthy , Siva G. Narendra
发明人： Atila Alvandpour , Ram K. Krishnamurthy , Siva G. Narendra
IPC分类号： G11C1140
CPC分类号： G11C11/412
摘要： Embodiments of the present invention relate to memory circuits with heavily loaded bit-lines, and where either the effect of leakage current in the read access or pass transistors is reduced, or leakage current is reduced.

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