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61. 发明授权

US08563352B2 Creation and translation of low-relief texture for a photovoltaic cell 失效
标题翻译：光伏电池的低浮雕纹理的创建和翻译
公开(公告)号：US08563352B2
公开(公告)日：2013-10-22
申请号：US12750635
申请日：2010-03-30
申请人： Mohamed M. Hiliali , S. Brad Herner
发明人： Mohamed M. Hiliali , S. Brad Herner
IPC分类号： H01L31/0236
CPC分类号： H01L31/0236 , Y02E10/50
摘要： Low-relief texture can be created by applying and firing frit paste on a silicon surface. Where frit contacts the surface at high temperature, it etches silicon, dissolving silicon in the softened glass frit. The result is a series of small, randomly located pits, which produce a near-Lambertian surface, suitable for use in a photovoltaic cell. This texturing method consumes little silicon, and is advantageously used in a photovoltaic cell in which a thin silicon lamina comprises the base region of the cell. When the lamina is formed by implanting ions in a donor wafer to form a cleave plane and cleaving the lamina from the donor wafer at the cleave plane, the ion implantation step will serve to translate texture formed at a first surface to the cleave plane, and thus to the second, opposing surface following cleaving. Low-relief texture formed by other methods can be translated from the first surface to the second surface in this way as well.
摘要翻译：可以通过在硅表面上施加和焙烧玻璃料膏来产生低浮雕纹理。当玻璃料在高温下接触表面时，会腐蚀硅，将硅溶解在软化玻璃料中。结果是一系列小的，随机位置的凹坑，其产生近Lambertian表面，适用于光伏电池。这种纹理化方法消耗很少的硅，并且有利地用于其中薄硅层包括电池的基极区域的光伏电池中。当通过在施主晶片中注入离子以形成解理平面并在分裂面处从施主晶片切割层而形成层板时，离子注入步骤将用于将形成在第一表面处的纹理平移至解理面，以及从而在切割之后到达第二相对表面。通过其他方法形成的低浮雕纹理也可以以这种方式从第一表面转换到第二表面。

62. 发明授权

US08482973B2 Nonvolatile memory cell operating by increasing order in polycrystalline semiconductor material 有权
标题翻译：非易失性存储单元通过增加多晶半导体材料的顺序来操作
公开(公告)号：US08482973B2
公开(公告)日：2013-07-09
申请号：US13568834
申请日：2012-08-07
申请人： S. Brad Herner , Abhijit Bandyopadhyay
发明人： S. Brad Herner , Abhijit Bandyopadhyay
IPC分类号： G11C11/36 , G11C11/34 , G11C11/00
CPC分类号： G11C11/36 , G11C5/02 , G11C11/39 , G11C17/06 , G11C17/16 , H01L27/1021
摘要： A memory cell is provided that includes a first conductor, a second conductor, and a semiconductor junction diode between the first and second conductors. The semiconductor junction diode is not in contact with a material having a lattice mismatch of less than 12 percent with the semiconductor junction diode. In addition, no resistance-switching element having its resistance changed by application of a programming voltage by more than a factor of two is disposed between the semiconductor junction diode and the first conductor or between the semiconductor junction diode and the second conductor. Numerous other aspects are provided.
摘要翻译：提供了一种存储单元，其包括在第一和第二导体之间的第一导体，第二导体和半导体结二极管。半导体结二极管与半导体结二极管不与具有小于12％的晶格失配的材料接触。此外，在半导体结二极管和第一导体之间或半导体结二极管和第二导体之间设置不具有通过施加编程电压大于2的电阻而改变其电阻的电阻切换元件。提供了许多其他方面。

63. 发明授权

US08431492B2 Memory cell that includes a sidewall collar for pillar isolation and methods of forming the same 有权
标题翻译：存储单元，其包括用于柱隔离的侧壁套圈及其形成方法
公开(公告)号：US08431492B2
公开(公告)日：2013-04-30
申请号：US12698761
申请日：2010-02-02
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L21/311
CPC分类号： H01L45/124 , G11C13/0002 , G11C13/0007 , G11C13/025 , G11C17/16 , G11C2213/35 , G11C2213/72 , H01L27/1021 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/149 , H01L45/16 , H01L45/1675
摘要： In a first embodiment, a method of forming a memory cell is provided that includes (a) forming one or more layers of steering element material above a substrate; (b) etching a portion of the steering element material to form a pillar of steering element material having an exposed sidewall; (c) forming a sidewall collar along the exposed sidewall of the pillar; and (d) forming a memory cell using the pillar. Numerous other aspects are provided.
摘要翻译：在第一实施例中，提供了形成存储单元的方法，其包括：（a）在基板上方形成一层或多层操纵元件材料; （b）蚀刻所述操纵元件材料的一部分以形成具有暴露侧壁的操纵元件材料的支柱; （c）沿着柱的暴露的侧壁形成侧壁套环; 和（d）使用该柱形成存储单元。提供了许多其他方面。

64. 发明授权

US08227787B2 Heterojunction device comprising a semiconductor and a resistivity-switching oxide or nitride 有权
标题翻译：异质结装置包括半导体和电阻率切换氧化物或氮化物
公开(公告)号：US08227787B2
公开(公告)日：2012-07-24
申请号：US13007812
申请日：2011-01-17
申请人： Tanmay Kumar , S. Brad Herner
发明人： Tanmay Kumar , S. Brad Herner
IPC分类号： H01L29/02 , H01L47/00
CPC分类号： H01L29/868 , H01L21/84 , H01L27/1021 , H01L27/2409 , H01L29/165 , H01L29/22 , H01L29/267 , H01L29/417 , H01L29/737 , H01L29/8615 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： In the present invention, a metal oxide or nitride compound which is a wide-band-gap semiconductor abuts a silicon, germanium, or alloy of silicon and/or germanium of the opposite conductivity type to form a p-n heterojunction. This p-n heterojunction can be used to advantage in various devices. In preferred embodiments, one terminal of a vertically oriented p-i-n heterojunction diode is a metal oxide or nitride layer, while the rest of the diode is formed of a silicon or silicon-germanium resistor. For example, a diode may include a heavily doped n-type silicon region, an intrinsic silicon region, and a nickel oxide layer serving as the p-type terminal. Many of these metal oxides and nitrides exhibit resistivity-switching behavior, and such a heterojunction diode can be used in a nonvolatile memory cell, for example in a monolithic three dimensional memory array.
摘要翻译：在本发明中，作为宽带隙半导体的金属氧化物或氮化物化合物与相反导电型的硅和/或锗的硅，锗或合金相接触以形成p-n异质结。该p-n异质结可以用于各种装置中。在优选实施例中，垂直取向的p-i-n异质结二极管的一个端子是金属氧化物或氮化物层，而二极管的其余部分由硅或硅 - 锗电阻器形成。例如，二极管可以包括重掺杂的n型硅区，本征硅区和用作p型端的氧化镍层。这些金属氧化物和氮化物中的许多表现出电阻率切换行为，并且这种异质结二极管可以用在非易失性存储单元中，例如在单片三维存储器阵列中。

65. 发明授权

US08178419B2 Method to texture a lamina surface within a photovoltaic cell 有权
标题翻译：纹理光伏电池内薄片表面的方法
公开(公告)号：US08178419B2
公开(公告)日：2012-05-15
申请号：US12343420
申请日：2008-12-23
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L21/30
CPC分类号： H01L31/0236 , H01L31/02363 , H01L31/028 , H01L31/03921 , H01L31/1804 , H01L31/1892 , Y02E10/547 , Y02E10/548 , Y02P70/521
摘要： It is advantageous to create texture at the surface of a photovoltaic cell to reduce reflection and increase travel length of light within the cell. A method is disclosed to create texture at the surface of a silicon body by reacting a silicide-forming metal at the surface, where the silicide-silicon interface is non-planar, then stripping the silicide, leaving behind a textured surface. Depending on the metal and the conditions of silicide formation, the resulting surface may be faceted. The peak-to-valley height of this texturing will generally be between about 300 and about 5000 angstroms, which is well-suited for use in photovoltaic cells comprising a thin silicon lamina.
摘要翻译：有利的是在光伏电池的表面处产生纹理以减少反射并增加电池内的光的行进长度。公开了一种通过使表面处的硅化物形成金属（其中硅化物 - 硅界面是非平面的）反应然后剥离硅化物，留下纹理表面来在硅体的表面上产生纹理的方法。取决于金属和硅化物形成的条件，所得到的表面可以是刻面的。该纹理的峰谷高度通常在约300至约5000埃之间，这非常适用于包含薄硅层的光伏电池。

66. 发明授权

US08173486B2 Memory cell that employs a selectively grown reversible resistance-switching element and methods of forming the same 有权
标题翻译：采用选择性生长的可逆电阻切换元件的存储单元及其形成方法
公开(公告)号：US08173486B2
公开(公告)日：2012-05-08
申请号：US12915290
申请日：2010-10-29
申请人： April D. Schricker , S. Brad Herner , Mark H. Clark
发明人： April D. Schricker , S. Brad Herner , Mark H. Clark
IPC分类号： H01L29/02
CPC分类号： H01L45/1641 , G11C13/0007 , G11C2213/31 , G11C2213/33 , G11C2213/56 , G11C2213/71 , G11C2213/72 , G11C2213/79 , H01L27/2409 , H01L27/2436 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/1633 , H01L45/1675
摘要： In some aspects, a method of forming a memory cell is provided that includes (1) forming a steering element above a substrate; and (2) selectively forming a reversible resistance-switching element coupled to the steering element by: (a) forming a material layer on the substrate; (b) etching the material layer; and (c) oxidizing the etched material layer to form a reversible resistance-switching material. Numerous other aspects are provided.
摘要翻译：在一些方面，提供一种形成存储单元的方法，其包括：（1）在基板上形成操纵元件; 和（2）通过以下步骤选择性地形成耦合到所述操舵元件的可逆电阻切换元件：（a）在所述基板上形成材料层; （b）蚀刻材料层; 和（c）氧化蚀刻的材料层以形成可逆电阻切换材料。提供了许多其他方面。

67. 发明申请

US20120056147A1 LARGE ARRAY OF UPWARD POINTINIG P-I-N DIODES HAVING LARGE AND UNIFORM CURRENT 有权
标题翻译：具有大电流和均匀电流的上升点阵电位器P-I-N二极管
公开(公告)号：US20120056147A1
公开(公告)日：2012-03-08
申请号：US13294224
申请日：2011-11-11
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L45/00
CPC分类号： H01L45/122 , B82Y10/00 , G11C13/0007 , G11C17/16 , G11C2213/16 , G11C2213/32 , G11C2213/71 , H01L27/1021 , H01L27/24 , H01L27/2409 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/145 , H01L45/146 , H01L45/149 , H01L45/16 , Y10S977/742 , Y10S977/842
摘要： A circuit is provided that includes a plurality of vertically oriented p-i-n diodes. Each p-i-n diode is coupled to a resistivity-switching element and includes a bottom heavily doped p-type region. When a voltage between about 1.5 volts and about 3.0 volts is applied across each p-i-n diode, a current of at least 1.5 microamps flows through 99 percent of the p-i-n diodes. Numerous other aspects are also provided.
摘要翻译：提供了包括多个垂直取向的p-i-n二极管的电路。每个p-i-n二极管耦合到电阻率开关元件并且包括底部重掺杂p型区域。当在每个p-i-n二极管之间施加约1.5伏和约3.0伏之间的电压时，至少1.5微安的电流流过99％的p-i-n二极管。还提供了许多其他方面。

68. 发明授权

US08004013B2 Polycrystalline thin film bipolar transistors 有权
标题翻译：多晶薄膜双极晶体管
公开(公告)号：US08004013B2
公开(公告)日：2011-08-23
申请号：US11763816
申请日：2007-06-15
申请人： Christopher J Petti , S. Brad Herner
发明人： Christopher J Petti , S. Brad Herner
IPC分类号： H01L31/0336 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/7317 , G11C5/025 , G11C11/416 , H01L27/0688 , H01L27/1022 , H01L29/456 , H01L29/735
摘要： A semiconductor device comprising a bipolar transistor having a base region, an emitter region and a collector region, wherein the base region comprises polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide is described. The emitter region and collector region also may comprise polycrystalline semiconductor material formed by crystallizing silicon, germanium or silicon germanium in contact with a silicide, germanide or silicide germanide forming metal. The polycrystalline semiconductor material is preferably silicided polysilicon, which is formed in contact with C49 phase titanium silicide.
摘要翻译：一种半导体器件，包括具有基极区域，发射极区域和集电极区域的双极晶体管，其中所述基极区域包括通过使与硅化物，锗化物或硅化物锗化物接触的硅，锗或锗锗结晶而形成的多晶半导体材料。发射极区域和集电极区域还可以包括通过使硅，锗或锗锗与硅化物，锗化锗或锗化锗形成金属接触而形成的多晶半导体材料。多晶半导体材料优选为与C49相钛硅化物接触形成的硅化多晶硅。

69. 发明申请

US20110186797A1 MEMORY CELL THAT INCLUDES A SIDEWALL COLLAR FOR PILLAR ISOLATION AND METHODS OF FORMING THE SAME 有权
标题翻译：包含用于支柱隔离的小眼镜的记忆细胞及其形成方法
公开(公告)号：US20110186797A1
公开(公告)日：2011-08-04
申请号：US12698761
申请日：2010-02-02
申请人： S. Brad Herner
发明人： S. Brad Herner
IPC分类号： H01L47/00 , H01L21/02 , H01L21/329 , H01L29/04 , H01L23/525 , H01L29/06
CPC分类号： H01L45/124 , G11C13/0002 , G11C13/0007 , G11C13/025 , G11C17/16 , G11C2213/35 , G11C2213/72 , H01L27/1021 , H01L27/2409 , H01L27/2418 , H01L27/2481 , H01L45/04 , H01L45/1233 , H01L45/146 , H01L45/149 , H01L45/16 , H01L45/1675
摘要： In a first embodiment, a method of forming a memory cell is provided that includes (a) forming one or more layers of steering element material above a substrate; (b) etching a portion of the steering element material to form a pillar of steering element material having an exposed sidewall; (c) forming a sidewall collar along the exposed sidewall of the pillar; and (d) forming a memory cell using the pillar. Numerous other aspects are provided.
摘要翻译：在第一实施例中，提供了形成存储单元的方法，其包括：（a）在基板上方形成一层或多层操纵元件材料; （b）蚀刻所述操纵元件材料的一部分以形成具有暴露侧壁的操纵元件材料的支柱; （c）沿着柱的暴露的侧壁形成侧壁套环; 和（d）使用该柱形成存储单元。提供了许多其他方面。

70. 发明申请

US20110076796A1 INTERMETAL STACK FOR USE IN A PHOTOVOLTAIC CELL 有权
标题翻译：用于光伏电池的间隔堆叠
公开(公告)号：US20110076796A1
公开(公告)日：2011-03-31
申请号：US12571415
申请日：2009-09-30
申请人： S. Brad Herner , Mark H. Clark
发明人： S. Brad Herner , Mark H. Clark
IPC分类号： H01L31/18
CPC分类号： H01L31/0747 , H01L21/187 , H01L31/1804 , H01L31/1896 , Y02E10/547 , Y02P70/521
摘要： A donor silicon wafer may be bonded to a substrate and a lamina cleaved from the donor wafer. A photovoltaic cell may be formed from the lamina bonded to the substrate. An intermetal stack is described that is optimized for use in such a cell. The intermetal stack may include a transparent conductive oxide layer serving as a quarter-wave plate, a low resistance layer, an adhesion layer to help adhesion to the receiver element, and may also include a barrier layer to prevent or impede unwanted diffusion within the stack.
摘要翻译：供体硅晶片可以结合到基底和从施主晶片分离的薄片。可以从结合到衬底的薄片形成光伏电池。描述了优化用于这种电池的金属间堆叠。金属间堆叠可以包括用作四分之一波片的透明导电氧化物层，低电阻层，用于帮助粘附到接收器元件的粘合层，并且还可以包括防止或阻碍堆叠内的不期望扩散的阻挡层。

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