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61. 发明授权

US06730601B2 Methods for fabricating a metal-oxide-metal capacitor 有权
标题翻译：制造金属氧化物 - 金属电容器的方法
公开(公告)号：US06730601B2
公开(公告)日：2004-05-04
申请号：US10080186
申请日：2002-02-21
申请人： Edward Belden Harris , Yifeng Winston Yan , Sailesh Mansinh Merchant
发明人： Edward Belden Harris , Yifeng Winston Yan , Sailesh Mansinh Merchant
IPC分类号： H01L2144
CPC分类号： H01L28/75 , H01L21/28568 , H01L21/76807
摘要： A method of fabricating a metal-oxide-metal capacitor in a microelectronic device is provided. First, a recess is formed in a surface of a dielectric layer deposited over a microelectronic substrate. A first barrier layer is then deposited over the dielectric layer such that the first barrier layer conforms to the recess. A first conductive element is then deposited over the first barrier layer so as to at least fill the recess. A second barrier layer is further deposited over the first conductive element such that the first barrier layer and the second barrier layer cooperate to encapsulate the first conductive element. The first conductive element thus comprises a first plate of the capacitor. A capacitor dielectric layer is then deposited over the second barrier layer, followed by the deposition of a second conductive element over the capacitor dielectric layer. The second conductive element thus comprises a second plate of the capacitor. In one embodiment, the dielectric layer may be comprised of an oxide and the barrier layers are comprised of, for example, tantalum; tantalum nitride; titanium nitride; tungsten nitride; silicon nitrides of tantalum, titanium, and tungsten; and combinations thereof. The first conductive element is preferably comprised of copper. The capacitor dielectric may be comprised of an oxide or tantalum pentoxide, while the second conductive element may be comprised of a layer of an aluminum alloy disposed between two barrier layers, each comprised of, for example, tantalum; tantalum nitride; titanium nitride; tungsten nitride; silicon nitrides of tantalum, titanium, and tungsten; and combinations thereof. Associated apparatuses are also provided.
摘要翻译：提供了一种在微电子器件中制造金属氧化物 - 金属电容器的方法。首先，在沉积在微电子衬底上的电介质层的表面上形成凹部。然后在电介质层上沉积第一阻挡层，使得第一阻挡层符合凹陷。然后将第一导电元件沉积在第一阻挡层上，以便至少填充凹部。第二阻挡层进一步沉积在第一导电元件上，使得第一阻挡层和第二阻挡层协作以封装第一导电元件。因此，第一导电元件包括电容器的第一板。然后在第二阻挡层上沉积电容器电介质层，随后在电容器介电层上沉积第二导电元件。因此，第二导电元件包括电容器的第二板。在一个实施例中，电介质层可以由氧化物构成，并且阻挡层由例如钽构成; 氮化钽; 氮化钛; 氮化钨; 钽，钛和钨的氮化硅; 及其组合。第一导电元件优选由铜构成。电容器电介质可以由氧化物或五氧化二钽组成，而第二导电元件可以由设置在两个阻挡层之间的铝合金层组成，每个阻挡层由例如钽构成; 氮化钽; 氮化钛; 氮化钨; 钽，钛和钨的氮化硅; 及其组合。还提供了相关装置。

62. 发明授权

US06727588B1 Diffusion preventing barrier layer in integrated circuit inter-metal layer dielectrics 有权
标题翻译：集成电路金属间介质中的防扩散阻挡层
公开(公告)号：US06727588B1
公开(公告)日：2004-04-27
申请号：US09377386
申请日：1999-08-19
申请人： Mahjoub Ali Abdelgadir , Nace Layadi , Sailesh Mansinh Merchant , Vivek Saxena , Pei H. Yih
发明人： Mahjoub Ali Abdelgadir , Nace Layadi , Sailesh Mansinh Merchant , Vivek Saxena , Pei H. Yih
IPC分类号： H01L2348
CPC分类号： H01L23/5329 , H01L21/76829 , H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A cap or barrier layer that can prevent the migration of impurities in low dielectric constant material, thereby preventing the impurities from attacking conductive elements in subsequent levels of a multi-level integrated circuit structure. The integrated circuit by may be fabricated by disposing the diffusion-preventing barrier layer between a first dielectric layer and the conductive layer at an upper level of the integrated circuit. The diffusion preventing barrier layer may be formed in-situ over the impurity containing dielectric material with the subsequent disposition of a metal layer thereover, and further processing of a multi-layer dielectric structure to include polishing. The in-situ deposition of the cap or barrier layer prevents the exposure of the impurity containing layer to atmosphere, thereby avoiding contamination of the layer by moisture absorption, hydrogen absorption, or the like. In an exemplary embodiment, the diffusion preventing barrier layer is a material containing silicon oxide or silicon rich silicon oxide SiOx, where x is preferably less than 2.
摘要翻译：可以防止杂质在低介电常数材料中迁移的帽或阻挡层，从而防止杂质在多级集成电路结构的后续级别中侵袭导电元件。集成电路可以通过在集成电路的上层设置第一介电层和导电层之间设置防扩散阻挡层来制造。扩散防止阻挡层可以在含杂质的电介质材料上的原位形成，随后在其上布置金属层，并且进一步处理多层电介质结构以包括抛光。帽或阻挡层的原位沉积防止了含杂质层暴露于大气中，从而避免了由吸湿，吸氢等引起的层的污染。在示例性实施例中，防扩散阻挡层是含有氧化硅或富硅氧化硅SiO x的材料，其中x优选小于2。

63. 发明授权

US06455418B1 Barrier for copper metallization 有权
标题翻译：铜金属化阻挡层
公开(公告)号：US06455418B1
公开(公告)日：2002-09-24
申请号：US09723557
申请日：2000-11-28
申请人： Siddhartha Bhowmik , Sailesh Chittipeddi , Sailesh Mansinh Merchant
发明人： Siddhartha Bhowmik , Sailesh Chittipeddi , Sailesh Mansinh Merchant
IPC分类号： H01L214763
CPC分类号： H01L21/76846 , H01L21/76843 , H01L21/76877 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The invention includes a process for copper metallization of an integrated circuit, comprising the steps of forming tantalum on a substrate, forming tantalum nitride over the tantalum, forming titanium nitride over the tantalum nitride, forming copper over the titanium nitride and integrated circuits made thereby. The invention is particularly useful in forming damascene structures with large aspect ratios.
摘要翻译：本发明包括一种用于集成电路的铜金属化的方法，包括在衬底上形成钽的步骤，在钽上形成氮化钽，在氮化钽上形成氮化钛，在氮化钛上形成铜并在其上形成集成电路。本发明特别可用于形成具有大纵横比的镶嵌结构。

64. 发明授权

US06373087B1 Methods of fabricating a metal-oxide-metal capacitor and associated apparatuses 有权
标题翻译：制造金属 - 氧化物 - 金属电容器及相关装置的方法
公开(公告)号：US06373087B1
公开(公告)日：2002-04-16
申请号：US09652479
申请日：2000-08-31
申请人： Edward Belden Harris , Yifeng Winston Yan , Sailesh Mansinh Merchant
发明人： Edward Belden Harris , Yifeng Winston Yan , Sailesh Mansinh Merchant
IPC分类号： H01L31119
CPC分类号： H01L28/75 , H01L21/28568 , H01L21/76807
摘要： A method of fabricating a metal-oxide-metal capacitor in a microelectronic device is provided. First, a recess is formed in a surface of a dielectric layer deposited over a microelectronic substrate. A first barrier layer is then deposited over the dielectric layer such that the first barrier layer conforms to the recess. A first conductive element is then deposited over the first barrier layer so as to at least fill the recess. A second barrier layer is further deposited over the first conductive element such that the first barrier layer and the second barrier layer cooperate to encapsulate the first conductive element. The first conductive element thus comprises a first plate of the capacitor. A capacitor dielectric layer is then deposited over the second barrier layer, followed by the deposition of a second conductive element over the capacitor dielectric layer. The second conductive element thus comprises a second plate of the capacitor. In one embodiment, the dielectric layer may be comprised of an oxide and the barrier layers are comprised of, for example, tantalum; tantalum nitride; titanium nitride; tungsten nitride; silicon nitrides of tantalum, titanium, and tungsten; and combinations thereof. The first conductive element is preferably comprised of copper. The capacitor dielectric may be comprised of an oxide or tantalum pentoxide, while the second conductive element may be comprised of a layer of an aluminum alloy disposed between two barrier layers, each comprised of, for example, tantalum; tantalum nitride; titanium nitride; tungsten nitride; silicon nitrides of tantalum, titanium, and tungsten; and combinations thereof. Associated apparatuses are also provided.
摘要翻译：提供了一种在微电子器件中制造金属氧化物 - 金属电容器的方法。首先，在沉积在微电子衬底上的电介质层的表面上形成凹部。然后在电介质层上沉积第一阻挡层，使得第一阻挡层符合凹陷。然后将第一导电元件沉积在第一阻挡层上，以便至少填充凹部。第二阻挡层进一步沉积在第一导电元件上，使得第一阻挡层和第二阻挡层协作以封装第一导电元件。因此，第一导电元件包括电容器的第一板。然后在第二阻挡层上沉积电容器电介质层，随后在电容器介电层上沉积第二导电元件。因此，第二导电元件包括电容器的第二板。在一个实施例中，电介质层可以由氧化物构成，并且阻挡层由例如钽构成; 氮化钽; 氮化钛; 氮化钨; 钽，钛和钨的氮化硅; 及其组合。第一导电元件优选由铜构成。电容器电介质可以由氧化物或五氧化二钽组成，而第二导电元件可以由设置在两个阻挡层之间的铝合金层组成，每个阻挡层由例如钽构成; 氮化钽; 氮化钛; 氮化钨; 钽，钛和钨的氮化硅; 及其组合。还提供了相关装置。

65. 发明授权

US6136159A Method for depositing metal 有权
标题翻译：沉积金属的方法
公开(公告)号：US6136159A
公开(公告)日：2000-10-24
申请号：US276086
申请日：1998-11-06
申请人： Joseph William Buckfeller , Sailesh Chittipeddi , Sailesh Mansinh Merchant
发明人： Joseph William Buckfeller , Sailesh Chittipeddi , Sailesh Mansinh Merchant
IPC分类号： C23C14/34 , C23C14/50 , C23C14/54 , C23C16/12 , C23C16/46 , C23C16/50 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768
CPC分类号： H01L21/2855 , C23C14/50 , C23C14/541 , H01L21/76877
摘要： A method of depositing aluminum or other metals so that vias are more completely filled is disclosed. The wafer or substrate is preheated to a temperature of approximately 200.degree. C. Then the wafer is placed in an ambient of approximately 350.degree. C. while metal deposition commences. The resulting metal layer has a gradually increasing grain size and exhibits improved via filling. Also disclosed is a method and apparatus (involving cooling of support structures) for deposition of an antireflective coating to prevent rainbowing or spiking of the coating into the underlying metal.
摘要翻译：公开了一种沉积铝或其它金属使得通孔更完全填充的方法。将晶片或衬底预热至约200℃的温度。然后将晶片置于约350℃的环境中，同时开始金属沉积。所得到的金属层具有逐渐增加的晶粒尺寸并表现出改进的通孔填充。还公开了一种用于沉积抗反射涂层的方法和装置（包括冷却支撑结构），以防止涂层向底层金属中起彩虹或尖峰。

66. 发明授权

US6034405A Bonding of aluminum oxide components to silicons substrates 失效
标题翻译：氧化铝组分与硅衬底的接合
公开(公告)号：US6034405A
公开(公告)日：2000-03-07
申请号：US899291
申请日：1997-07-22
申请人： Michael Francis Brady , Mindaugas Fernand Dautartas , James F. Dormer , Sailesh Mansinh Merchant , Casimir Roman Nijander , John William Osenbach
发明人： Michael Francis Brady , Mindaugas Fernand Dautartas , James F. Dormer , Sailesh Mansinh Merchant , Casimir Roman Nijander , John William Osenbach
IPC分类号： G02B6/42 , H01L31/0232 , G02B6/32 , H01L31/00
CPC分类号： G02B6/4204 , G02B6/4236 , G02B6/4244 , G02B6/4257 , G02B6/4274
摘要： The invention is a method and resulting device which provides a strong bond between a silicon substrate and an oxide component mounted within a cavity in the substrate. A layer of titanium, for example, is deposited on the walls of the cavity, followed by deposition of a layer of aluminum. The structure is preferably annealed to form titanium silicide and titanium-aluminum interface layers. The component is then bonded to the aluminum layer.
摘要翻译：本发明是一种方法和产生的装置，其在硅衬底和安装在衬底中的空腔内的氧化物组件之间提供强结合。例如，一层钛沉积在空腔的壁上，随后沉积一层铝。该结构优选被退火以形成硅化钛和钛 - 铝界面层。然后将该组分结合到铝层。

67. 发明授权

US5972179A Silicon IC contacts using composite TiN barrier layer 失效
标题翻译：硅IC接触使用复合TiN阻挡层
公开(公告)号：US5972179A
公开(公告)日：1999-10-26
申请号：US941556
申请日：1997-09-30
申请人： Sailesh Chittipeddi , Sailesh Mansinh Merchant
发明人： Sailesh Chittipeddi , Sailesh Mansinh Merchant
IPC分类号： H01L21/28 , C23C14/04 , C23C14/06 , C23C16/04 , C23C16/34 , H01L21/768 , C23C14/14
CPC分类号： C23C14/046 , C23C14/0641 , C23C16/34 , H01L21/76843 , H01L21/76856
摘要： The specification describes a composite TiN barrier layer structure formed by depositing a first TiN layer by CVD to obtain good step coverage, followed by a second TiN layer formed by PVD to obtain uniform surface morphology for subsequent deposition of an aluminum alloy contact layer. Alternatively, uniform TiN layer morphology is obtained by depositing multiple CVD TiN layers as a series of thin strata, and passivating after each deposition step to fully crystallize each stratum thereby obtaining a uniformly crystallized barrier layer.
摘要翻译：该说明书描述了通过CVD沉积第一TiN层以获得良好的台阶覆盖形成的复合TiN阻挡层结构，随后是由PVD形成的第二TiN层，以获得均匀的表面形态，以便随后沉积铝合金接触层。或者，通过将多个CVD TiN层作为一系列薄层沉积而获得均匀的TiN层形态，并且在每个沉积步骤之后钝化以使每个层完全结晶，从而获得均匀结晶的阻挡层。

68. 发明授权

US5935396A Method for depositing metal 失效
标题翻译：沉积金属的方法
公开(公告)号：US5935396A
公开(公告)日：1999-08-10
申请号：US843125
申请日：1997-04-25
申请人： Joseph William Buckfeller , Sailesh Chittipeddi , Sailesh Mansinh Merchant
发明人： Joseph William Buckfeller , Sailesh Chittipeddi , Sailesh Mansinh Merchant
IPC分类号： C23C14/34 , C23C14/50 , C23C14/54 , C23C16/12 , C23C16/46 , C23C16/50 , H01L21/28 , H01L21/285 , H01L21/3205 , H01L21/768
CPC分类号： H01L21/2855 , C23C14/50 , C23C14/541 , H01L21/76877
摘要： A method of depositing aluminum or other metals so that vias are more completely filled is disclosed. The wafer or substrate is preheated to a temperature of approximately 200.degree. C. Then the wafer is placed in an ambient of approximately 350.degree. C. while metal deposition commences. The resulting metal layer has a gradually increasing grain size and exhibits improved via filling. Also disclosed is a method and apparatus (involving cooling of support structures) for deposition of an anti-reflective coating to prevent rainbowing or spiking of the coating into the underlying metal.
摘要翻译：公开了一种沉积铝或其它金属使得通孔更完全填充的方法。将晶片或衬底预热至约200℃的温度。然后将晶片置于约350℃的环境中，同时开始金属沉积。所得到的金属层具有逐渐增加的晶粒尺寸并表现出改进的通孔填充。还公开了一种方法和装置（包括冷却支撑结构），用于沉积防反射涂层，以防止涂层向底层金属中起彩虹或尖峰。

69. 发明授权

US5798300A Method for forming conductors in integrated circuits 失效
标题翻译：在集成电路中形成导体的方法
公开(公告)号：US5798300A
公开(公告)日：1998-08-25
申请号：US857079
申请日：1997-05-15
申请人： Sailesh Chittipeddi , Sailesh Mansinh Merchant
发明人： Sailesh Chittipeddi , Sailesh Mansinh Merchant
IPC分类号： H01L21/285 , H01L21/203 , H01L21/768 , H01L21/28
CPC分类号： H01L21/76877
摘要： A method of forming electromigration resistant integrated circuit runners is disclosed. A collimated beam of particles is directed toward a substrate to form a metal nucleating layer. Then a non-collimated beam is used to form the rest of the metal layer. Then the layers are patterned to form runners.
摘要翻译：公开了一种形成电迁移集成电路流道的方法。准直的颗粒束指向基板以形成金属成核层。然后使用非平行光束形成金属层的其余部分。然后将这些层图案化以形成流道。

70. 发明授权

US07301107B2 Semiconductor device having reduced intra-level and inter-level capacitance 有权
标题翻译：具有降低的电平和电平间电容的半导体器件
公开(公告)号：US07301107B2
公开(公告)日：2007-11-27
申请号：US10694611
申请日：2003-10-27
申请人： Subramanian Karthikeyan , Sailesh Mansinh Merchant
发明人： Subramanian Karthikeyan , Sailesh Mansinh Merchant
IPC分类号： H05K1/11
CPC分类号： H01L23/5222 , H01L21/565 , H01L21/76807 , H01L21/76832 , H01L21/76834 , H01L21/76835 , H01L23/49575 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure of a semiconductor device designed for reduced intralevel and interlevel capacitance, and includes a lower metal layer and an upper metal layer and an insulating layer interposed between metal layers. Each of the lower metal layer and upper metal layer include a plurality of conductive lines spaced apart and extending within a low-k dielectric material. A plurality of metal-filled vias interconnects the conductive lines of the lower metal layer to the conductive lines of the upper metal layer. The insulating layer comprises also comprises a low-k dielectric material disposed between the adjacent metal-filled vias. Openings, having been etched in the low-k dielectric material between the conductive lines of the upper and lower metal layers, and the metal-filled vias, an ultra-low k material is deposited within the openings. The integration of the ultra-low k and low-d dielectric materials reduces the overall capacitance of the structure to enhance performance.
摘要翻译：设计用于降低层间和层间电容的半导体器件的互连结构，并且包括下金属层和上金属层以及介于金属层之间的绝缘层。下金属层和上金属层中的每一个包括间隔开并在低k电介质材料内延伸的多条导线。多个金属填充的通孔将下金属层的导线与上金属层的导电线互连。绝缘层还包括设置在相邻的金属填充通孔之间的低k电介质材料。已经在上下金属层的导电线之间的低k电介质材料中蚀刻的开口和金属填充的通孔，在开口内沉积超低k材料。超低k和低d介电材料的集成降低了结构的总体电容以增强性能。

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