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61. 发明申请

US20060100227A1 Pyrimidine derivaties 有权
标题翻译：嘧啶衍生物
公开(公告)号：US20060100227A1
公开(公告)日：2006-05-11
申请号：US10507060
申请日：2003-03-14
申请人： Rolf Baenteli , Gerhard Zenke , Nigel Cooke , Rudolf Duthaler , Gebhard Thoma , Anette Von Matt , Toshiyuki Honda , Naoko Matsuura , Kazuhiko Nonomura , Osamu Ohmori , Ichiro Umemura , Klaus Hinterding , Christos Papageorgiou
发明人： Rolf Baenteli , Gerhard Zenke , Nigel Cooke , Rudolf Duthaler , Gebhard Thoma , Anette Von Matt , Toshiyuki Honda , Naoko Matsuura , Kazuhiko Nonomura , Osamu Ohmori , Ichiro Umemura , Klaus Hinterding , Christos Papageorgiou
IPC分类号： A61K31/505 , C07D403/02 , C07D239/48
CPC分类号： C07D239/48 , A61K31/505 , A61K31/506 , A61K31/5377 , A61K31/55 , A61K45/06 , C07D231/12 , C07D233/56 , C07D249/08 , C07D401/12 , C07D401/14 , C07D403/12 , C07D417/12
摘要： There are provided compounds of formula I Wherein X, R1, R2, R3, R4, R5, R6, R7, R8 and R9 are as indicated in claim 1, useful in disorders where ZAP-70 and/or Syk inhibition plays a role or caused by a malfunction of signal cascades connected with FAK.
摘要翻译：提供式I的化合物，其中X，R 1，R 2，R 3，R 4， R 5，R 6，R 7，R 8和R 9均为如权利要求1所述，其可用于ZAP-70和/或Syk抑制作用或由与FAK连接的信号级联的故障引起的疾病中。

62. 发明申请

US20050275741A1 Image pickup device and production method thereof 有权
标题翻译：摄像装置及其制作方法
公开(公告)号：US20050275741A1
公开(公告)日：2005-12-15
申请号：US10968111
申请日：2004-10-20
申请人： Naoyuki Watanabe , Toshiyuki Honda , Yoshito Akutagawa , Susumu Moriya , Izumi Kobayashi
发明人： Naoyuki Watanabe , Toshiyuki Honda , Yoshito Akutagawa , Susumu Moriya , Izumi Kobayashi
IPC分类号： H01L27/14 , H01L23/00 , H01L27/146 , H01L31/0203 , H01L31/0232 , H04N5/225 , H04N5/257 , H04N5/335
CPC分类号： H01L31/0203 , H01L24/97 , H01L27/14618 , H01L27/14625 , H01L27/14627 , H01L31/02325 , H01L31/02327 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/97 , H01L2924/12043 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H04N5/2254 , H01L2924/00014 , H01L2924/00
摘要： An image pickup device is disclosed that has little deformation caused by thermal expansion of a transparent resin for sealing an image pickup element. The image pickup device includes an image pickup element having a light receiving surface, a micro-lens for condensing incident light to the image pickup element, a first transparent plate disposed on the light receiving surface of the image pickup element with the micro-lens in between, a transparent resin that seals the image pickup element and the first transparent plate, and a second transparent plate disposed on the transparent resin to face the first transparent plate.
摘要翻译：公开了一种由用于密封图像拾取元件的透明树脂的热膨胀引起的变形小的图像拾取装置。图像拾取装置包括具有光接收表面的图像拾取元件，用于将入射光聚焦到图像拾取元件的微透镜，设置在图像拾取元件的光接收表面上的第一透明板，微透镜密封图像拾取元件的透明树脂和第一透明板，以及设置在透明树脂上以面对第一透明板的第二透明板。

63. 发明授权

US06922768B2 Non-volatile storage device and control method thereof 失效
标题翻译：非易失性存储装置及其控制方法
公开(公告)号：US06922768B2
公开(公告)日：2005-07-26
申请号：US10415126
申请日：2002-08-16
申请人： Toshiyuki Honda , Tetsushi Kasahara , Masayuki Toyama , Teruo Akashi , Keisuke Sakai
发明人： Toshiyuki Honda , Tetsushi Kasahara , Masayuki Toyama , Teruo Akashi , Keisuke Sakai
IPC分类号： G11C16/02 , G06F12/00 , G06F12/02
CPC分类号： G06F12/0246
摘要： To provide a nonvolatile storage device and control method thereof which improve convenience of portable devices by shortening initialization time. In generating a data validity table at initialization, a control part firstly reads out a validity flag and a second translation table. In the case where the validity flag is valid, logical blocks in the second translation table are valid. For that reason, the fourth table generation means can set all logical blocks in the second translation table as being valid, in the data validity table. In a single reading as mentioned above, the fourth table generation means can carry out setting with respect to a plurality of logical blocks. Further, with respect to a partial logical block which is set as being valid in the data validity table, it is possible to bypass reading out the data validity flag of the block and proceed to operation of next partial logical block.
摘要翻译：提供一种通过缩短初始化时间来提高便携式设备的便利性的非易失性存储装置及其控制方法。在初始化时生成数据有效性表时，控制部首先读出有效标志和第二转换表。在有效标志有效的情况下，第二转换表中的逻辑块是有效的。为此，第四表生成装置可以在数据有效性表中将第二转换表中的所有逻辑块设置为有效。在如上所述的单次读取中，第四表生成装置可以执行关于多个逻辑块的设置。此外，对于在数据有效性表中被设置为有效的部分逻辑块，可以绕过读出块的数据有效性标志并进行下一个部分逻辑块的操作。

64. 发明授权

US06872998B2 Ferroelectric memory device 失效
标题翻译：铁电存储器件
公开(公告)号：US06872998B2
公开(公告)日：2005-03-29
申请号：US09333049
申请日：1999-06-15
申请人： Hiroshige Hirano , Toshiyuki Honda
发明人： Hiroshige Hirano , Toshiyuki Honda
IPC分类号： H01L27/10 , H01L21/02 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108 , H01L27/115 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/11502 , H01L28/55
摘要： A memory cell transistor using a word line WL as the gate thereof is provided in an active region OD, and a ferroelectric capacitor, including bottom electrode, ferroelectric film and top electrode TE, is formed on a field oxide film. A first interconnection layer is made up of storage lines, each connecting the top electrode TE to one of doped layers of the memory cell transistor, and bit lines, each of which is connected to the other doped layer. In a planar layout, the storage line-intersects only one side of the top electrode TE and the bit line BL does not overlap with the top electrode TE. Thus, it is possible to prevent the retention characteristics of the ferroelectric capacitor from being deteriorated due to the stress applied by the first interconnection layer to the ferroelectric capacitor. As a result, the reliability of a ferroelectric memory device, including, in a memory cell, a ferroelectric capacitor with a ferroelectric film interposed between the bottom and top electrodes, can be improved.
摘要翻译：使用字线WL作为其栅极的存储单元晶体管设置在有源区域OD中，并且在场氧化膜上形成包括底电极，铁电体膜和顶电极TE的铁电电容器。第一互连层由存储线组成，每个存储线将顶部电极TE连接到存储单元晶体管的一个掺杂层，以及位线，每个位线连接到另一个掺杂层。在平面布局中，存储线仅与顶部电极TE的一侧相交，并且位线BL不与顶部电极TE重叠。因此，可以防止由于第一互连层向强电介质电容器施加的应力而使铁电电容器的保持特性劣化。结果，可以提高包括在存储单元中的强电介质存储器件的可靠性，该铁电电容器具有置于底部和顶部电极之间的铁电体膜。

65. 发明授权

US06563330B1 Probe card and method of testing wafer having a plurality of semiconductor devices 有权
标题翻译：探针卡和测试具有多个半导体器件的晶片的方法
公开(公告)号：US06563330B1
公开(公告)日：2003-05-13
申请号：US09540870
申请日：2000-03-31
申请人： Shigeyuki Maruyama , Daisuke Koizumi , Naoyuki Watanabe , Yoshito Konno , Eiji Yoshida , Toshiyuki Honda , Toshimi Kawahara , Kenichi Nagashige
发明人： Shigeyuki Maruyama , Daisuke Koizumi , Naoyuki Watanabe , Yoshito Konno , Eiji Yoshida , Toshiyuki Honda , Toshimi Kawahara , Kenichi Nagashige
IPC分类号： G01R3102
CPC分类号： G01R31/2886 , H01L2224/05001 , H01L2224/05008 , H01L2224/05022 , H01L2224/05024 , H01L2224/05568 , H01L2224/05569 , H01L2224/05573 , H01L2224/11 , H05K3/326
摘要： A probe card for testing a wafer having formed a plurality of semiconductor chips, the probe card including a board and a multi-layer substrate. The probe card may also include a flexible substrate. A contact electrode, located opposite from an electrode on one of the chips, is disposed above or below the flexible substrate, or may be provided on an elastic material on the multi-layered substrate. A first wiring has a first portion connected to the contact electrode, a level transitioning portion extending from a level of the first portion to the multi-layer substrate at a lower level, and a connecting terminal at an end of the level transitioning portion connected to an internal terminal on the multi-layered substrate. A second wiring in the multi-layered substrate connects the internal terminal to an external terminal at a periphery of the multi-layer substrate. A third wiring on the board connects the external terminal on the multi-layer substrate to an external connecting terminal on the board. Displacements of the internal terminal resulting from the temperature load applied during testing of the wafer are compensated by the level transitioning portion of the first wiring. Unevenness involved with the contact between the contact electrodes on the probe card and the electrodes on the chips are compensated by the contact electrodes and/or elastic material according to the present invention. An electrode pitch of the contact electrodes is expanded by the first wiring.
摘要翻译：一种用于测试形成多个半导体芯片的晶片的探针卡，所述探针卡包括基板和多层基板。探针卡还可以包括柔性基底。在其中一个芯片上与电极相对设置的接触电极设置在柔性基板的上方或下方，或者可以设置在多层基板上的弹性材料上。第一布线具有连接到接触电极的第一部分，从第一部分的电平延伸到较低电平的多层基板的电平转换部分，以及连接到电平转换部分的端部处的连接端子多层基板上的内部端子。多层基板中的第二布线将内部端子连接到多层基板的外围的外部端子。电路板上的第三个接线将多层基板上的外部端子连接到电路板上的外部连接端子。在晶片测试期间施加的温度负载导致的内部端子的位移由第一布线的电平转换部分补偿。涉及探针卡上的接触电极和芯片上的电极之间的接触的不均匀性由根据本发明的接触电极和/或弹性材料补偿。接触电极的电极间距由第一布线扩大。

66. 发明授权

US5841698A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5841698A
公开(公告)日：1998-11-24
申请号：US697511
申请日：1996-08-26
申请人： Hiroshige Hirano , Toshiyuki Honda
发明人： Hiroshige Hirano , Toshiyuki Honda
IPC分类号： G11C5/14 , G11C7/06 , G11C16/26 , G11C16/06
CPC分类号： G11C7/067 , G11C16/26 , G11C5/143 , G11C2207/063
摘要： A semiconductor device includes a nonvolatile memory cell and a current detecting type sense amplifier for detecting a current flowing through a data line into the memory cell. The semiconductor device is further provided with an element for outputting a first voltage detecting signal when a detected supply voltage exceeds a set value and outputting a second voltage detecting signal when the detected supply voltage does not exceed the set value. The sense amplifier includes an element for switching a dependent characteristic of a level sensing current upon the supply voltage to be higher in response to the second voltage detecting signal that in response to the first voltage detecting signal. Thus, error reading of a data from the memory cell, which can be otherwise caused under application of a low supply voltage, can be avoided.
摘要翻译：半导体器件包括非易失性存储单元和电流检测型读出放大器，用于检测流过存储单元的数据线的电流。半导体器件还设置有用于当检测到的电源电压超过设定值时输出第一电压检测信号并在检测到的电源电压未超过设定值时输出第二电压检测信号的元件。感测放大器包括用于响应于响应于第一电压检测信号的第二电压检测信号而将电源电压上的电平感测电流的相关特性切换到更高的元件。因此，可以避免在应用低电源电压下可能导致来自存储单元的数据的错误读取。

67. 发明授权

US5831904A Non-volatile semiconductor memory device capable of conditioning over-erased memory cells 失效
标题翻译：能够调节过度擦除的存储单元的非易失性半导体存储器件
公开(公告)号：US5831904A
公开(公告)日：1998-11-03
申请号：US690790
申请日：1996-08-01
申请人： Hiroshige Hirano , Toshiyuki Honda
发明人： Hiroshige Hirano , Toshiyuki Honda
IPC分类号： G11C16/34 , G11C16/06
CPC分类号： G11C16/3409 , G11C16/3404
摘要： By setting full group reversal control gates to a logical voltage "H", memory cells on all bit lines of a memory cell array block are connected to a reversal voltage supply circuit so that a group reversal operation is performed. When one of the group reversal control gates is set to the logical voltage "H", the memory cells on the bit lines having either even or odd numbers of the memory cell array block are connected to the reversal voltage supply circuit so that a partial group reversal operation is performed. When one of column selection gates is set to the logical voltage "H", the selected bit line is connected to the reversal voltage supply circuit. Consequently, a line reversal operation for the memory cell connected to the selected bit line is performed. Thus, the high-speed reversal operation which fully controls the offleak current of the memory cell can be implemented and the low-voltage operation can be realized by changing the operation unit for performing the reversal operation.
摘要翻译：通过将全部组反转控制栅极设置为逻辑电压“H”，存储单元阵列块的所有位线上的存储单元连接到反向电压供应电路，从而执行组反转操作。当组反转控制门中的一个被设置为逻辑电压“H”时，具有偶数或奇数个存储单元阵列块的位线上的存储单元连接到反向电压供应电路，使得部分组执行反转操作。当列选择门之一被设置为逻辑电压“H”时，所选择的位线连接到反向电压供应电路。因此，执行连接到所选位线的存储单元的线路反向操作。因此，可以实现完全控制存储单元的截止电流的高速反转操作，并且可以通过改变用于执行反转操作的操作单元来实现低电压操作。

68. 发明授权

US5687126A Semiconductor device 失效
公开(公告)号：US5687126A
公开(公告)日：1997-11-11
申请号：US697507
申请日：1996-08-26
申请人： Hiroshige Hirano , Toshiyuki Honda
发明人： Hiroshige Hirano , Toshiyuki Honda
IPC分类号： G11C5/14 , G11C7/06 , G11C16/26
CPC分类号： G11C7/067 , G11C16/26 , G11C5/143 , G11C2207/063
摘要： A semiconductor device includes a nonvolatile memory cell and a current detecting type sense amplifier for detecting a current flowing through a data line into the memory cell. The semiconductor device is further provided with an element for outputting a first voltage detecting signal when a detected supply voltage exceeds a set value and outputting a second voltage detecting signal when the detected supply voltage does not exceed the set value. The sense amplifier includes an element for switching a dependent characteristic of a level sensing current upon the supply voltage to be higher in response to the second voltage detecting signal that in response to the first voltage detecting signal. Thus, error reading of a data from the memory cell, which can be otherwise caused under application of a low supply voltage, can be avoided.

69. 发明授权

US5463253A Semiconductor device having a plurality of chips 失效
标题翻译：具有多个芯片的半导体装置
公开(公告)号：US5463253A
公开(公告)日：1995-10-31
申请号：US246567
申请日：1994-05-20
申请人： Masaki Waki , Junichi Kasai , Tsuyoshi Aoki , Toshiyuki Honda , Hirotaka Sato
发明人： Masaki Waki , Junichi Kasai , Tsuyoshi Aoki , Toshiyuki Honda , Hirotaka Sato
IPC分类号： H01L23/495 , H01L23/28 , H01L23/16
CPC分类号： H01L23/49524 , H01L23/4951 , H01L23/49575 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L24/48 , H01L2924/00014 , H01L2924/01013 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/07802 , H01L2924/12042 , H01L2924/181
摘要： A semiconductor device includes lead frames (21) respectively having first main surfaces and second main surfaces opposite to each other, bonding being able to be performed on the first and second main surfaces, a first semiconductor chip (22) arranged on first main surface sides of the lead frames, first tape leads (23) electrically connecting the first main surfaces of the lead frames to the first semiconductor chip, a second semiconductor chip (24) arranged on second main surface sides of the lead frames, and second tape leads (25) electrically connecting the second main surfaces of the lead frames to the second semiconductor.
摘要翻译： PCT No.PCT / JP91 / 00348 Sec。 371日期：1991年11月14日 102（e）1991年11月14日PCT PCT 1991年3月14日PCT。出版物WO91 / 14282 日期：1991年9月19日。半导体器件包括分别具有彼此相对的第一主表面和第二主表面的引线框架（21），能够在第一和第二主表面上进行接合的第一半导体芯片（22 ），布置在引线框架的第一主表面侧上的第一引线（23）将引线框架的第一主表面电连接到第一半导体芯片，第二半导体芯片（24）布置在引线的第二主表面侧上框架和将引线框架的第二主表面电连接到第二半导体的第二带引线（25）。

70. 发明授权

US08898420B2 Non-volatile storage device and a memory controller controlling parity tables of recording regions of the non-volatile storage device 有权
标题翻译：非易失性存储设备和控制非易失性存储设备的记录区域的奇偶校验表的存储器控制器
公开(公告)号：US08898420B2
公开(公告)日：2014-11-25
申请号：US13464194
申请日：2012-05-04
申请人： Hirokazu So , Toshiyuki Honda
发明人： Hirokazu So , Toshiyuki Honda
IPC分类号： G06F12/00 , G06F11/10
CPC分类号： G06F11/1004 , G06F11/1008
摘要： A non-volatile storage device, which communicates with an access device and carries out reading and/or writing of data in accordance with a command from the access device, the device comprises one or more non-volatile memories for storing data and a memory controller for carrying out control of the non-volatile memory. The memory controller writes data to the error correcting group and writes a provisional error correcting code with respect to the data to the parity table if a data size is smaller than the first size when writing the data.
摘要翻译：一种非易失性存储设备，其与接入设备进行通信并根据来自接入设备的命令执行数据的读取和/或写入，该设备包括用于存储数据的一个或多个非易失性存储器和存储器控制器用于执行非易失性存储器的控制。如果在写入数据时数据大小小于第一大小，则存储器控制器将数据写入纠错组，并将关于数据的临时纠错码写入奇偶校验表。

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