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61. 发明授权

US09147597B2 Method for isolating active regions in germanium-based MOS device 有权
标题翻译：在锗系MOS器件中分离有源区的方法
公开(公告)号：US09147597B2
公开(公告)日：2015-09-29
申请号：US14344050
申请日：2012-06-14
申请人： Ming Li , Min Li , Ru Huang , Xia An , Xing Zhang
发明人： Ming Li , Min Li , Ru Huang , Xia An , Xing Zhang
IPC分类号： H01L21/76 , H01L21/762 , H01L21/763
CPC分类号： H01L21/76232 , H01L21/02052 , H01L21/02236 , H01L21/02255 , H01L21/28255 , H01L21/32 , H01L21/7621 , H01L21/763
摘要： Disclosed herein is a method for isolating active regions in a germanium-based MOS device. A surface of a germanium-based substrate is covered by a thin polysilicon layer or a poly-SiGe layer, and an isolation structure of germanium dioxide covered by a silicon dioxide layer or a SiGe oxide layer on top is formed by means of two steps of oxidation in a case of the active regions are protected. Such two steps of oxidation using the polysilicon layer or the poly-SiGe layer as a sacrificial layer is advantageous to improve the isolation quality of a fabricated germanium dioxide and to reduce a beak effect occurred during a local field oxygen oxidation so as to dramatically elevate the performance of the germanium device.
摘要翻译：本文公开了一种用于隔离锗基MOS器件中的有源区的方法。基于锗的衬底的表面被薄的多晶硅层或多晶硅层覆盖，并且通过两个步骤形成由二氧化硅层或顶部的SiGe氧化物层覆盖的二氧化锗的隔离结构在活性区域的情况下的氧化被保护。使用多晶硅层或多晶硅层作为牺牲层的这两个氧化步骤有利于提高制造的二氧化锗的隔离质量，并且减少在局部场氧氧化期间发生的喙效应，从而显着提升锗器件的性能。

62. 发明授权

US09086448B2 Method for predicting reliable lifetime of SOI mosfet device 有权
标题翻译：用于预测SOI mosfet器件的可靠寿命的方法
公开(公告)号：US09086448B2
公开(公告)日：2015-07-21
申请号：US13504433
申请日：2011-11-30
申请人： Ru Huang , Dong Yang , Xia An , Xing Zhang
发明人： Ru Huang , Dong Yang , Xia An , Xing Zhang
IPC分类号： G01R31/26 , G06F19/00 , G01R31/28
CPC分类号： G01R31/287
摘要： A method for predicting a reliable lifetime of a SOI MOSFET device including: measuring a relationship of a gate resistance of the device varying as a function of a temperature at different wafer temperatures; performing a lifetime accelerating test on the device at different wafer temperatures, so as to obtain a degenerating relationship of a parameter representing the lifetime of the device as a function of stress time, and obtain a lifetime in the presence of self-heating when the parameter degenerates to 10%; performing a self-heating correction on the measured lifetime of the device by using the measured self-heating temperature and an Arrhenius model, so as to obtain a lifetime without self-heating influence; performing a self-heating correction on a variation of the drain current caused by self-heating; performing a self-heating correction on an impact ionization rate caused by hot carriers; and predicting the lifetime of the device under a bias.
摘要翻译：一种用于预测SOI MOSFET器件的可靠寿命的方法，包括：测量在不同晶片温度下作为温度变化的器件的栅极电阻的关系; 在不同的晶片温度下在器件上进行寿命加速测试，以获得表示器件寿命的参数作为应力时间的函数的退化关系，并且当参数为自加热时，在自加热的情况下获得寿命退化为10％; 通过使用测量的自热温度和Arrhenius模型对器件的测量寿命进行自加热校正，以获得没有自热影响的寿命; 对由自加热引起的漏极电流的变化进行自热校正; 对热载体产生的冲击电离率进行自热校正; 并预测设备的使用寿命。

63. 发明申请

US20150031188A1 METHOD FOR ISOLATING ACTIVE REGIONS IN GERMANIUM-BASED MOS DEVICE 有权
标题翻译：用于在基于锗的MOS器件中隔离有源区的方法
公开(公告)号：US20150031188A1
公开(公告)日：2015-01-29
申请号：US14344050
申请日：2012-06-14
申请人： Ming Li , Min Li , Ru Huang , Xia An , Xing Zhang
发明人： Ming Li , Min Li , Ru Huang , Xia An , Xing Zhang
IPC分类号： H01L21/762
CPC分类号： H01L21/76232 , H01L21/02052 , H01L21/02236 , H01L21/02255 , H01L21/28255 , H01L21/32 , H01L21/7621 , H01L21/763
摘要： Disclosed herein is a method for isolating active regions in a germanium-based MOS device. A surface of a germanium-based substrate is covered by a thin polysilicon layer or a poly-SiGe layer, and an isolation structure of germanium dioxide covered by a silicon dioxide layer or a SiGe oxide layer on top is formed by means of two steps of oxidation in a case of the active regions are protected. Such two steps of oxidation using the polysilicon layer or the poly-SiGe layer as a sacrificial layer is advantageous to improve the isolation quality of a fabricated germanium dioxide and to reduce a beak effect occurred during a local field oxygen oxidation so as to dramatically elevate the performance of the germanium device.
摘要翻译：本文公开了一种用于隔离锗基MOS器件中的有源区的方法。基于锗的衬底的表面被薄的多晶硅层或多晶硅层覆盖，并且通过两个步骤形成由二氧化硅层或顶部的SiGe氧化物层覆盖的二氧化锗的隔离结构在活性区域的情况下的氧化被保护。使用多晶硅层或多晶硅层作为牺牲层的这两个氧化步骤有利于提高制造的二氧化锗的隔离质量，并且减少在局部场氧氧化期间发生的喙效应，从而显着提升锗器件的性能。

64. 发明申请

US20130309875A1 INTERFACE TREATMENT METHOD FOR GERMANIUM-BASED DEVICE 有权
标题翻译：用于基于锗的器件的接口处理方法
公开(公告)号：US20130309875A1
公开(公告)日：2013-11-21
申请号：US13702562
申请日：2012-06-14
申请人： Ru Huang , Min Li , Xia An , Ming Li , Meng Lin , Xing Zhang
发明人： Ru Huang , Min Li , Xia An , Ming Li , Meng Lin , Xing Zhang
IPC分类号： H01L21/02
CPC分类号： H01L21/02052 , H01L21/306
摘要： Disclosed herein is an interface treatment method for germanium-based device, which belongs to the field of manufacturing technologies of ultra large scaled integrated (ULSI) circuits. In the method, the natural oxide layer on ther surface of the germanium-based substrate is removed by using a concentrated hydrochloric acid solution having a mass percentage concentration of 15%˜36%, and dangling bonds of the surface are performed a passivation treatment by using a diluted hydrochloric acid solution having a mass percentage concentration of 5%˜10% so as to form a stable passivation layer on the surface. This method makes a good foundation for depositing a high-K (high dielectric constant) gate dielectric on the surface of the germanium-based substrate after cleaning and passivating, enhances quality of the interface between the gate dielectric and the substrate, and improves the electrical performance of germanium-based MOS device.
摘要翻译：本文公开了一种锗系器件的接口处理方法，属于超大规模集成（ULSI）电路制造技术领域。在该方法中，通过使用质量百分比浓度为15％〜36％的浓盐酸溶液除去锗基底板的表面上的天然氧化物层，并且通过以下方式进行钝化处理：使用质量百分比浓度为5％〜10％的稀盐酸溶液，以在表面上形成稳定的钝化层。该方法为清洗和钝化后在锗基基板表面上沉积高K（高介电常数）栅极电介质提供了良好的基础，提高了栅极电介质和基板之间界面的质量，改善了电气锗系MOS器件的性能。

65. 发明授权

US08541847B2 Semiconductor device and method for fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08541847B2
公开(公告)日：2013-09-24
申请号：US13201618
申请日：2010-09-25
申请人： Xia An , Yue Guo , Quanxin Yun , Ru Huang , Xing Zhang
发明人： Xia An , Yue Guo , Quanxin Yun , Ru Huang , Xing Zhang
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L29/16 , H01L29/6659 , H01L29/7833 , H01L29/7848
摘要： The present invention provides a semiconductor device and a method for fabricating the same, wherein the method comprises: providing a germanium-based semiconductor substrate having a plurality of active regions and device isolation regions between the plurality of the active regions, wherein a gate dielectric layer and a gate over the gate dielectric layer are provided on the active regions, and the active regions include source and drain extension regions and deep source and drain regions; performing a first ion implantation process with respect to the source and drain extension regions, wherein the ions implanted in the first ion implantation process include silicon or carbon; performing a second ion implantation process with respect to the source and drain extension regions; performing a third ion implantation process with respect to the deep source and drain regions; performing an annealing process with respect to the germanium-based semiconductor substrate which has been subjected to the third ion implantation process. According to the method for fabricating a semiconductor device, through the implantation of silicon impurities, appropriate stress may be introduced into the germanium channel effectively by the mismatch of lattices in the source and drain regions, so that the mobility of electrons in the channel is enhanced and the performance of the device is improved.
摘要翻译：本发明提供一种半导体器件及其制造方法，其中该方法包括：在多个有源区之间提供具有多个有源区和器件隔离区的锗基半导体衬底，其中栅介电层并且栅极电介质层上的栅极设置在有源区上，有源区包括源极和漏极延伸区以及深的源极和漏极区; 对源极和漏极延伸区域执行第一离子注入工艺，其中在第一离子注入工艺中注入的离子包括硅或碳; 对源极和漏极延伸区域执行第二离子注入工艺; 相对于深源极和漏极区域执行第三离子注入工艺; 对已进行第三离子注入工艺的锗基半导体衬底进行退火处理。根据制造半导体器件的方法，通过硅杂质的注入，可以通过源极和漏极区域中的晶格失配有效地将合适的应力引入锗通道中，使得通道中电子的迁移率增强并提高了设备的性能。

66. 发明申请

US20130214810A1 METHOD FOR TESTING DENSITY AND LOCATION OF GATE DIELECTRIC LAYER TRAP OF SEMICONDUCTOR DEVICE 有权
标题翻译：测试半导体器件栅极电介质层的密度和位置的方法
公开(公告)号：US20130214810A1
公开(公告)日：2013-08-22
申请号：US13879967
申请日：2012-02-28
申请人： Ru Huang , Jibin Zou , Changze Liu , Runsheng Wang , Jiewen Fan , Yangyuan Wang
发明人： Ru Huang , Jibin Zou , Changze Liu , Runsheng Wang , Jiewen Fan , Yangyuan Wang
IPC分类号： G01R31/26
CPC分类号： G01R31/2642 , G01R31/2621 , H01L22/14 , H01L22/34
摘要： Proposed is a method for testing the density and location of a gate dielectric layer trap of a semiconductor device. The testing method tests the trap density and two-dimensional trap location in the gate dielectric layer of a semiconductor device with a small area (the effective channel area is less than 0.5 square microns) using the gate leakage current generated by a leakage path. The present invention is especially suitable for testing a device with an ultra-small area (the effective channel area is less than 0.05 square microns). The present method can obtain trap distribution scenarios of the gate dielectric layer in the case of different materials and different processes. In the present method, the device requirements are simple, the testing structure is simple, the testing cost is low, the testing is rapid and the trap distribution of the gate dielectric layer of the device can be obtained within a short time, which is suitable for large batches of automatic testing and is especially suitable for process monitoring and finished product quality detection during the manufacture of ultra-small semiconductor devices.
摘要翻译：提出了一种用于测试半导体器件的栅介质层陷阱的密度和位置的方法。测试方法使用由泄漏路径产生的栅极泄漏电流来测试具有小面积（有效沟道面积小于0.5平方微米）的半导体器件的栅极介电层中的阱密度和二维陷阱位置。本发明特别适用于测试具有超小面积（有效通道面积小于0.05平方微米）的器件。在不同材料和不同工艺的情况下，本方法可以获得栅极电介质层的陷阱分布情况。在本方法中，器件要求简单，测试结构简单，测试成本低，测试快速，可在短时间内获得器件栅极电介质层的陷阱分布，适合用于大批量的自动测试，特别适用于超小型半导体器件制造过程中的过程监控和成品质量检测。

67. 发明申请

US20130168759A1 FIELD EFFECT TRANSISTOR WITH A VERTICAL CHANNEL AND FABRICATION METHOD THEREOF 有权
标题翻译：具有垂直通道的场效应晶体管及其制造方法
公开(公告)号：US20130168759A1
公开(公告)日：2013-07-04
申请号：US13821944
申请日：2011-09-09
申请人： Ru Huang , Yujie Ai , Zhihua Hao , Shuangshuang Pu , Jiewen Fan , Shuai Sun , Runsheng Wang , Xiaoyan Xu
发明人： Ru Huang , Yujie Ai , Zhihua Hao , Shuangshuang Pu , Jiewen Fan , Shuai Sun , Runsheng Wang , Xiaoyan Xu
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7827 , B82Y10/00 , H01L21/2815 , H01L29/04 , H01L29/0653 , H01L29/0657 , H01L29/0676 , H01L29/0692 , H01L29/0847 , H01L29/413 , H01L29/42376 , H01L29/66439 , H01L29/66666 , H01L29/775
摘要： Disclosed herein is a field effect transistor with a vertical channel and a fabrication method thereof. A channel region of the field effect transistor is a circular ring-shaped Si platform, which is formed over a substrate and perpendicular to the substrate; a source, which is made of polysilicon, is located at an upper end of the Si platform; a drain is disposed at an outside of a lower end of the circular ring-shaped Si platform; a gate is placed on an outer side surface of the circular ring-shaped Si platform; and an inside of the circular ring-shaped Si platform is filled with a dielectric material. In comparison with the conventional vertical structure MOSFET with a Si platform, the circular ring-shaped structure field effect transistor according to the invention can effectively suppress the short channel effect and improve the device performance.
摘要翻译：本文公开了具有垂直沟道的场效应晶体管及其制造方法。场效应晶体管的沟道区域是形成在衬底上并垂直于衬底的圆形环形Si平台; 由多晶硅制成的源头位于Si平台的上端; 在圆环状Si平台的下端的外侧配置有排水口，在圆环状Si平台的外侧面上设置有闸门; 并且圆形环形Si平台的内部填充有电介质材料。与传统的具有Si平台的垂直结构MOSFET相比，根据本发明的圆环形结构场效应晶体管可以有效地抑制短沟道效应并提高器件性能。

68. 发明申请

US20130011980A1 FABRICATION METHOD OF VERTICAL SILICON NANOWIRE FIELD EFFECT TRANSISTOR 有权
标题翻译：垂直硅纳米管场效应晶体管的制造方法
公开(公告)号：US20130011980A1
公开(公告)日：2013-01-10
申请号：US13501711
申请日：2011-11-18
申请人： Ru Huang , Jiewen Fan , Yujie Ai , Shuai Sun , Runsheng Wang , Jibin Zou , Xin Huang
发明人： Ru Huang , Jiewen Fan , Yujie Ai , Shuai Sun , Runsheng Wang , Jibin Zou , Xin Huang
IPC分类号： H01L21/336 , B82Y40/00
CPC分类号： H01L29/0676 , B82Y10/00 , B82Y40/00 , H01L29/66439 , H01L29/775
摘要： The present invention discloses a fabrication method of a vertical silicon nanowire field effect transistor having a low parasitic resistance, which relates to a field of an ultra-large-integrated-circuit fabrication technology. As compared with a conventional planar field effect transistor, on one hand the vertical silicon nanowire field effect transistor fabricated by the present invention can provide a good ability for suppressing a short channel effect due to the excellent gate control ability caused by the one-dimensional structure, and reduce a leakage current and a drain-induced barrier lowering (DIBL). On the other hand, an area of the transistor is further reduced and an integration degree of an IC system is increased.
摘要翻译：本发明公开了一种具有低寄生电阻的垂直硅纳米线场效应晶体管的制造方法，其涉及超大集成电路制造技术的领域。与传统的平面场效应晶体管相比，一方面，本发明制造的垂直硅纳米线场效应晶体管可以提供良好的抑制由于一维结构引起的栅极控制能力的短通道效应的能力，并减少泄漏电流和漏极引起的屏障降低（DIBL）。另一方面，晶体管的面积进一步减小，并且IC系统的集成度增加。

69. 发明申请

US20130001655A1 Heat Dissipation Structure of SOI Field Effect Transistor 有权
标题翻译： SOI场效应晶体管的散热结构
公开(公告)号：US20130001655A1
公开(公告)日：2013-01-03
申请号：US13582624
申请日：2011-08-17
申请人： Ru Huang , Xin Huang , Shoubin Xue , Yujie Ai
发明人： Ru Huang , Xin Huang , Shoubin Xue , Yujie Ai
IPC分类号： H01L23/38 , H01L29/80
CPC分类号： H01L23/38 , H01L27/16 , H01L2924/0002 , H01L2924/00
摘要： The present invention discloses a heat dissipation structure for a SOI field effect transistor having a schottky source/drain, which relates to a field of microelectronics. The heat dissipation structure includes two holes connected with a drain terminal or with both a source terminal and a drain terminal, which are filled with an N-type material with high thermoelectric coefficient and a P-type material with high thermoelectric coefficient respectively. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a high potential with respect to the drain terminal, and a metal wire for the P-type material with high thermoelectric coefficient in the vicinity of the drain terminal is applied a low potential with respect to the drain terminal. A metal wire for the N-type material with high thermoelectric coefficient in the vicinity of the source terminal is applied a high potential with respect to the source terminal, and a metal wire for the P-type material in the vicinity of the source terminal is applied a lower potential with respect to the source terminal. By way of a Peltier effect, in the present invention heat can be absorbed at a contact portion between the thermoelectric material and the source/drain, and at the same time dissipated at a connection portion between the thermoelectric material and a bottom electrode metal, so that the heat generated in an active region of the device is effectively transferred to the substrate and dissipated through a heat sink.
摘要翻译：本发明公开了一种具有肖特基源极/漏极的SOI场效应晶体管的散热结构，涉及微电子领域。散热结构包括与漏极端子或者源极端子和漏极端子连接的两个孔，其分别填充有高热电系数的N型材料和具有高热电系数的P型材料。在漏极端子附近，用于具有高热电系数的N型材料的金属线相对于漏极端子施加高电位，并且用于具有高热电系数的P型材料的金属线漏极端子相对于漏极端子施加低电位。在源极端子附近具有高热电系数的N型材料的金属线相对于源极端子施加高电位，并且在源极端子附近的用于P型材料的金属线是相对于源极端子施加较低的电位。通过珀耳帖效应，在本发明中，热量可以在热电材料和源极/漏极之间的接触部分处被吸收，并且同时在热电材料和底部电极金属之间的连接部分消散，因此在器件的有源区域中产生的热量有效地传递到衬底并通过散热器散发。

70. 发明申请

US20120289004A1 FABRICATION METHOD OF GERMANIUM-BASED N-TYPE SCHOTTKY FIELD EFFECT TRANSISTOR 审中-公开
标题翻译：基于锗的N型肖特基效应晶体管的制造方法
公开(公告)号：US20120289004A1
公开(公告)日：2012-11-15
申请号：US13390755
申请日：2011-10-14
申请人： Ru Huang , Zhiqiang Li , Yue Guo , Xia An , Quanxin Yun , Yinglong Huang , Xing Zhang
发明人： Ru Huang , Zhiqiang Li , Yue Guo , Xia An , Quanxin Yun , Yinglong Huang , Xing Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/0895 , H01L29/41783 , H01L29/517 , H01L29/66643 , H01L29/78
摘要： The present invention discloses a fabrication method of a Ge-based N-type Schottky field effect transistor and relates to a filed of ultra-large-scaled integrated circuit fabrication process. The present invention forms a thin high K dielectric layer between a substrate and a metal source/drain. The thin layer on one hand may block the electron wave function of metal from inducing an MIGS interface state in the semiconductor forbidden band, on the other hand may passivate the dangling bonds at the interface of Ge. Meanwhile, since the insulating dielectric layer has a very thin thickness, and electrons can substantially pass freely, the parasitic resistances of the source and the drain are not significantly increased. The method can weaken the Fermi level pinning effect, cause the Fermi energy level close to the position of the conduction band of Ge and lower the electron barrier, thereby increasing the current switching ratio of the Ge-based Schottky transistor and improve the performance of the NMOS device.
摘要翻译：本发明公开了一种Ge系N型肖特基场效应晶体管的制造方法，涉及超大规模集成电路制造工艺。本发明在衬底和金属源极/漏极之间形成薄的高K电介质层。薄层一方面可能阻止金属的电子波函数在半导体禁带中引起MIGS界面态，另一方面可能会钝化Ge界面处的悬挂键。同时，由于绝缘介电层具有非常薄的厚度，并且电子可以基本上自由地通过，所以源极和漏极的寄生电阻不会显着增加。该方法可以削弱费米能级钉扎效应，使费米能级接近Ge导带的位置，降低电子势垒，从而提高Ge基肖特基晶体管的电流开关比，提高Ge NMOS器件。

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