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61. 发明申请

US20090086521A1 MULTIPLE ANTIFUSE MEMORY CELLS AND METHODS TO FORM, PROGRAM, AND SENSE THE SAME 审中-公开
标题翻译：多种抗体存储细胞及其形成，程序和感觉的方法
公开(公告)号：US20090086521A1
公开(公告)日：2009-04-02
申请号：US11864870
申请日：2007-09-28
申请人： S. Brad Herner , Roy E. Scheuerlein , Christopher J. Petti
发明人： S. Brad Herner , Roy E. Scheuerlein , Christopher J. Petti
IPC分类号： G11C5/06 , G11C17/06 , H01L21/44 , H01L29/00 , G11C17/18
CPC分类号： G11C17/16 , G11C11/5685 , G11C11/5692 , G11C13/0007 , G11C17/06 , G11C17/146 , G11C17/165 , G11C2213/32 , G11C2213/72 , H01L27/101 , H01L27/1021
摘要： Methods are described to fabricate, program, and sense a multilevel one-time-programmable memory cell including a steering element such as a diode and two, three, or more dielectric antifuses in series. The antifuses may be of different thicknesses, or may be formed of dielectric materials having different dielectric constants, or both. The antifuses and programming pulses are selected such that when the cell is programmed, the largest voltage drop in the memory cell is across only one of the antifuses, while the other antifuses allow some leakage current. In some embodiments, the antifuse with the largest voltage drop breaks down, while the other antifuses remain intact. In this way, the antifuses can be broken down individually, so a memory cell having two, three, or more antifuses may achieve any of three, four, or more unique data states.
摘要翻译：描述了制造，编程和感测多级一次可编程存储器单元的方法，所述存储单元包括诸如二极管的导向元件和串联的两个，三个或更多个介质反熔丝。反熔丝可以具有不同的厚度，或者可以由具有不同介电常数的介电材料或两者形成。选择反熔丝和编程脉冲，使得当单元被编程时，存储单元中的最大电压降仅跨越反熔丝中的一个，而另一个反熔丝允许一些漏电流。在一些实施例中，具有最大电压降的反熔丝分解，而其它反熔丝保持完整。以这种方式，可以单独地分解反熔丝，因此具有两个，三个或更多个反熔丝的存储单元可以实现三个，四个或更多个唯一数据状态中的任何一个。

62. 发明授权

US07499366B2 Method for using dual data-dependent busses for coupling read/write circuits to a memory array 有权
标题翻译：使用双数据相关总线将读/写电路耦合到存储器阵列的方法
公开(公告)号：US07499366B2
公开(公告)日：2009-03-03
申请号：US11461369
申请日：2006-07-31
申请人： Roy E. Scheuerlein , Luca G. Fasoli
发明人： Roy E. Scheuerlein , Luca G. Fasoli
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C7/1048 , G11C7/18 , G11C8/08 , G11C8/14 , Y10T29/49002
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

63. 发明授权

US07495500B2 Method for using a multiple polarity reversible charge pump circuit 有权
标题翻译：使用多极性可逆电荷泵电路的方法
公开(公告)号：US07495500B2
公开(公告)日：2009-02-24
申请号：US11618838
申请日：2006-12-31
申请人： Ali K. Al-Shamma , Roy E. Scheuerlein
发明人： Ali K. Al-Shamma , Roy E. Scheuerlein
IPC分类号： G05F1/10
CPC分类号： H02M3/073 , H02M2003/071 , H02M2003/077
摘要： A multiple polarity reversible charge pump circuit is disclosed which, in certain embodiments, may be configured to generate a positive voltage at times and may be reversed to generate a negative voltage at other times. Such a charge pump circuit is advantageous if both the positive and negative voltage are not simultaneously required. In certain other embodiments, a charge pump circuit generates a high output current for only a positive boosted voltage in one mode of operation, but lower current positive and negative boosted voltage outputs in another mode of operation. Use with certain erasable memory array technologies is disclosed, particularly certain resistive passive element memory cells, and more particularly in a three-dimensional memory array.
摘要翻译：公开了一种多极性可逆电荷泵电路，其在某些实施例中可被配置为有时产生正电压并且可以反向以在其它时间产生负电压。如果不同时需要正电压和负电压，则这种电荷泵电路是有利的。在某些其他实施例中，电荷泵电路仅在一种工作模式下产生仅仅正升压电压的高输出电流，而在另一种工作模式下产生较低电流正和负升压电压输出。公开了某些可擦除存储器阵列技术的使用，特别是某些电阻性无源元件存储单元，更具体地在三维存储器阵列中使用。

64. 发明申请

US20080310231A1 OPTIMIZATION OF CRITICAL DIMENSIONS AND PITCH OF PATTERNED FEATURES IN AND ABOVE A SUBSTRATE 有权
标题翻译：关键尺寸的优化和基板上及以上图案特征的优化
公开(公告)号：US20080310231A1
公开(公告)日：2008-12-18
申请号：US12136766
申请日：2008-06-10
申请人： James M. Cleeves , Roy E. Scheuerlein
发明人： James M. Cleeves , Roy E. Scheuerlein
IPC分类号： G11C11/34 , H01L27/092
CPC分类号： H01L27/105 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.
摘要翻译：在使用光刻和蚀刻技术的不同器件级别和那些器件级别的区域中，使用不同且优化的临界尺寸形成管芯。本发明的一个方面提供了形成在衬底上的存储器阵列，其中驱动电路形成在衬底中。存储器阵列的一个级别包括例如平行轨道和扇出区域。希望使轨道的密度最大化并最小化整个存储器阵列的光刻成本。这可以通过以比它下面的CMOS电路更紧的间距形成轨道来实现，从而允许在形成CMOS时使用更便宜的光刻工具，并且类似地通过优化用于器件级别的光刻和蚀刻技术以在轨道，并且在不太关键的扇出区域更放松。

65. 发明授权

US07463546B2 Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders 有权
标题翻译：使用包含可逆极性字线和位线解码器的无源元件存储器阵列的方法
公开(公告)号：US07463546B2
公开(公告)日：2008-12-09
申请号：US11461364
申请日：2006-07-31
申请人： Luca G. Fasoli , Christopher J. Petti , Roy E. Scheuerlein
发明人： Luca G. Fasoli , Christopher J. Petti , Roy E. Scheuerlein
IPC分类号： G11C8/00
CPC分类号： G11C17/18 , G11C8/08 , G11C8/10 , G11C17/16 , G11C17/165
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

66. 发明授权

US07423304B2 Optimization of critical dimensions and pitch of patterned features in and above a substrate 有权
标题翻译：优化衬底中和图案上的图案特征的临界尺寸和间距
公开(公告)号：US07423304B2
公开(公告)日：2008-09-09
申请号：US10728437
申请日：2003-12-05
申请人： James M. Cleeves , Roy E. Scheuerlein
发明人： James M. Cleeves , Roy E. Scheuerlein
IPC分类号： H01L29/80 , H01L31/112
CPC分类号： H01L27/105 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A die is formed with different and optimized critical dimensions in different device levels and areas of those device levels using photolithography and etch techniques. One aspect of the invention provides for a memory array formed above a substrate, with driver circuitry formed in the substrate. A level of the memory array consists of, for example, parallel rails and a fan-out region. It is desirable to maximize density of the rails and minimize cost of lithography for the entire memory array. This can be achieved by forming the rails at a tighter pitch than the CMOS circuitry beneath it, allowing cheaper lithography tools to be used when forming the CMOS, and similarly by optimizing lithography and etch techniques for a device level to produce a tight pitch in the rails, and a more relaxed pitch in the less-critical fan-out region.
摘要翻译：在使用光刻和蚀刻技术的不同器件级别和那些器件级别的区域中，使用不同且优化的临界尺寸形成管芯。本发明的一个方面提供了形成在衬底上的存储器阵列，其中驱动电路形成在衬底中。存储器阵列的一个级别包括例如平行轨道和扇出区域。希望使轨道的密度最大化并最小化整个存储器阵列的光刻成本。这可以通过以比它下面的CMOS电路更紧的间距形成轨道来实现，从而允许在形成CMOS时使用更便宜的光刻工具，并且类似地通过优化用于器件级别的光刻和蚀刻技术来产生紧密的间距轨道，并且在不太关键的扇出区域更放松。

67. 发明授权

US07362604B2 Apparatus and method for programming an array of nonvolatile memory cells including switchable resistor memory elements 有权
标题翻译：用于编程包括可切换电阻存储元件的非易失性存储单元阵列的装置和方法
公开(公告)号：US07362604B2
公开(公告)日：2008-04-22
申请号：US11179077
申请日：2005-07-11
申请人： Roy E. Scheuerlein
发明人： Roy E. Scheuerlein
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C11/5614 , G11C13/0069 , G11C2013/009 , G11C2213/71 , G11C2213/79
摘要： A non-volatile memory cell includes a switchable resistor memory element in series with a switch device. An array of such cells may be programmed using only positive voltages. A method for programming such cells also supports a direct write of both 0 and 1 data states without requirement of a block erase operation, and is scalable for use with relatively low voltage power supplies. A method for reading such cells reduces read disturb of a selected memory cell by impressing a read bias voltage having a polarity opposite that of a set voltage employed to change the switchable resistor memory element to a low resistance state. Such programming and read methods are well suited for use in a three-dimensional memory array formed on multiple levels above a substrate, particularly those having extremely compact array line drivers on very tight layout pitch.
摘要翻译：非易失性存储单元包括与开关装置串联的可切换电阻存储元件。可以仅使用正电压来编程这样的单元阵列。用于编程这样的单元的方法还支持0和1数据状态的直接写入，而不需要块擦除操作，并且可扩展以用于相对低电压的电源。用于读取这种单元的方法通过将具有极性与用于将可切换电阻器存储元件改变为低电阻状态的设定电压的极性相反的读取偏置电压来减小所选存储单元的读取干扰。这种编程和读取方法非常适用于形成在衬底上的多个层上的三维存储器阵列，特别是在非常紧凑的布局间距上具有非常紧凑的阵列线驱动器的那些。

68. 发明申请

US20080025134A1 METHOD FOR USING TWO DATA BUSSES FOR MEMORY ARRAY BLOCK SELECTION 有权
标题翻译：使用两个数据总线进行存储器阵列选择的方法
公开(公告)号：US20080025134A1
公开(公告)日：2008-01-31
申请号：US11461372
申请日：2006-07-31
申请人： Roy E. Scheuerlein , Luca G. Fasoli , Christopher J. Petti
发明人： Roy E. Scheuerlein , Luca G. Fasoli , Christopher J. Petti
IPC分类号： G11C11/00 , G11C7/10 , G11C8/00
CPC分类号： G11C8/14 , G11C7/1048 , G11C7/18 , G11C8/08 , G11C8/12
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

69. 发明申请

US20080025089A1 METHOD FOR READING A MULTI-LEVEL PASSIVE ELEMENT MEMORY CELL ARRAY 有权
标题翻译：读取多级被动元件存储单元阵列的方法
公开(公告)号：US20080025089A1
公开(公告)日：2008-01-31
申请号：US11461367
申请日：2006-07-31
申请人： Roy E. Scheuerlein , Tyler J. Thorp , Luca G. Fasoli
发明人： Roy E. Scheuerlein , Tyler J. Thorp , Luca G. Fasoli
IPC分类号： G11C16/04
CPC分类号： G11C17/16 , G11C11/565 , G11C11/5685 , G11C11/5692 , G11C13/0007 , G11C13/004 , G11C17/18 , G11C2013/0054 , G11C2211/5631 , G11C2211/5634 , G11C2213/32 , G11C2213/72
摘要： A four level passive element cell has memory states corresponding to decreasing resistance levels, which are preferably mapped respectively to data states 11, 01, 00, and 10. The LSB and MSB are preferably mapped as part of different pages. To discriminate between memory cell states, the selected bit line current is sensed for at least two different combinations of reference current level and read bias voltage. A mid-level reference is used to read the LSB. When reading the MSB, a first reference between the 10 and 00 data states, and a second reference between 01 and 11 data states may be used, and the mid-level reference need not be used. In certain embodiments, the bit line current may be simultaneously compared against the first and second references, without requiring a delay to stabilize the bit line current to a different value, and the MSB generated accordingly.
摘要翻译：四级无源元件单元具有对应于降低电阻电平的存储器状态，其优选分别映射到数据状态11,01,00和10. LSB和MSB优选地被映射为不同页面的一部分。为了区分存储单元状态，对于参考电流电平和读取偏置电压的至少两种不同的组合来检测所选择的位线电流。中间级参考用于读取LSB。当读取MSB时，可以使用10和00数据状态之间的第一个参考，并且可以使用01和11数据状态之间的第二个参考，并且不需要使用中间级参考。在某些实施例中，位线电流可以同时与第一和第二参考值进行比较，而不需要延迟来将位线电流稳定到不同的值，并且相应地生成MSB。

70. 发明申请

US20080025078A1 SYSTEMS FOR REVERSE BIAS TRIM OPERATIONS IN NON-VOLATILE MEMORY 有权
标题翻译：用于在非易失性存储器中反向偏移操作的系统
公开(公告)号：US20080025078A1
公开(公告)日：2008-01-31
申请号：US11461431
申请日：2006-07-31
申请人： Roy E. Scheuerlein , Tanmay Kumar
发明人： Roy E. Scheuerlein , Tanmay Kumar
IPC分类号： G11C11/00
CPC分类号： G11C8/08 , G11C5/02 , G11C11/56 , G11C13/0023 , G11C13/0028 , G11C13/0038 , G11C13/0069 , G11C13/0097 , G11C17/16 , G11C17/18 , G11C2213/71 , G11C2213/72
摘要： A reverse bias trim operation for the reset state of a non-volatile memory system is disclosed. Non-volatile memory cells including a resistance change element undergo a reverse bias reset operation to change their resistance from a set state at a first level of resistance to a reset state at a second level of resistance. Certain memory cells in a set of cells that was reset may be deeply reset to a level of resistance beyond a target level for the reset state. A second reverse bias is applied to the set of memory cells to move the resistance of each cell that was deeply reset toward the target level of the reset state. A smaller reverse bias than used for the reset operation can shift the resistance of the cells back toward the set level and out of their deeply reset condition. The operation is self-limiting in that cells stop their resistance shifts upon reaching the target level. Cells that were not deeply reset are not affected.
摘要翻译：公开了一种用于非易失性存储器系统的复位状态的反偏压调整操作。包括电阻变化元件的非易失性存储单元经历反向偏置复位操作，以在第二电阻电平处的第一电阻电平将其电阻从设定状态改变为复位状态。复位的一组单元格中的某些存储单元可能被重新设置为超出复位状态的目标电平的电阻水平。第二反向偏压被施加到存储器单元组，以将每个单元的电阻移动到复位状态的目标电平。与用于复位操作相比较小的反向偏压可以将电池的电阻转移回设定电平并脱离它们的深度复位状态。操作是自限制的，因为细胞在达到目标水平时停止其阻力位移。未重新设置的单元格不受影响。

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