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61. 发明授权

US07813077B2 Apparatus, system, and method for detecting a periodic sequence of servo signals 有权
标题翻译：用于检测伺服信号的周期性序列的装置，系统和方法
公开(公告)号：US07813077B2
公开(公告)日：2010-10-12
申请号：US11469133
申请日：2006-08-31
申请人： Nhan Xuan Bui , Roy Daron Cideciyan , Robert Allen Hutchins , Thomas Mittelholzer , Kazuhiro Tsuruta
发明人： Nhan Xuan Bui , Roy Daron Cideciyan , Robert Allen Hutchins , Thomas Mittelholzer , Kazuhiro Tsuruta
IPC分类号： G11B5/596
CPC分类号： G11B20/1407 , G11B5/584 , G11B20/1492 , G11B2020/1284 , G11B2020/1484 , G11B2220/90
摘要： An apparatus, system, and method are disclosed for detecting a periodic sequence. A value detector module detects a plurality of values of a periodic sequence. In one embodiment, a transformation module transforms the plurality of values into transformed values. A confinement module confines the values to a limited set of confined values. A correlation module correlates the confined values with a plurality of instances of the periodic sequence. In addition, a selection module selects an instance of the periodic sequence with the highest correlation to the confined values as an observed periodic sequence.
摘要翻译：公开了用于检测周期性序列的装置，系统和方法。值检测器模块检测周期性序列的多个值。在一个实施例中，变换模块将多个值转换为变换值。限制模块将值限制为有限的一组限制值。相关模块将约束值与周期性序列的多个实例相关联。此外，选择模块选择具有与限定值的最高相关性的周期性序列的实例作为观察到的周期性序列。

62. 发明申请

US20100232047A1 DATA INTERLEAVING IN TAPE DRIVES 有权
标题翻译：磁带驱动器中的数据交互
公开(公告)号：US20100232047A1
公开(公告)日：2010-09-16
申请号：US12720711
申请日：2010-03-10
申请人： Giovanni Cherubini , Roy Daron Cideciyan , Evangelos S. Eleftheriou , Thomas Mittelholzer
发明人： Giovanni Cherubini , Roy Daron Cideciyan , Evangelos S. Eleftheriou , Thomas Mittelholzer
IPC分类号： G11B5/09 , G06F13/28
CPC分类号： G11B20/1202 , G11B20/1833 , G11B20/1866 , G11B2020/1836 , G11B2020/1853 , G11B2220/93
摘要： Methods and apparatus for interleaving data in a multitrack tape drive and for writing data on a multitrack tape in the tape drive. One method includes: partitioning the data into m(2n+k) data blocks, where each data block has a logical array of rows and columns of data bytes; error-correction coding a row and a column of the logical array to produce an encoded block; assigning the coded row to a respective location in a logical interleave array having L rows and 2n+k columns of locations; and writing a sequence of assigned coded rows simultaneously in respective data tracks on the multitrack tape. The coded row is assigned such that the minimum Euclidean distance on the multitrack tape between the coded rows is maximized. The apparatus includes units for performing the methods and the computer program product includes a program code means for causing a computer to perform the methods.
摘要翻译：用于在多轨磁带驱动器中交织数据并在磁带驱动器中的多轨磁带上写入数据的方法和装置。一种方法包括：将数据划分为m（2n + k）个数据块，其中每个数据块具有数据字节的行和列的逻辑阵列; 对逻辑阵列的行和列进行纠错编码以产生编码块; 将编码行分配给具有L行和2n + k列位置的逻辑交错阵列中的相应位置; 以及在多轨磁带上的相应数据轨道中同时写入分配的编码行序列。分配编码行使得编码行之间的多轨磁带上的最小欧几里得距离最大化。所述装置包括用于执行所述方法的单元，并且所述计算机程序产品包括用于使计算机执行所述方法的程序代码装置。

63. 发明申请

US20100214829A1 MEMORY PROGRAMMING 有权
标题翻译：内存编程
公开(公告)号：US20100214829A1
公开(公告)日：2010-08-26
申请号：US12391693
申请日：2009-02-24
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C11/00
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译：提供了用于向内存位置迭代地写入内容的系统，方法和设备。统计模型用于确定将所需内容写入存储器位置的脉冲序列。内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。统计模型和查询表可用于选择和修改脉冲。自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

64. 发明授权

US08839076B2 Encoding a data word for writing the encoded data word in a multi-level solid state memory 有权
标题翻译：编码用于将编码数据字写入多级固态存储器的数据字
公开(公告)号：US08839076B2
公开(公告)日：2014-09-16
申请号：US13418423
申请日：2012-03-13
申请人： Thomas Mittelholzer , Nikolaos Papandreou , Charalampos Pozidis
发明人： Thomas Mittelholzer , Nikolaos Papandreou , Charalampos Pozidis
IPC分类号： G11C29/00 , H03M13/25 , H03M13/29 , H03M13/31 , H03M13/35 , G06F11/10 , H03M13/15 , H03M13/19
CPC分类号： H03M13/251 , G06F11/1072 , G11C11/5678 , G11C29/00 , G11C29/70 , G11C2211/5641 , H03M13/1515 , H03M13/19 , H03M13/253 , H03M13/2906 , H03M13/31 , H03M13/353
摘要： A method for encoding a data word for writing an encoded data word in N cells of a solid state memory. Each of the N cells can be programmed in one of q nominal levels. The method includes encoding the data word as a codeword of a first codeword type having q symbol values or as a codeword of a second codeword type having (q-d) symbol values, d ε [1, . . . , q−1], depending on a state of the N cells.
摘要翻译：一种编码用于在固态存储器的N个单元中写入编码数据字的数据字的方法。 N个单元中的每一个可以以q个标称电平中的一个编程。该方法包括将数据字编码为具有q个符号值的第一码字类型的码字或具有（q-d）符号值的第二码字类型的码字，d' [1，。。。，q-1]，取决于N细胞的状态。

65. 发明授权

US08743499B2 Adaptive soft-output detector for magnetic tape read channels 失效
标题翻译：用于磁带读取通道的自适应软输出检测器
公开(公告)号：US08743499B2
公开(公告)日：2014-06-03
申请号：US13527490
申请日：2012-06-19
申请人： Katherine T. Blinick , Robert A. Hutchins , Thomas Mittelholzer , Sedat Oelcer
发明人： Katherine T. Blinick , Robert A. Hutchins , Thomas Mittelholzer , Sedat Oelcer
IPC分类号： G11B5/035 , G11B20/10
CPC分类号： G11B5/00817 , G11B5/09 , G11B20/10046 , G11B20/10074 , G11B20/10287 , G11B2220/90
摘要： In one embodiment, a system includes a tape channel for reading data from a magnetic tape medium to produce a signal, a bank of noise whitening filters positioned subsequent to the tape channel adapted for receiving the signal, the bank of noise whitening filters being adapted for minimizing variance of noise affecting the signal at an output of the bank of noise whitening filters, wherein each noise whitening filter in the bank of noise whitening filters is dependent on a different possible data pattern, a soft DMAX detector adapted for calculating first soft information, dependent on the different possible data patterns, about each bit of the signal from the bank of noise whitening filters, and sending the first soft information to a soft decoder adapted for calculating second soft information about each bit of the signal and sending the second soft information to the soft DMAX detector.
摘要翻译：在一个实施例中，系统包括用于从磁带介质读取数据以产生信号的带通道，位于适于接收信号的磁带通道之后的一组噪声白化滤波器，噪声增白滤波器组适于最小化影响噪声白化滤波器组的输出处的信号的噪声的方差，其中噪声白化滤波器组中的每个噪声白化滤波器取决于不同的可能数据模式，适于计算第一软信息的软DMAX检测器，取决于不同的可能数据模式，关于噪声白化滤波器组的信号的每个位，并且将第一软信息发送到软解码器，该软解码器适于计算关于信号的每个位的第二软信息，并且发送第二软信息到软DMAX检测器。

66. 发明授权

US08405925B2 Track-dependent data randomization mitigating false VFO detection 有权
标题翻译：跟踪依赖的数据随机化减轻虚假的VFO检测
公开(公告)号：US08405925B2
公开(公告)日：2013-03-26
申请号：US13149905
申请日：2011-06-01
申请人： Roy Daron Cideciyan , Thomas Mittelholzer , Paul J. Seger , Keisuke Tanaka
发明人： Roy Daron Cideciyan , Thomas Mittelholzer , Paul J. Seger , Keisuke Tanaka
IPC分类号： G11B5/09
CPC分类号： G11B5/0083 , G11B5/09 , G11B20/10009 , G11B20/10222 , G11B20/10259 , G11B20/1833 , G11B2220/956 , H03M13/09 , H03M13/27 , H03M13/2909 , H03M13/2945 , H03M13/6561 , H04L1/0042
摘要： A method for randomizing data to mitigate false VFO detection is described. In one embodiment, such a method includes simultaneously receiving multiple input data streams. Each input data stream is associated with a different track on a magnetic tape medium. The input data streams are simultaneously scrambled to produce multiple randomized data streams. The input data streams are scrambled such that different bit patterns are produced in the randomized data streams even where corresponding bit patterns in the input data streams are identical. The randomized data streams are simultaneously written to their associated data tracks on the magnetic tape medium. A corresponding apparatus is also described.
摘要翻译：描述用于随机化数据以减轻虚假VFO检测的方法。在一个实施例中，这种方法包括同时接收多个输入数据流。每个输入数据流与磁带介质上的不同轨道相关联。输入数据流被同时加扰以产生多个随机数据流。输入数据流被加扰，使得在随机数据流中产生不同的位模式，即使输入数据流中相应的位模式是相同的。随机数据流被同时写入到磁带介质上的相关联的数据轨道上。还描述了相应的装置。

67. 发明授权

US08386883B2 Lengthening life of a limited life memory 有权
标题翻译：延长生命有限的生活记忆
公开(公告)号：US08386883B2
公开(公告)日：2013-02-26
申请号：US12391547
申请日：2009-02-24
申请人： Michele Franceschini , John Peter Karidis , Luis A Lastras-Montano , Thomas Mittelholzer , Mark N Wegman
发明人： Michele Franceschini , John Peter Karidis , Luis A Lastras-Montano , Thomas Mittelholzer , Mark N Wegman
IPC分类号： G11C29/00 , H01L29/04 , H01L29/10 , H01L31/036 , H01L31/00 , H01L21/70
CPC分类号： G11C13/0069 , G06F11/1012 , G11C13/0002 , G11C2207/104
摘要： A phase-change memory (PCM) includes a matrix of storage cells, including at least a first group with at least one cell. Each cell includes a phase change material having at least a first resistance value and a second resistance value, such that the first group can have an identical message encoded therein in at least a first way and a second way. The memory also includes a controller configured to encode the identical message in the at least first group the first or second way, based on which way causes the least amount of writing cost, given current levels of the group. Another embodiment of memory includes a matrix of storage cells, including at least a first group with at least one cell. Each of the storage cells has at least two levels, such that each of the storage cells can have an identical message encoded therein in at least a first way and a second way (the cells can be PCM or another technology). Each one of the storage cells is arbitrarily individually changeable among the at least two levels, and each of the cells is cost-asymmetric. A controller encodes the identical message in the at least first group using the first way or the second way, based on which way incurs a least cost when writing the message into the at least one cell of the at least first group, given current levels of the at least first group.
摘要翻译：相变存储器（PCM）包括存储单元矩阵，至少包括具有至少一个单元的第一组。每个单元包括具有至少第一电阻值和第二电阻值的相变材料，使得第一组可以以至少第一种方式和第二种方式在其中编码相同的消息。所述存储器还包括控制器，所述控制器被配置为在所述至少第一组中对所述第一或第二方式的相同消息进行编码，基于哪种方式，给出所述组的当前级别的最小写入成本量。存储器的另一实施例包括存储单元的矩阵，包括至少一个具有至少一个单元的第一组。每个存储单元具有至少两个级别，使得每个存储单元可以以至少第一种方式和第二种方式在其中编码相同的消息（该单元可以是PCM或另一种技术）。存储单元中的每一个在至少两个级别中可任意地单独变化，并且每个单元是成本不对称的。控制器使用第一种方法或第二种方式在至少第一组中编码相同的消息，基于哪种方式在将消息写入至少第一组的至少一个小区时产生最低成本，给定当前级别至少第一组。

68. 发明申请

US20120192034A1 Lengthening Life of a Limited Life Memory 有权
标题翻译：延长生命有限的生活记忆
公开(公告)号：US20120192034A1
公开(公告)日：2012-07-26
申请号：US13408407
申请日：2012-02-29
申请人： Michele Franceschini , John Peter Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mark N. Wegman
发明人： Michele Franceschini , John Peter Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mark N. Wegman
IPC分类号： G11C29/00 , G06F11/08
CPC分类号： G11C13/0069 , G06F11/1012 , G11C13/0002 , G11C2207/104
摘要： A phase-change memory (PCM) includes a matrix of storage cells, including at least a first group with at least one cell. Each cell includes a phase change material having at least a first resistance value and a second resistance value, such that the first group can have an identical message encoded therein in at least a first way and a second way. The memory also includes a controller configured to encode the identical message in the at least first group the first or second way, based on which way causes the least amount of writing cost, given current levels of the group. Another embodiment of memory includes a matrix of storage cells. Each of the storage cells has at least two levels, such that each of the storage cells can have an identical message encoded therein in at least a first way and a second way.
摘要翻译：相变存储器（PCM）包括存储单元矩阵，至少包括具有至少一个单元的第一组。每个单元包括具有至少第一电阻值和第二电阻值的相变材料，使得第一组可以以至少第一种方式和第二种方式在其中编码相同的消息。所述存储器还包括控制器，所述控制器被配置为在所述至少第一组中对所述第一或第二方式的相同消息进行编码，基于哪种方式，给出所述组的当前级别的最小写入成本量。存储器的另一实施例包括存储单元矩阵。每个存储单元具有至少两个级别，使得每个存储单元可以以至少第一种方式和第二种方式在其中编码相同的消息。

69. 发明申请

US20110069521A1 ADJUSTABLE WRITE BINS FOR MULTI-LEVEL ANALOG MEMORIES 有权
标题翻译：用于多级模拟记忆体的可调写文字
公开(公告)号：US20110069521A1
公开(公告)日：2011-03-24
申请号：US12566430
申请日：2009-09-24
申请人： Ibrahim M. Elfadel , Michele M. Franceschini , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Ibrahim M. Elfadel , Michele M. Franceschini , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C27/00 , G11C11/00
CPC分类号： G11C8/10 , G11C11/56 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C27/005 , G11C2013/0083
摘要： An analog memory having adjustable write bins including a system for writing to the memory. The system includes a write apparatus interpreting one or more write control signals, generating a write signal, and applying the write signal at a selected memory location to store a desired content. The selected memory location is subject to data dependent noise and is capable of storing a range of values grouped into “n” bins configured such that the average cost to write to at least “n-1” of the bins is within a threshold of a target cost for the selected analog memory location. The system also includes a read apparatus. The system further includes write control circuitry that includes a write signal selector selecting the one or more write control signals responsive to the desired content, current content of the selected memory location, and a bin associated with the desired content.
摘要翻译：具有可调节写入箱的模拟存储器，包括用于向存储器写入的系统。该系统包括解释一个或多个写入控制信号的写入装置，产生写入信号，以及在选择的存储器位置处施加写入信号以存储所需的内容。所选择的存储器位置受到数据相关噪声的影响，并且能够存储被分配到“n”个存储槽中的值的范围，其被配置为使得写入至少“n-1”个存储单元的平均成本在所选模拟存储器位置的目标成本。该系统还包括读取装置。该系统还包括写控制电路，其包括响应于期望内容选择一个或多个写入控制信号的写入信号选择器，所选择的存储器位置的当前内容以及与期望内容相关联的存储区。

70. 发明申请

US20090115647A1 MODULATION CODING AND DECODING 有权
标题翻译：调制编码和解码
公开(公告)号：US20090115647A1
公开(公告)日：2009-05-07
申请号：US12262297
申请日：2008-10-31
申请人： Thomas Mittelholzer
发明人： Thomas Mittelholzer
IPC分类号： H03M7/14
CPC分类号： H03M5/145 , H03M7/02 , H03M7/3088
摘要： Methods and apparatus are provided for modulation coding a stream of binary input data. A 4-ary enumerative encoding algorithm is applied to the input bit-stream to produce a succession of 4-ary output symbols. The 4-ary algorithm is operative to simultaneously encode respective generalized Fibonacci codes in the odd and even interleaves of the input bit-stream. The bits of each successive 4-ary output symbol are then interleaved, producing an output bit-stream which has global and interleaved run-length constraints. Inverting the bits of the 4-ary output symbols produces an output bit-stream with (G, I)-constraints as in the PRML (G, I) codes used in reverse-concatenation modulation systems. Corresponding decoding systems are also provided.
摘要翻译：提供了用于对二进制输入数据流进行调制编码的方法和装置。 4进制枚举编码算法被应用于输入比特流以产生一系列4进制输出符号。 4进制算法可用于在输入比特流的奇数和偶数交织中同时编码相应的广义斐波纳契码。然后每个连续的4进制输出符号的比特被交织，产生具有全局和交织的游程长度约束的输出比特流。反转四元输出符号的位产生与（G，I）约束的输出比特流，如反向级联调制系统中使用的PRML（G，I）码一样。还提供了相应的解码系统。

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