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61. 发明授权

US07929637B2 Method and apparatus for digital amplitude and phase modulation 有权
标题翻译：用于数字幅度和相位调制的方法和装置
公开(公告)号：US07929637B2
公开(公告)日：2011-04-19
申请号：US10927879
申请日：2004-08-27
申请人： Robert B. Staszewski , Sameh Rezeq , Dirk Leipold
发明人： Robert B. Staszewski , Sameh Rezeq , Dirk Leipold
IPC分类号： H04L27/00
CPC分类号： H03F3/24 , H03F1/0205 , H03F1/0211 , H03F1/32 , H03F2200/331 , H03F2200/451 , H04L27/361
摘要： A transmitter using quadrature modulation includes a rectangular to polar converter for converting data symbols into a polar form, where each polar symbol has a magnitude signal and an angle signal. Digital phase modulation circuitry includes an all digital PLL circuit for generating a phase modulated RF carrier signal responsive to the angle signal frequency control word (FCW) and a carrier frequency FCW. A digitally controlled amplifier for amplifying the phase modulated signal is controlled by a digital amplitude control circuitry for controlling the gain of the digitally controlled amplifier responsive to the magnitude signal.
摘要翻译：使用正交调制的发射机包括用于将数据符号转换成极性形式的矩形到极化转换器，其中每个极性符号具有幅度信号和角度信号。数字相位调制电路包括全数字PLL电路，用于响应角度信号频率控制字（FCW）和载波频率FCW产生相位调制的RF载波信号。用于放大相位调制信号的数字控制放大器由数字幅度控制电路控制，用于响应于幅度信号来控制数字控制放大器的增益。

62. 发明授权

US07791407B2 Technique for improving antialiasing and adjacent channel interference filtering using cascaded passive IIR filter stages combined with direct sampling and mixing 有权
标题翻译：使用级联无源IIR滤波器级与直接采样和混合相结合的改进抗混叠和相邻信道干扰滤波的技术
公开(公告)号：US07791407B2
公开(公告)日：2010-09-07
申请号：US11388558
申请日：2006-03-24
申请人： Khurram Muhammad , Robert B. Staszewski , Dirk Leipold
发明人： Khurram Muhammad , Robert B. Staszewski , Dirk Leipold
IPC分类号： H03K5/00
CPC分类号： H04B1/109 , H03H19/004
摘要： A technique of improving antialiasing and adjacent channel interference filtering uses cascaded passive IIR filter stages combined with direct sampling and mixing. The methodology and related architecture allows for increased passive IIR filtering without necessitating use of amplifier stages.
摘要翻译：改进抗混叠和相邻信道干扰滤波的技术使用级联无源IIR滤波器级与直接采样和混合相结合。该方法和相关架构允许增加无源IIR滤波，而不需要使用放大器级。

63. 发明申请

US20100188148A1 PREDISTORTION MECHANISM FOR COMPENSATION OF TRANSISTOR SIZE MISMATCH IN A DIGITAL POWER AMPLIFIER 审中-公开
标题翻译：用于补偿数字功率放大器中晶体管尺寸误差的预测机制
公开(公告)号：US20100188148A1
公开(公告)日：2010-07-29
申请号：US12359613
申请日：2009-01-26
申请人： Jaimin A. Mehta , Sameh S. Rezeq , Manouchehr Entezari , Robert B. Staszewski
发明人： Jaimin A. Mehta , Sameh S. Rezeq , Manouchehr Entezari , Robert B. Staszewski
IPC分类号： H03F1/26
CPC分类号： H03F1/3247 , H03F1/30
摘要： A novel and useful apparatus for and method of predistortion compensation of device (e.g., transistor) mismatch in a digital power amplifier (DPA). The device mismatch predistortion mechanism of the present invention addresses the problem of matching between two types of binary weighted transistors, whereby mismatched transistors cause degradation in wideband noise. The invention provides a digital predistortion mechanism which functions to pre-distort the mismatch ratio based on a data table calculated a priori enabling a polar transmitter to meet output spectrum and error vector magnitude (EVM) requirements of the particular modern wideband wireless standard, such as GSM, 3G WCDMA, etc.
摘要翻译：一种用于数字功率放大器（DPA）中的器件（例如，晶体管）失配的预失真补偿的新颖有用的装置和方法。本发明的器件失配预失真机制解决了两种二进制加权晶体管之间的匹配问题，由此失配的晶体管导致宽带噪声的降低。本发明提供了一种数字预失真机制，其用于基于先前计算的数据表来预失真失配比，使得极性发射机能够满足特定现代宽带无线标准的输出频谱和误差矢量幅度（EVM）要求，例如 GSM，3G WCDMA等

64. 发明授权

US07647192B2 Active removal of aliasing frequencies in a decimating structure by changing a decimation ratio in time and space 有权
标题翻译：通过在时间和空间上改变抽取比例，在抽取结构中主动去除混叠频率
公开(公告)号：US07647192B2
公开(公告)日：2010-01-12
申请号：US10924297
申请日：2004-08-23
申请人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
发明人： Khurram Muhammad , Robert B. Staszewski , Gennady Feygin
IPC分类号： G06F19/00
CPC分类号： H03D7/125 , H04B1/1036
摘要： When a sample stream is decimated, frequency components from outside of a desired frequency band are aliased into the desired band, causing interference and loss of information. Different decimating ratios result in different frequencies aliasing into the desired frequency band. A current-mode sampling mixer 800 with capacitor banks 811 and 812 that are controlled by a digital control unit 820 with a capability to integrate and decimate an RF current at different decimating ratios is able to measure the frequency spectrum with different decimating ratios. The measured frequency spectrum is then analyzed to detect the presence of interferers aliased into the desired frequency band. The interferers can then be eliminated or avoided.
摘要翻译：当采样流被抽取时，来自期望频带外部的频率分量被混叠成所需频带，导致信息的干扰和丢失。不同的抽取率导致不同的频率混叠成所需的频带。具有电容器组811和812的电流模式采样混频器800能够以不同的抽取率对能够集成和抽取RF电流的数字控制单元820进行控制，能够以不同的抽取率来测量频谱。然后分析测量的频谱以检测混叠到期望频带中的干扰源的存在。然后可以消除或避免干扰源。

65. 发明授权

US07460612B2 Method and apparatus for a fully digital quadrature modulator 有权
标题翻译：全数字正交调制器的方法和装置
公开(公告)号：US07460612B2
公开(公告)日：2008-12-02
申请号：US11203504
申请日：2005-08-11
申请人： Oren E. Eliezer , Francis P. Cruise , Robert B. Staszewski , Jaimin Mehta
发明人： Oren E. Eliezer , Francis P. Cruise , Robert B. Staszewski , Jaimin Mehta
IPC分类号： H04L27/00
CPC分类号： H03F3/24 , H03C3/40 , H03C5/00 , H03F2200/324 , H03F2200/331 , H03F2200/336 , H04K1/02 , H04L27/04 , H04L27/2092 , H04L27/365
摘要： A novel apparatus and method for a fully digital quadrature architecture for a complex modulator. The complex modulator can substitute for existing prior art analog quadrature modulator structures and those based on a digital polar architecture (r, θ). The modulator effectively operates as a complex digital-to-analog converter where the digital inputs are given in Cartesian form, namely I and Q representing the complex number I+jQ, while the output is a modulated RF signal having a corresponding amplitude and phase shift. The phase shift being with respect to a reference phase dictated by the local oscillator, which is also input to the converter/modulator. Several embodiments are provided including modulators incorporating dual I and Q transistor arrays, a single shared I/Q transistor array, modulators with single ended and differential outputs and modulators with single and dual polarity clock and I/Q data signals.
摘要翻译：一种用于复调制器的全数字正交架构的新型装置和方法。复调制器可以替代现有的现有技术的模拟正交调制器结构和基于数字极坐标（r，θ）的那些。调制器有效地作为复数数模转换器工作，其中数字输入以笛卡尔形式给出，即I和Q表示复数I + jQ，而输出是具有对应幅度和相移的调制RF信号。相移相对于由本地振荡器指定的参考相位，本地振荡器也被输入到转换器/调制器。提供了包括具有双I和Q晶体管阵列的调制器，单个共享I / Q晶体管阵列，具有单端和差分输出的调制器以及具有单极性和双极性时钟和I / Q数据信号的调制器的几个实施例。

66. 发明授权

US07382200B2 Type-II all-digital phase-locked loop (PLL) 有权
标题翻译： II型全数字锁相环（PLL）
公开(公告)号：US07382200B2
公开(公告)日：2008-06-03
申请号：US11464420
申请日：2006-08-14
申请人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad
发明人： Robert B. Staszewski , Dirk Leipold , Khurram Muhammad
IPC分类号： H03L7/00
CPC分类号： H03L7/1075 , H03F1/0211 , H03F1/3282 , H03L7/093 , H03L7/0991 , H03L7/107 , H03L2207/50
摘要： System and method for providing type-II (and higher order) phase-locked loops (PLLs) with a fast signal acquisition mode. A preferred embodiment comprises a loop filter with a proportional loop gain path (proportional loop gain circuit 1115) and an integral loop gain block (integral loop gain block 1120). The proportional loop gain path is used during signal acquisition to provide large loop bandwidth, hence fast signal acquisition of a desired signal. Then, during the PLL's signal tracking phase, the integral loop gain block is enabled and its output is combined with output from the proportional loop gain path to provide higher order filtering of the desired signal. An offset that may be present due to the use of the proportional loop gain path can be measured and subtracted to help improve signal tracking settling times.
摘要翻译：用于提供具有快速信号采集模式的II型（和更高阶）锁相环（PLL）的系统和方法。优选实施例包括具有比例环路增益路径（比例环路增益电路1115）和积分环路增益模块（积分环路增益模块1120）的环路滤波器。在信号采集期间使用比例环路增益路径来提供较大的环路带宽，从而快速获取所需信号的信号。然后，在PLL的信号跟踪阶段期间，使用积分环路增益模块，并将其输出与比例环路增益路径的输出相结合，以提供所需信号的高阶滤波。可以测量和减去由于使用比例环路增益路径而可能存在的偏移量，以帮助改善信号跟踪稳定时间。

67. 发明申请

US20070188243A1 FREQUENCY TUNING RANGE EXTENSION AND MODULATION RESOLUTION ENHANCEMENT OF A DIGITALLY CONTROLLED OSCILLATOR 有权
标题翻译：频率调谐范围扩展和调制分辨率增强数字控制振荡器
公开(公告)号：US20070188243A1
公开(公告)日：2007-08-16
申请号：US11618034
申请日：2006-12-29
申请人： Khurram Waheed , Siraj Akhtar , Robert B. Staszewski
发明人： Khurram Waheed , Siraj Akhtar , Robert B. Staszewski
IPC分类号： H03L7/00
CPC分类号： H03L7/099 , H03C5/00 , H03L7/10 , H03L2207/50
摘要： A novel apparatus and method of extending the frequency tuning range and improving the modulation resolution of an RF digitally controlled oscillator (DCO). In addition to the coarse PVT MIM varactor bank, the DCO uses a single unified bank of varactors that is further subdivided divided into an MSB bank, LSB bank and sigma-delta (SD-LSB) bank. Any ratio mismatches between MSBs and LSBs are digitally calibrated out using a DCO step-size pre-distortion scheme wherein the LSB steps are adjusted to account for the ratio mismatch between the MSB/LSB step sizes. A harmonic characterization technique is used to estimate the mismatches in the minimal size CMOS tuning varactors of a digitally controlled RF oscillator (DCO), wherein the nominal ratio mismatch between the MSB and LSB devices is estimated using hybrid stochastic gradient DCO gain estimation algorithms. The nominal ratio mismatch and the mismatches in the MSB and LSB banks are used to determine the average MSB/LSB mismatch. The average mismatch value is then used to correct the LSB steps.
摘要翻译：一种扩展频率调谐范围并提高RF数字控制振荡器（DCO）的调制分辨率的新型装置和方法。除了粗略的PVT MIM变容二极管组外，DCO还使用单个统一的变容二极管组，进一步细分为MSB组，LSB组和Σ-Δ（SD-LSB）组。使用DCO步长预失真方案对MSB和LSB之间的任何比例不匹配进行数字校准，其中LSB步长被调整以考虑MSB / LSB步长之间的比率失配。使用谐波表征技术来估计数字控制RF振荡器（DCO）的最小尺寸CMOS调谐变容二极管中的不匹配，其中使用混合随机梯度DCO增益估计算法来估计MSB和LSB器件之间的标称比率失配。标称比例失配和MSB和LSB组中的不匹配用于确定平均MSB / LSB失配。然后使用平均不匹配值来校正LSB步长。

68. 发明授权

US07218904B2 Removing close-in interferers through a feedback loop 有权
标题翻译：通过反馈回路消除紧密的干扰源
公开(公告)号：US07218904B2
公开(公告)日：2007-05-15
申请号：US10280156
申请日：2002-10-25
申请人： Robert B. Staszewski , Khurram Muhammad , Dirk Leipold
发明人： Robert B. Staszewski , Khurram Muhammad , Dirk Leipold
IPC分类号： H04B1/06 , H03F1/26
CPC分类号： H04B1/28 , H04B1/1036
摘要： System and method for elimination of close-in interferers through feedback. A preferred embodiment comprises an interferer predictor (for example, interferer predictor 840) coupled to a digital output of a direct RF radio receiver (for example, radio receiver 800). The interferer predictor predicts the presence of interferers and feeds the information back to a sampling unit (for example, sampling unit 805) through a feedback circuit (for example, feedback unit 845) through the use of charge sharing. The interferers are then eliminated in the sampling unit. Additionally, the number and placement of zeroes in a filter in the sampling unit is increased and changed through the implementation of arbitrary-coefficient finite impulse response filters.
摘要翻译：通过反馈消除接近干扰的系统和方法。优选实施例包括耦合到直接RF无线电接收机（例如，无线电接收机800）的数字输出的干扰源预测器（例如，干扰源预测器840）。干扰源预测器预测干扰源的存在，并且通过使用电荷共享通过反馈电路（例如，反馈单元845）将信息反馈给采样单元（例如，采样单元805）。然后在采样单元中消除干扰源。另外，通过执行任意系数有限脉冲响应滤波器来增加和改变采样单元滤波器中的零数和位置。

69. 发明授权

US06924681B2 Efficient pulse amplitude modulation transmit modulation 有权
标题翻译：有效的脉冲幅度调制发射调制
公开(公告)号：US06924681B2
公开(公告)日：2005-08-02
申请号：US10154093
申请日：2002-05-22
申请人： Robert B. Staszewski , Dirk Leipold , Kenneth J. Maggio
发明人： Robert B. Staszewski , Dirk Leipold , Kenneth J. Maggio
IPC分类号： H03F1/02 , H03F1/06 , H03F3/217 , H03K3/00 , H03K3/017 , H03K5/06 , H03K7/02 , H04B1/04
CPC分类号： H03F1/02 , H03F1/0205 , H03F3/217 , H03F3/2171 , H03F3/2176 , H03F2200/331 , H03K5/06 , H03K7/02 , H04B1/0483 , H04B2001/0491
摘要： Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.
摘要翻译：由PAM调制器提供有效的PAM发射调制，PAM调制器包括提供时钟信号CKV（408）的振荡器（404）。时钟信号408和时钟信号的延迟版本（CKV_DLY）420被提供给逻辑门（414）。逻辑门（414）的输出用作射频功率放大器（416）的功率放大器输入信号（PA_IN）。根据CKV时钟信号（408）和CKV_DLY延迟时钟信号（420）的相对时间延迟，可以控制逻辑门（414）占空比的定时和占空比。占空比或脉冲宽度变化影响功率放大器的导通时间（416）; 从而建立RF输出振幅。

70. 发明授权

US06851493B2 Digital PLL with gear shift 有权
标题翻译：数字PLL与换档
公开(公告)号：US06851493B2
公开(公告)日：2005-02-08
申请号：US09728180
申请日：2000-12-01
申请人： Robert B. Staszewski , Kenneth J. Maggio
发明人： Robert B. Staszewski , Kenneth J. Maggio
IPC分类号： H03L7/093 , H03L7/06 , H03L7/099 , H03L7/107 , H03L7/18 , H03D3/24
CPC分类号： H03L7/107 , H03L7/0991 , H03L7/1806
摘要： A PLL synthesizer (100) includes a gear-shifting scheme of the PLL loop gain constant, α. During frequency/phase acquisition, a larger loop gain constant, α1 is used such that the resulting phase error is within limits. After the frequency/phase gets acquired, the developed phase error, which is a rough indication of the frequency offset is in a steady-state condition. While transitioning into the tracking mode, the DC offset is added to the DCO tuning signal preferably the DC offset is added to the phase error signal and the loop constant is reduced from α1 to α2. This scheme provides for hitless operation, while requiring a low dynamic range of the phase detector (101).
摘要翻译： PLL合成器（100）包括PLL环路增益常数α的换档方案。在频率/相位采集期间，使用较大的环路增益常数α1，使得所得到的相位误差在限度内。在获取频率/相位之后，发展的相位误差是频率偏移的粗略指示处于稳态条件。当转换到跟踪模式时，DC偏移被添加到DCO调谐信号中，优选地，DC偏移被加到相位误差信号上，并且环路常数从α1减小到α2。该方案提供了无脉冲操作，同时需要相位检测器（101）的低动态范围。

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