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61. 发明授权

US06172920B2 Data transfer using two-stage bit switch in memory circuit 有权
标题翻译：在存储器电路中使用两级位开关进行数据传输
公开(公告)号：US06172920B2
公开(公告)日：2001-01-09
申请号：US09498087
申请日：2000-02-04
申请人： Sang Hoo Dhong , Manabu Ohkubo , Shohji Onishi , Osamu Takahashi
发明人： Sang Hoo Dhong , Manabu Ohkubo , Shohji Onishi , Osamu Takahashi
IPC分类号： G11C712
CPC分类号： G11C7/06 , G11C7/1048 , G11C7/12
摘要： A data transfer circuit for read data operations in a memory circuit employs a two-stage bit switch. True and compliment bit lines from a memory cell array are coupled to gates of a pair of transistors in a first stage bit switch. The data from the bit lines is thus transferred to a pair of read data nodes without a DC connection, so charge-sharing is avoided. Also, this allows the data to be extracted without a full logic-level swing of the bit lines, so faster operation is provided. The data from the data nodes is transferred to a pair of data lines through a second-stage bit switch activated by a timing input. The differential voltage on the bit lines is enhanced by a sense amplifier, and, also, the use of the first-stage bit switch allows the bit lines to be precharged to only half the logic level, speeding up operation; this sense amplifier is activated before the timing input for the second-stage bit switch. The data lines are precharged then selectively discharged through source-to-drain paths of the transistors of the first and second stage bit switches.
摘要翻译：用于在存储器电路中读取数据操作的数据传输电路采用两级位开关。来自存储单元阵列的真实和补充位线耦合到第一级位开关中的一对晶体管的栅极。因此，来自位线的数据被转移到没有DC连接的一对读数据节点，因此避免了电荷共享。此外，这允许在没有位线的完全逻辑电平摆幅的情况下提取数据，因此提供更快的操作。来自数据节点的数据通过由定时输入激活的第二级位开关传送到一对数据线。位线上的差分电压由读出放大器增强，并且使用第一级位开关也可以将位线预充电至逻辑电平的一半，加速操作; 该读出放大器在第二级位开关的定时输入之前被激活。数据线被预充电，然后通过第一和第二级位开关的晶体管的源极到漏极路径选择性地放电。

62. 发明授权

US07318182B2 Memory array manufacturing defect detection system and method 失效
标题翻译：内存阵列制造缺陷检测系统及方法
公开(公告)号：US07318182B2
公开(公告)日：2008-01-08
申请号：US11002692
申请日：2004-12-02
申请人： Louis Bernard Bushard , Sang Hoo Dhong , Brian King Flachs , Osamu Takahashi , Michael Brian White
发明人： Louis Bernard Bushard , Sang Hoo Dhong , Brian King Flachs , Osamu Takahashi , Michael Brian White
IPC分类号： G01R31/28
CPC分类号： G11C29/08 , G11C7/20 , G11C2029/0407
摘要： The present invention provides for a method for memory array verification. Initialization commands are received and memory array initialization settings are generated based on received initialization commands. The memory array initialization settings are stored in a memory array. A deterministic read output function for the memory array is identified and a logic built-in self test scan on the memory array is performed based on the identified deterministic read output function.
摘要翻译：本发明提供了一种用于存储器阵列校验的方法。接收初始化命令，并根据接收到的初始化命令生成内存阵列初始化设置。存储器阵列初始化设置存储在存储器阵列中。识别存储器阵列的确定性读输出功能，并且基于所识别的确定性读输出功能来执行存储器阵列上的逻辑内置自检扫描。

63. 发明授权

US07113443B2 Method of address distribution time reduction for high speed memory macro 失效
标题翻译：高速存储器宏的地址分配时间缩短方法
公开(公告)号：US07113443B2
公开(公告)日：2006-09-26
申请号：US10965627
申请日：2004-10-14
申请人： Sang Hoo Dhong , Hiroaki Murakami , Shohji Onishi , Osamu Takahashi
发明人： Sang Hoo Dhong , Hiroaki Murakami , Shohji Onishi , Osamu Takahashi
IPC分类号： G11C8/00
CPC分类号： G11C8/06
摘要： An apparatus, a method, and a computer program product are provided for time reduction and energy conservation during address distribution in a high speed memory macro. To address these concerns, this design divides the typical data arrays into sets of paired subarrays, divides the conventional memory address latches into separate sets, and interposes one set of memory address latches between each pair of subarrays. Therefore, time is saved because the address signals have less wire length to travel and energy is saved because only one set of address latches needs to be powered on for each transmission.
摘要翻译：提供了一种在高速存储器宏中的地址分配期间用于时间减少和节能的装置，方法和计算机程序产品。为了解决这些问题，该设计将典型的数据阵列划分为成对的阵列集合，将传统的存储器地址锁存器分成单独的集合，并在每对子阵列之间插入一组存储器地址锁存器。因此，节省时间是因为地址信号具有更少的导线长度以保持行驶并且能量被节省，因为每个传输只需要为一个地址锁存器供电。

64. 发明授权

US06717882B1 Cell circuit for multiport memory using 3-way multiplexer 失效
标题翻译：使用3路复用器的多端口存储器的单元电路
公开(公告)号：US06717882B1
公开(公告)日：2004-04-06
申请号：US10273590
申请日：2002-10-17
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Shoji Onishi , Osamu Takahashi
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Shoji Onishi , Osamu Takahashi
IPC分类号： G11C800
CPC分类号： G11C8/16
摘要： An improved cell circuit for data readout for use in a multiport memory is provided. The multiport memory stores write data signals. The cell circuit includes a plurality of multiplexers each coupled to a discharge device. Each of the multiplexers receives a subset of the write data signals and a plurality of read wordline signals and selects an output enable signal among the subset of the write data signals based on the read wordline signals. Each of the discharge devices are coupled to one of the multiplexers for receiving the output enable signal to generate a drive signal for driving one or more bitlines of the multiport memory.
摘要翻译：提供用于多端口存储器中的用于数据读出的改进的单元电路。多端口存储器存储写入数据信号。电池电路包括多个多路复用器，每个多路复用器耦合到放电装置。每个多路复用器接收写入数据信号的子集和多个读取字线信号，并且基于所读取的字线信号在写入数据信号的子集中选择输出使能信号。每个放电装置耦合到多路复用器中的一个，用于接收输出使能信号，以产生用于驱动多端口存储器的一个或多个位线的驱动信号。

65. 发明授权

US06285218B1 Method and apparatus for implementing logic using mask-programmable dynamic logic gates 有权
标题翻译：使用掩码可编程动态逻辑门实现逻辑的方法和装置
公开(公告)号：US06285218B1
公开(公告)日：2001-09-04
申请号：US09567381
申请日：2000-05-10
申请人： Sang Hoo Dhong , Hung Cai Ngo , Jaehong Park , Osamu Takahashi
发明人： Sang Hoo Dhong , Hung Cai Ngo , Jaehong Park , Osamu Takahashi
IPC分类号： H03K19094
CPC分类号： H03K19/1736
摘要： A method and apparatus for implementing dynamic logic with programmable dynamic logic gates acts as a complement to programmable logic arrays (PLAs) used in high-speed microprocessor designs. A matrix of selectable cells provides powerful logic functions such as AND-OR gate capability with a minimum of inputs and transistors. By using programmable logic arrays and programmable dynamic gates, the efficiency of a logic block can be dramatically improved with little added circuit area.
摘要翻译：用于用可编程动态逻辑门实现动态逻辑的方法和装置作为用于高速微处理器设计中的可编程逻辑阵列（PLA）的补充。可选单元的矩阵提供强大的逻辑功能，例如具有最小输入和晶体管的AND-OR门能力。通过使用可编程逻辑阵列和可编程动态门，逻辑块的效率可以大大提高，几乎没有增加电路面积。

66. 发明授权

US07716516B2 Method for controlling operation of microprocessor which performs duty cycle correction process 失效
标题翻译：用于控制执行占空比校正处理的微处理器的操作的方法
公开(公告)号：US07716516B2
公开(公告)日：2010-05-11
申请号：US11471819
申请日：2006-06-21
申请人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry, Jr. , Sang Hoo Dhong
发明人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry, Jr. , Sang Hoo Dhong
IPC分类号： G06F1/04 , G06F1/24 , G06F11/00
CPC分类号： G06F1/04
摘要： A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.
摘要翻译：用于向微处理器提供电源电压的技术。在微处理器的正常运算处理之前，执行用于调整微处理器内的时钟信号占空比的占空比校正处理。在用于调整占空比的占空比校正处理中，调整时钟信号的占空比以使微处理器仍然可操作的电源电压最小化。

67. 发明授权

US07447725B2 Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units 失效
标题翻译：用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置
公开(公告)号：US07447725B2
公开(公告)日：2008-11-04
申请号：US10982110
申请日：2004-11-05
申请人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Harm Peter Hofstee , Christian Jacobi , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/38
CPC分类号： G06F7/49947 , G06F7/483 , G06F7/49968 , G06F7/49973 , G06F7/49989 , G06F2207/3828
摘要： An apparatus for controlling rounding modes in a single instruction multiple data (SIMD) floating-point unit is disclosed. The SIMD floating-point unit includes a floating-point status-and-control register (FPSCR) having a first rounding mode bit field and a second rounding mode bit field. The SIMD floating-point unit also includes means for generating a first slice and a second slice. During a floating-point operation, the SIMD floating-point unit concurrently performs a first rounding operation on the first slice and a second rounding operation on the second slice according to a bit in the first rounding mode bit field and a bit in the second rounding mode bit field within the FPSCR, respectively.
摘要翻译：公开了一种用于在单指令多数据（SIMD）浮点单元中控制舍入模式的装置。 SIMD浮点单元包括具有第一舍入模式位字段和第二舍入模式位字段的浮点状态和控制寄存器（FPSCR）。 SIMD浮点单元还包括用于生成第一切片和第二切片的装置。在浮点运算期间，SIMD浮点单元根据第一舍入模式位字段中的位并且在第二舍入中的位同时对第一切片进行第一舍入运算，并对第二切片进行第二舍入运算 FPSCR中的模式位字段。

68. 发明授权

US07406589B2 Processor having efficient function estimate instructions 失效
标题翻译：处理器具有有效的功能估计指令
公开(公告)号：US07406589B2
公开(公告)日：2008-07-29
申请号：US11127848
申请日：2005-05-12
申请人： Sang Hoo Dhong , Gordon Clyde Fossum , Harm Peter Hofstee , Brad William Michael , Silvia Melitta Mueller , Hwa-Joon Oh
发明人： Sang Hoo Dhong , Gordon Clyde Fossum , Harm Peter Hofstee , Brad William Michael , Silvia Melitta Mueller , Hwa-Joon Oh
IPC分类号： G06F7/552 , G06F7/544 , G06F7/38
CPC分类号： G06F7/483 , G06F7/535 , G06F7/5443 , G06F7/5525 , G06F9/30014 , G06F2207/5356
摘要： High-precision floating-point function estimates are split in two instructions each: a low precision table lookup instruction and a linear interpolation instruction. Estimates of different functions can be implemented using this scheme: A separate table-lookup instruction is provided for each different function, while only a single interpolation instruction is needed, since the single interpolation instruction can perform the interpolation step for any of the functions to be estimated. Thus, significantly less overhead is incurred than would be incurred with specialized hardware, while still maintaining a uniform FPU latency, which allows for much simpler control logic.
摘要翻译：高精度浮点函数估计分为两个指令：低精度表查找指令和线性插值指令。可以使用该方案来实现不同功能的估计：为每个不同的功能提供单独的表查找指令，而仅需要单个插补指令，因为单个内插指令可以执行任何功能的内插步骤估计。因此，与专用硬件相比，产生的开销大大降低，同时仍保持统一的FPU延迟，这允许更简单的控制逻辑。

69. 发明授权

US07237163B2 Leakage current reduction system and method 有权
标题翻译：漏电流减少系统及方法
公开(公告)号：US07237163B2
公开(公告)日：2007-06-26
申请号：US10982111
申请日：2004-11-05
申请人： Sang Hoo Dhong , Hwa-Joon Oh , Silvia Melitta Mueller , Joel Silberman
发明人： Sang Hoo Dhong , Hwa-Joon Oh , Silvia Melitta Mueller , Joel Silberman
IPC分类号： G01R31/28
CPC分类号： G06F11/267 , G01R31/3008
摘要： An apparatus, a method and a computer program are provided to reduce leakage current in a processor. Traditionally, extra logic is employed to reduce leakage currents. However, reducing leakage current without sacrificing fine grain operations and speed can be difficult. Achieving such a goal can be accomplished by incorporating a multiplexer (mux) into the scan-in path of scan registers so that units or sub-units of the processor can be powered down individually. Additionally, the muxes are not incorporated into time paths, so speed can be preserved.
摘要翻译：提供了一种装置，方法和计算机程序以减少处理器中的泄漏电流。传统上，采用额外的逻辑来减少漏电流。然而，减少泄漏电流而不牺牲精细的晶粒操作和速度可能是困难的。可以通过将多路复用器（多路复用器）复用到扫描寄存器的扫描路径中来实现这一目标，从而可以单独关闭处理器的单元或子单元。此外，多路复用器并不并入时间路径，因此可以保留速度。

70. 发明授权

US07149877B2 Byte execution unit for carrying out byte instructions in a processor 失效
标题翻译：用于在处理器中执行字节指令的字节执行单元
公开(公告)号：US07149877B2
公开(公告)日：2006-12-12
申请号：US10621908
申请日：2003-07-17
申请人： Sang Hoo Dhong , Hwa-Joon Oh , Brad William Michael , Silvia Melitta Mueller , Kevin D. Tran
发明人： Sang Hoo Dhong , Hwa-Joon Oh , Brad William Michael , Silvia Melitta Mueller , Kevin D. Tran
IPC分类号： G06F15/76
CPC分类号： G06F9/30014 , G06F9/30036
摘要： A disclosed byte execution unit receives byte instruction information and two operands, and performs an operation specified by the byte instruction information upon one or both of the operands, thereby producing a result. The byte instruction specifies either a count ones in bytes operation, an average bytes operation, an absolute differences of bytes operation, or a sum bytes into halfwords operation. In one embodiment, the byte execution unit includes multiple byte units. Each byte unit includes multiple population counters, two compressor units, adder input multiplexer logic, adder logic, and result multiplexer logic. A data processing system is described including a processor coupled to a memory system. The processor includes the byte execution unit. The memory system includes a byte instruction, wherein the byte instruction specifies either the count ones in bytes operation, the average bytes operation, the absolute differences of bytes operation, or the sum bytes into halfwords operation.
摘要翻译：公开的字节执行单元接收字节指令信息和两个操作数，并且在一个或两个操作数上执行由字节指令信息指定的操作，从而产生结果。字节指令指定以字节为单位的计数值，平均字节操作，字节操作的绝对差值，或字节字节到半字操作。在一个实施例中，字节执行单元包括多个字节单元。每个字节单元包括多个总体计数器，两个压缩器单元，加法器输入复用器逻辑，加法器逻辑和结果复用器逻辑。描述了包括耦合到存储器系统的处理器的数据处理系统。处理器包括字节执行单元。存储器系统包括一个字节指令，其中字节指令指定字节操作中的计数值，平均字节操作，字节操作的绝对差值，或字节数字到半字操作。

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