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61. 发明授权

US09286257B2 Bus clock frequency scaling for a bus interconnect and related devices, systems, and methods 有权
标题翻译：总线互连及相关设备，系统和方法的总线时钟频率缩放
公开(公告)号：US09286257B2
公开(公告)日：2016-03-15
申请号：US13015657
申请日：2011-01-28
申请人： Richard Gerard Hofmann , Jaya Prakash Subramaniam Ganasan , Brandon Wayne Lewis
发明人： Richard Gerard Hofmann , Jaya Prakash Subramaniam Ganasan , Brandon Wayne Lewis
IPC分类号： G06F13/00 , G06F13/40 , G06F1/06 , G06F1/32
CPC分类号： G06F13/4022 , G06F1/06 , G06F1/3209 , G06F1/324 , Y02D10/126 , Y02D10/151
摘要： Bus clock frequency scaling for a bus interconnect and related devices, systems, and methods are disclosed. In one embodiment, the bus interconnect comprises an interconnect network configurable to connect a master port(s) to a slave port(s). A bus interconnect clock signal clocks the interconnect network. The controller is configured to receive bandwidth information related to traffic communicated over the master port(s) and the slave port(s). The controller is further configured to scale (e.g., increase or decrease) the frequency of the bus interconnect clock signal if the bandwidth of the master port(s) and/or the slave port(s) meets respective bandwidth condition(s), and/or if the latency of the master port(s) meets a respective latency condition(s) for the master port(s). The master port(s) and/or slave port(s) can also be reconfigured in response to a change in frequency of the bus interconnect clock signal to optimize performance and conserve power.
摘要翻译：公布了总线互连及相关设备，系统和方法的总线时钟频率缩放。在一个实施例中，总线互连包括可配置为将主端口连接到从端口的互连网络。总线互连时钟信号对互连网络进行时钟。控制器被配置为接收与通过主端口和从端口传送的业务相关的带宽信息。如果主端口和/或从端口的带宽满足相应的带宽条件，则控制器进一步被配置为扩展（例如，增加或减少）总线互连时钟信号的频率，以及 /或如果主端口的延迟满足主端口的相应等待时间条件。主端口和/或从端口也可以被重新配置以响应总线互连时钟信号的频率变化，以优化性能并节省功率。

62. 发明授权

US09026744B2 Enforcing strongly-ordered requests in a weakly-ordered processing 有权
标题翻译：在弱有序的处理中执行强有序的请求
公开(公告)号：US09026744B2
公开(公告)日：2015-05-05
申请号：US11253307
申请日：2005-10-19
申请人： Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Jaya Prakash Subramaniam Ganasan , James Norris Dieffenderfer , James Edward Sullivan
发明人： Richard Gerard Hofmann , Thomas Andrew Sartorius , Thomas Philip Speier , Jaya Prakash Subramaniam Ganasan , James Norris Dieffenderfer , James Edward Sullivan
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G06F13/1621
摘要： The disclosure is directed to a weakly-ordered processing system and method for enforcing strongly-ordered memory access requests in a weakly-ordered processing system. The processing system includes a plurality of memory devices and a plurality of processors. Each of the processors are configured to generate memory access requests to one or more of the memory devices, with each of the memory access requests having an attribute that can be asserted to indicate a strongly-ordered request. The processing system further includes a bus interconnect configured to interface the processors to the memory devices, the bus interconnect being further configured to enforce ordering constraints on the memory access requests based on the attributes.
摘要翻译：本公开涉及一种用于在弱有序处理系统中强制执行强有序存储器访问请求的弱有序处理系统和方法。处理系统包括多个存储器件和多个处理器。每个处理器被配置为生成对一个或多个存储器设备的存储器访问请求，其中每个存储器访问请求具有可以被断言以指示强有序请求的属性。处理系统还包括被配置为将处理器与存储器设备接口的总线互连，总线互连还被配置为基于属性来强制对存储器访问请求的排序限制。

63. 发明授权

US08675679B2 Cooperative writes over the address channel of a bus 有权
标题翻译：在总线的地址通道上进行合作写入
公开(公告)号：US08675679B2
公开(公告)日：2014-03-18
申请号：US13330734
申请日：2011-12-20
申请人： Richard Gerard Hofmann , Terence J. Lohman
发明人： Richard Gerard Hofmann , Terence J. Lohman
IPC分类号： H04J3/00
CPC分类号： G06F13/4243 , G06F13/42 , G06F13/4273
摘要： A method of communicating over a bus is disclosed. The bus includes a write address channel, a write channel, and a read address channel. The method includes sending an address from a sending device to a receiving device via the write address channel. The method further includes concurrently sending a portion of a payload to the receiving device via the write channel and another portion of the payload to the receiving device via the read address channel. When sending multiple sequential portions of the payload via the bus concurrently, the sending device is configured to give data ordering preference to the write channel over the read address channel by sending a first sequential portion of the multiple sequential portions via the write channel and sending a subsequent sequential portion of the multiple sequential portions via the read address channel.
摘要翻译：公开了一种通过总线进行通信的方法。总线包括写地址通道，写通道和读地址通道。该方法包括经由写入地址信道从发送设备发送地址到接收设备。该方法还包括经由读取地址信道经由写入信道和有效载荷的另一部分经由读取地址信道同时将一部分有效负载发送到接收设备。当经由总线同时发送有效负载的多个连续部分时，发送设备被配置为通过经由写入通道发送多个连续部分的第一顺序部分来通过读取地址信道给予写入信道的数据排序偏好，并且发送多个顺序部分的后续顺序部分经由读地址信道。

64. 发明授权

US08661274B2 Temperature compensating adaptive voltage scalers (AVSs), systems, and methods 有权
标题翻译：温度补偿自适应电压缩放器（AVS），系统和方法
公开(公告)号：US08661274B2
公开(公告)日：2014-02-25
申请号：US12701657
申请日：2010-02-08
申请人： David W. Hansquine , Richard Gerard Hofmann , Richard Alan Moore
发明人： David W. Hansquine , Richard Gerard Hofmann , Richard Alan Moore
IPC分类号： G06F1/04 , G06F1/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Adaptive voltage scalers (AVSs), systems, and related methods are disclosed. The AVSs are configured to adaptively adjust voltage levels powering a functional circuit(s) based on target operating frequencies and delay variation conditions to avoid or reduce voltage margin. In one embodiment, the AVS includes a database. The database can be configured to store voltage levels for various operating frequencies of a functional circuit(s) to avoid or reduce voltage margin. The database allows rapid voltage level decisions. In one embodiment, a voltage offset is added to a voltage level retrieved from the database corresponding to a target operating frequency of the functional circuit(s). In another embodiment, a voltage level is retrieved from the database corresponding to a target operating frequency for and a temperature level of the functional circuit(s). The AVS may partially or fully controllable by a software-based module that consults the database to make voltage level decisions.
摘要翻译：自适应电压缩放器（AVS），系统和相关方法被公开。 AVS被配置为基于目标工作频率和延迟变化条件自适应地调整为功能电路供电的电压电平，以避免或减少电压裕度。在一个实施例中，AVS包括数据库。数据库可以配置为存储功能电路的各种工作频率的电压电平，以避免或减少电压裕度。数据库允许快速的电压电平决定。在一个实施例中，电压偏移被添加到从数据库检索的电压电平，该电压电平对应于功能电路的目标工作频率。在另一个实施例中，从对应于功能电路的目标工作频率和温度水平的数据库检索电压电平。 AVS可以由参考数据库的基于软件的模块部分或完全控制，以进行电压电平决定。

65. 发明授权

US08615638B2 Memory controllers, systems and methods for applying page management policies based on stream transaction information 有权
标题翻译：基于流交易信息应用页面管理策略的内存控制器，系统和方法
公开(公告)号：US08615638B2
公开(公告)日：2013-12-24
申请号：US12900857
申请日：2010-10-08
申请人： Martyn Ryan Shirlen , Richard Gerard Hofmann , Mark Michael Schaffer
发明人： Martyn Ryan Shirlen , Richard Gerard Hofmann , Mark Michael Schaffer
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F13/1689 , G06F12/0215
摘要： Memory controllers, systems, methods, and computer-readable mediums for applying a page management policy(ies) based on stream transaction information are disclosed. In one embodiment, a memory controller is provided and configured to receive memory access requests for stream transactions. The memory controller is configured to perform a memory access to a memory page(s) in memory included in the stream transaction. The controller is further configured to apply a page management policy(ies) to the memory page(s) in memory based on information related to the stream transactions. In this manner, the page management policy(ies) can be configured to utilize page open policies for efficiency that stream transactions may facilitate, but while also recognizing and taking into consideration in the page management policy latency issues that can arise when the memory controller is handling memory access requests from different devices.
摘要翻译：公开了用于基于流交易信息应用页面管理策略的内存控制器，系统，方法和计算机可读介质。在一个实施例中，存储器控制器被提供并被配置为接收流事务的存储器访问请求。存储器控制器被配置为对包含在流事务中的存储器中的存储器页执行存储器访问。控制器还被配置为基于与流事务相关的信息将页面管理策略应用于存储器中的存储器页面。以这种方式，页面管理策略可以被配置为利用页面打开的策略来实现流交易可以促进的效率，但是在存储器控制器是可能出现的页面管理策略延迟问题的同时还识别和考虑处理来自不同设备的存储器访问请求。

66. 发明授权

US08107492B2 Cooperative writes over the address channel of a bus 有权
标题翻译：在总线的地址通道上进行合作写入
公开(公告)号：US08107492B2
公开(公告)日：2012-01-31
申请号：US11468908
申请日：2006-08-31
申请人： Richard Gerard Hofmann , Terence J. Lohman
发明人： Richard Gerard Hofmann , Terence J. Lohman
IPC分类号： H04J3/00
CPC分类号： G06F13/4243 , G06F13/42 , G06F13/4273
摘要： A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to write a first portion of a payload to the receiving device on the first channel and a second portion of the payload to the receiving device on the third channel.
摘要翻译：公开了一种用于通过总线在处理系统中通信的处理系统和方法。处理系统包括接收装置，具有第一，第二和第三信道的总线，以及配置成在第一信道上寻址接收装置并从第二信道上的接收装置读取有效载荷的发送装置，发送装置是还被配置为将所述有效负载的第一部分写入所述第一信道上的所述接收设备，并且将所述有效载荷的第二部分写入所述第三信道上的接收设备。

67. 发明申请

US20100005208A1 Efficient Execution of Memory Barrier Bus Commands 有权
标题翻译：高效执行内存障碍总线命令
公开(公告)号：US20100005208A1
公开(公告)日：2010-01-07
申请号：US12561381
申请日：2009-09-17
申请人： James Edward Sullivan, JR. , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann
发明人： James Edward Sullivan, JR. , Jaya Prakash Subramaniam Ganasan , Richard Gerard Hofmann
IPC分类号： G06F13/00
CPC分类号： G06F13/1621 , G06F9/52 , G06F9/522
摘要： The disclosure is directed to a weakly-ordered processing system and method of executing memory barriers in weakly-ordered processing system. The processing system includes memory and a master device configured to issue memory access requests, including memory barriers, to the memory. The processing system also includes a slave device configured to provide the master device access to the memory, the slave device being further configured to produce a signal indicating that an ordering constraint imposed by a memory barrier issued by the master device will be enforced, the signal being produced before the execution of all memory access requests issued by the master device to the memory before the memory barrier.
摘要翻译：本公开涉及一种弱有序处理系统和在弱有序处理系统中执行存储障碍的方法。处理系统包括存储器和被配置为向存储器发出存储器访问请求（包括存储器障碍）的主设备。处理系统还包括被配置为提供主设备对存储器的访问的从设备，从设备还被配置为产生指示由主设备发布的存储器障碍施加的排序约束将被强制的信号，信号在执行由主设备发出的所有存储器访问请求之前在存储器屏障之前被产生到存储器。

68. 发明申请

US20090228698A1 Method and Apparatus for Detecting Unauthorized Access to a Computing Device and Securely Communicating Information about such Unauthorized Access 有权
标题翻译：用于检测未授权访问计算设备的方法和装置，并且安全地传达关于这种未授权访问的信息
公开(公告)号：US20090228698A1
公开(公告)日：2009-09-10
申请号：US12044409
申请日：2008-03-07
申请人： Martyn Ryan Shirlen , Richard Gerard Hofmann
发明人： Martyn Ryan Shirlen , Richard Gerard Hofmann
IPC分类号： H04L9/00 , G06F11/00
CPC分类号： H04L63/1416 , G06F21/55 , G06F21/554 , G06F2221/2115
摘要： A method and apparatus for detecting attacks against a computing device are described. Such attacks may be detected by the device and reported to a requesting entity in a manner that makes it difficult for an attacker to know that the attack has been detected. Several exemplary embodiments comprising different client/server and client/network type systems are presented.
摘要翻译：描述了用于检测针对计算设备的攻击的方法和装置。这种攻击可以由设备检测并以使得攻击者难以知道已经检测到攻击的方式报告给请求实体。呈现了包括不同客户端/服务器和客户端/网络类型系统的几个示例性实施例。

69. 发明授权

US07523449B2 System and method for adaptive run-time reconfiguration for a reconfigurable instruction set co-processor architecture 失效
标题翻译：用于可重构指令集协处理器架构的自适应运行时重新配置的系统和方法
公开(公告)号：US07523449B2
公开(公告)日：2009-04-21
申请号：US11508714
申请日：2006-08-23
申请人： Sameh W. Asaad , Richard Gerard Hofmann
发明人： Sameh W. Asaad , Richard Gerard Hofmann
IPC分类号： G06F9/45 , G06F9/44 , G06F15/00 , G06F7/38 , G06F12/00
CPC分类号： G06F9/3885 , G06F8/443 , G06F9/30181 , G06F9/3897
摘要： A method for adaptive runtime reconfiguration of a co-processor instruction set, in a computer system with at least a main processor communicatively connected to at least one reconfigurable co-processor, includes the steps of configuring the co-processor to implement an instruction set comprising one or more co-processor instructions, issuing a co-processor instruction to the co-processor, and determining whether the instruction is implemented in the co-processor. For an instruction not implemented in the co-processor instruction set, raising a stall signal to delay the main processor, determining whether there is enough space in the co-processor for the non-implemented instruction, and if there is enough space for said instruction, reconfiguring the instruction set of the co-processor by adding the non-implemented instruction to the co-processor instruction set. The stall signal is cleared and the instruction is executed.
摘要翻译：一种在具有通信地连接到至少一个可重配置协处理器的至少一个主处理器的计算机系统中的协处理器指令集的自适应运行时重新配置的方法包括以下步骤：配置协处理器以实现包括一个或多个协处理器指令，向协处理器发出协处理器指令，以及确定在协处理器中是否实现指令。对于未在协处理器指令集中实现的指令，提高失速信号以延迟主处理器，确定协处理器中对于未实现指令是否有足够的空间，以及如果存在足够的空间用于所述指令通过将未实现的指令添加到协处理器指令集来重新配置协处理器的指令集。停止信号被清除，指令被执行。

70. 发明申请

US20070233904A1 Auxiliary Writes Over Address Channel 有权
标题翻译：辅助写入地址通道
公开(公告)号：US20070233904A1
公开(公告)日：2007-10-04
申请号：US11468933
申请日：2006-08-31
申请人： Richard Gerard Hofmann , Terence J. Lohman
发明人： Richard Gerard Hofmann , Terence J. Lohman
IPC分类号： G06F3/00
CPC分类号： G06F13/4282 , G06F13/4265
摘要： A processing system and method for communicating in a processing system over a bus is disclosed. The processing system includes a receiving device, a bus having first, second and third channels, and a sending device configured to address the receiving device on the first channel, and read a payload from the receiving device on the second channel, the sending device being further configured to select between the first and third channels to write a payload to the receiving device.
摘要翻译：公开了一种用于通过总线在处理系统中通信的处理系统和方法。处理系统包括接收装置，具有第一，第二和第三信道的总线，以及配置成在第一信道上寻址接收装置并从第二信道上的接收装置读取有效载荷的发送装置，发送装置是还被配置为在所述第一和第三信道之间选择以将有效负载写入所述接收设备。

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