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61. 发明授权

US07003510B2 Table module compiler equivalent to ROM 有权
公开(公告)号：US07003510B2
公开(公告)日：2006-02-21
申请号：US10177591
申请日：2002-06-19
申请人： Alexander E. Andreev , Ranko Scepanovic
发明人： Alexander E. Andreev , Ranko Scepanovic
IPC分类号： H03K19/20 , G06F17/50 , G06F17/30
CPC分类号： G06F17/5045 , Y10S707/99933
摘要： A method of constructing a circuit for a Boolean function includes receiving as input a Boolean function of a number n of input variables wherein the number n of input variables may be varied over a range; generating at least two intermediate functions comprising sub-functions of the Boolean function wherein zero or one is substituted for all but two of the number n of input variables; and generating a selected output of the Boolean function of the number n of input variables from only two of the intermediate functions.

62. 发明授权

US06536027B1 Cell pin extensions for integrated circuits 失效
标题翻译：集成电路的单元针扩展
公开(公告)号：US06536027B1
公开(公告)日：2003-03-18
申请号：US09735837
申请日：2000-12-13
申请人： Mikhail I. Grinchuk , Alexander E. Andreev , Ranko Scepanovic
发明人： Mikhail I. Grinchuk , Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： A metal wire for a feature of a cell is extended using a grid based on a metal layer of the cell. Each grid element is assigned an “F” designator representing the metal wire being extended, an “E” designator representing blockages to extension of the metal wire, such as metal wires of other features, or a “U” designator representing grid elements that are neither F-designated, nor E-designated grid elements. U-designated grid elements that are neighbors to E-designated grid elements are identified. A minimum length path is defined through the U-designated grid elements that are not neighbors to E-designated grid elements between the cell boundary and a F-designated grid element.
摘要翻译：使用基于电池的金属层的栅格来延长用于电池特征的金属线。每个网格元素被分配一个表示正在扩展的金属线的“F”指示符，表示阻止金属线延伸的“E”指示符，例如其他特征的金属线，或表示网格元素的“U” F指定，E指定网格元素。与E指定的网格元素相邻的U指定网格元素被识别。通过U指定的网格元素定义最小长度路径，该网格元素不是单元格边界和F指定的网格元素之间的E指定网格元素的邻居。

63. 发明授权

US06292924B1 Modifying timing graph to avoid given set of paths 失效
标题翻译：修改时序图以避免给定的路径集
公开(公告)号：US06292924B1
公开(公告)日：2001-09-18
申请号：US08964997
申请日：1997-11-05
申请人： Ivan Pavisic , Anatoli A. Bolotov , Alexander E. Andreev , Ranko Scepanovic
发明人： Ivan Pavisic , Anatoli A. Bolotov , Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F1750
CPC分类号： G06F17/5031
摘要： Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Designing of the IC's require meeting real-world constraints such as minimization of the circuit area, minimization of wire length within the circuit, and minimization of the time the IC requires to perform its function, referred to as the IC delay. In order to design circuits to meet a given set of requirements, each signal path of the circuit must be analyzed. Because of the large number of the cells and the complex connections, the number of paths is very large and requires much computing power to analyze. Also, some of the paths are not important for the purposes of the operations of the chip and can be discounted during the analysis process. The present invention discloses a method and apparatus used to avoid analyzing non-important paths, referred to as false paths of a directed timing graph. To avoid the false paths, the timing graph representing the circuit is modified to exclude the false paths before the graph is analyzed. To modify the timing graph, duplicate nodes are constructed, duplicate edges are constructed, and some edges of the original graph are cut and replaced by mixed edges connecting non-duplicate nodes to duplicate nodes. Finally, mixed edges are created to connect duplicate nodes to non-duplicate nodes, integrating the duplicate graph with the original graph.
摘要翻译：集成电路芯片（IC）需要适当放置许多单元（电路组件组）和复杂的导线布线以连接单元的引脚。 IC的设计需要满足实际的限制，例如最小化电路面积，最小化电路内的电线长度，以及使IC执行其功能所需的时间最小化，称为IC延迟。为了设计电路以满足给定的一组要求，必须分析电路的每个信号路径。由于大量的单元和复杂的连接，路径数量非常多，需要很多计算能力进行分析。此外，一些路径对于芯片的操作的目的不重要，并且可以在分析过程期间被折扣。本发明公开了一种用于避免分析非重要路径的方法和装置，被称为定向定时图的假路径。为了避免错误路径，修改表示电路的时序图，以排除图表分析之前的虚假路径。为了修改时序图，构造了重复的节点，构建了重复的边，原始图的一些边被剪切，并将不重复的节点连接到重复节点的混合边替换。最后，创建混合边以将重复节点连接到非重复节点，将重复图与原始图集成。

64. 发明授权

US06247167B1 Method and apparatus for parallel Steiner tree routing 失效
标题翻译：并行Steiner树路由的方法和装置
公开(公告)号：US06247167B1
公开(公告)日：2001-06-12
申请号：US09062432
申请日：1998-04-17
申请人： Pedja Raspopovic , Ranko Scepanovic , Alexander E. Andreev
发明人： Pedja Raspopovic , Ranko Scepanovic , Alexander E. Andreev
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： The present invention provides for a method and apparatus to partition high fanout nets into smaller subnets. Said method includes the steps of identifying elementary pairs of pins in the net, each such elementary pair defining a line; eliminating lines such that a planar graph is formed; eliminating further lines such that a spanning tree is formed, said spanning tree connecting each pin in the net; identifying basic elements, each basic element forming a portion of said spanning tree; and constructing a connected cover for said net, said connected cover comprising a plurality of said basic elements.
摘要翻译：本发明提供了一种将高扇出网分成较小子网的方法和装置。所述方法包括以下步骤：识别网中的基本对引脚，每个这样的基本对定义一条线; 消除形成平面图形的线条; 消除形成生成树的更多的线，所述生成树连接网中的每个引脚; 识别基本元素，形成所述生成树的一部分的每个基本元素; 以及构建所述网的连接的盖，所述连接的盖包括多个所述基本元件。

65. 发明授权

US06175950B1 Method and apparatus for hierarchical global routing descend 失效
标题翻译：分级全局路由下降的方法和装置
公开(公告)号：US06175950B1
公开(公告)日：2001-01-16
申请号：US09062217
申请日：1998-04-17
申请人： Ranko Scepanovic , Alexander E. Andreev , Elyar E. Gasanov , Pedja Raspopovic
发明人： Ranko Scepanovic , Alexander E. Andreev , Elyar E. Gasanov , Pedja Raspopovic
IPC分类号： G06F1750
CPC分类号： G06F17/5077
摘要： Net routing is optimized in an integrated circuit device by dividing an integrated circuit design with a first group of substantially parallel lines in a first direction and with a group of substantially parallel lines in a second direction, with the second direction being substantially perpendicular to the first direction. A first routing graph is formed with vertices corresponding to locations where lines in the first direction and lines in the second direction cross, and nets are globally routed as a function of the first routing graph. The integrated circuit design is further subdivided with a second group of substantially parallel lines in the first direction, and a second routing graph is formed with vertices corresponding to locations where lines in the first and second groups of substantially parallel lines in the first direction cross lines in the group of substantially parallel lines in the second direction. For a net globally routed using the first routing graph, a first local net is formed in a first fragment of the second routing graph, and the first local net is rerouted within the first fragment by computing edge penalty values for edges in the first fragment and rerouting the first local net as a function of the edge penalty values.
摘要翻译：通过将集成电路设计与第一方向上的第一组基本上平行的线分隔开并且在第二方向上与一组基本上平行的线分开，使得第二方向基本上垂直于第一方向方向。第一路由图形成为与第一方向上的线和第二方向上的线交叉的位置相对应的顶点，并且网络作为第一路由图的函数被全局路由。集成电路设计在第一方向上被进一步细分为第二组基本上平行的线，并且第二路由图形成为与第一方向交叉线上的基本上平行的第一组和第二组中的线对应的顶点在第二方向上基本平行的线组。对于使用第一路由图全局路由的网络，在第二路由图的第一片段中形成第一本地网，并且通过计算第一片段中的边缘的边缘惩罚值，在第一片段内重新路由第一本地网，作为边缘惩罚值的函数重新路由第一个本地网络。

66. 发明授权

US6068662A Method and apparatus for congestion removal 失效
标题翻译：阻塞消除的方法和装置
公开(公告)号：US6068662A
公开(公告)日：2000-05-30
申请号：US906945
申请日：1997-08-06
申请人： Ranko Scepanovic , Alexander E. Andreev , Ivan Pavisic
发明人： Ranko Scepanovic , Alexander E. Andreev , Ivan Pavisic
IPC分类号： G06F17/50 , G06F19/00
CPC分类号： G06F17/5072
摘要： Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Because of the large number of the cells and the complex connections required, it is essential that placement of the cell and the wire routine be done correctly to avoid any congestion of wires. The present invention discloses method and apparatus to reduce or to eliminate cell placement and wire routing congestion. The congestion reduction is achieved by first examining regions of the IC to determine whether horizontal or vertical congestion exists. If horizontal congestion exists, then the cells are moved, within the columns, vertically to give more room for the cells and in between the cells for the routing of the wires. If vertical congestion exists, then the cells are moved to different columns to alleviate congestion. The present invention discloses techniques of determining horizontal and vertical congestion and the techniques for moving the cells. The movement of the cells to other columns may create overlapping of the cells or overloading of the columns. The present invention also discloses the methods to resolve the overlapping and overloading problems.
摘要翻译：集成电路芯片（IC）需要适当放置许多单元（电路组件组）和复杂的导线布线以连接单元的引脚。由于需要大量的单元和复杂的连接，所以必须正确地进行单元和电线程序的布置，以避免导线堵塞。本发明公开了减少或消除小区布置和布线拥塞的方法和装置。通过首先检查IC的区域以确定是否存在水平或垂直拥塞来实现拥塞减少。如果存在水平拥堵，那么单元在列内垂直移动，为单元格提供更多的空间，并且在单元之间用于导线的布线。如果存在垂直拥塞，则将小区移动到不同的列以减轻拥塞。本发明公开了确定水平和垂直拥塞的技术以及移动小区的技术。细胞到其他柱的运动可能造成细胞重叠或柱的重载。本发明还公开了解决重叠和重载问题的方法。

67. 发明授权

US5930500A Parallel processor implementation of net routing 失效
标题翻译：并行处理器实现网络路由
公开(公告)号：US5930500A
公开(公告)日：1999-07-27
申请号：US798880
申请日：1997-02-11
申请人： Ranko Scepanovic , Edwin Jones , Alexander E. Andreev
发明人： Ranko Scepanovic , Edwin Jones , Alexander E. Andreev
IPC分类号： G06F17/50
CPC分类号： G06F17/5077
摘要： A method for maximizing effectiveness of parallel processing, using multiple processors, to connect pins of a net of an integrated circuit is disclosed. The method requires the pins to be partitioned into sets of pins and the sets of pins to be further partitioned into meta-sets of the sets of pins. The sets and the meta-sets are connected using a minimal spanning tree algorithm, and the connected sets are made to share a pin, thereby ensuring that the whole net is interconnected without creating a loop in the routing. In addition, because the partitions and the sets of partitions average approximately the same number of pins, the work load can easily be balanced between the processors.
摘要翻译：公开了一种使多个处理器并联处理的有效性最大化的方法来连接集成电路网的引脚。该方法需要将引脚分成一组引脚，并且该引脚组进一步划分成该组引脚的元组。使用最小生成树算法连接集合和元集，并且使连接的集合共享引脚，从而确保整个网络互连而不在路由中创建环路。另外，由于分区和分区的平均数大致相同，所以处理器之间可以容易地平衡工作负载。

68. 发明授权

US08132075B2 Memory mapping for parallel turbo decoding 失效
标题翻译：并行turbo解码的内存映射
公开(公告)号：US08132075B2
公开(公告)日：2012-03-06
申请号：US11924385
申请日：2007-10-25
申请人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
发明人： Alexander E. Andreev , Anatoli A. Bolotov , Ranko Scepanovic
IPC分类号： H03M13/00
CPC分类号： H03M13/2771 , H03M13/2764 , H03M13/2957
摘要： A routing multiplexer system provides p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply signals at the two inputs to the two outputs in a direct or transposed order based on a value of a bit at the control input. A first p/2 group of the modules are coupled to the n inputs and a second p/2 group of the modules provide the n outputs. A plurality of control bit tables each contains a plurality of bits in an arrangement based on a respective permutation. The memory is responsive to a selected permutation to supply bits to the respective modules based on respective bit values of a respective control bit table, thereby establishing a selected and programmable permutation of the inputs to the outputs.
摘要翻译：路由复用器系统基于所选择的p个输入的排列来提供p个输出。多个模块中的每一个具有两个输入，两个输出和一个控制输入，并且被布置为基于控制输入处的位的值，以直接或转置的顺序将两个输入端的信号提供给两个输出。模块的第一个p / 2组耦合到n个输入端，第二个p / 2组模块提供n个输出。多个控制位表各自包含基于相应置换的布置中的多个位。存储器响应于所选择的置换，以基于相应控制位表的相应位值向相应模块提供位，由此建立对输出的输入的选择和可编程排列。

69. 发明授权

US07472358B2 Method and system for outputting a sequence of commands and data described by a flowchart 有权
标题翻译：用于输出由流程图描述的命令和数据序列的方法和系统
公开(公告)号：US07472358B2
公开(公告)日：2008-12-30
申请号：US11260517
申请日：2005-10-27
申请人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
发明人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F17/50
CPC分类号： G06F8/66
摘要： The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. The method includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A processor is generated to include the ROM, wherein the processor receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.
摘要翻译：本发明是用于输出由流程图描述的命令和数据序列的方法和系统。该方法包括以下步骤。接收描述命令和数据序列的流程图。流程图包括多个流程图符号。多个流程图符号中的每一个被分配有ROM（只读存储器）记录。分配的ROM记录存储在ROM中。产生处理器以包括ROM，其中处理器接收CLOCK信号作为输入，RESET信号，ENABLE信号和N个二进制输入x1，x2，...。。。 xN，并输出命令和数据的顺序。

70. 发明授权

US07315993B2 Verification of RRAM tiling netlist 失效
标题翻译：验证RRAM平铺网表
公开(公告)号：US07315993B2
公开(公告)日：2008-01-01
申请号：US10999468
申请日：2004-11-30
申请人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
发明人： Andrey A. Nikitin , Alexander E. Andreev , Ranko Scepanovic
IPC分类号： G06F9/45 , G06F17/50 , G06F11/00 , G11C29/00
CPC分类号： G06F17/5022
摘要： The present invention provides a method of verification of a RRAM tiling netlist. The method may include steps as follows. Properties “memory_number”, “clock_number” and “netlist_part” of all nets and cells of a RRAM tiling netlist are set to a value 0. A boolean value 0 is assigned to all ground nets of the RRAM tiling netlist, and a boolean value 1 is assigned to all power nets of the RRAM tiling netlist. The RRAM tiling netlist is verified for each customer memory Memk, k=1, 2, . . . , N.
摘要翻译：本发明提供了一种RRAM拼接网表的验证方法。该方法可以包括以下步骤。属性RRAM平铺网表的所有网络和单元格的“memory_number”，“clock_number”和“netlist_part”被设置为0.值为0的布尔值分配给RRAM平铺网表的所有地网，布尔值1 被分配给RRAM平铺网表的所有电网。对于每个客户存储器验证RRAM平铺网表，其中k = 1,2，...。。。，N.

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