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61. 发明申请

US20100218050A1 Parking Structure Memory-Module Tester that Moves Test Motherboards Along a Highway for Remote Loading/Unloading 有权
标题翻译：停车结构记忆模块测试仪，沿高速公路移动测试主板用于远程装载/卸载
公开(公告)号：US20100218050A1
公开(公告)日：2010-08-26
申请号：US12392401
申请日：2009-02-25
申请人： Ramon S. Co , Kevin J. Sun
发明人： Ramon S. Co , Kevin J. Sun
IPC分类号： G06F11/273
CPC分类号： G11C29/56 , G11C29/56016
摘要： A parking-structure test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. An unloader removes tested memory modules from test sockets on the motherboards, and a loader inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader to a parking and testing structure. An elevator raises or lowers the motherboards to different parking levels in the parking and testing structure. The motherboards move from the elevator to test stations on the parking level. A retractable connector from the test station makes contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns via the elevator and conveyors.
摘要翻译：停车结构测试系统具有测试内存模块的主板。主板不是静止的，而是位于沿传送带移动的活动托盘内。卸载器从主板上的测试插槽中删除测试的内存模块，并且加载器使用机械臂将未测试的内存模块插入主板。输送机将主板从装载机运送到停车和测试结构。电梯将主板升高或降低到停车和测试结构中的不同停车位。主板从电梯移动到停车位的测试站。来自测试台的可伸缩连接器与母板连接器接触，为主板供电，然后测试内存模块。测试结果从测试台传送到主机控制器，主机控制器指示装载机卸载机在主板通过电梯和输送机返回后对被测试的存储器模块进行排序。

62. 发明授权

US07688929B2 All-digital phase modulator/demodulator using multi-phase clocks and digital PLL 有权
标题翻译：全数字相位调制器/解调器采用多相时钟和数字PLL
公开(公告)号：US07688929B2
公开(公告)日：2010-03-30
申请号：US11692472
申请日：2007-03-28
申请人： Ramon S. Co
发明人： Ramon S. Co
IPC分类号： H03D3/24
CPC分类号： H03L7/0814 , H03C3/0966 , H03L2207/50 , H04L27/22
摘要： Multi-phase clocks are used to encode and decode signals that are phase-modulated. The input signal is phase-compared with a feedback clock. Phase differences increment or decrement an up/down counter. The count value from the up/down counter is applied to a phase rotator, which selects one clock phase from a bank of multi-phase clocks. The multi-phase clocks have the same frequency, but are offset in phase from each other. An output divider divides the selected multi-phase clock to generate a phase-modulated output. A feedback divider divides a fixed-phase clock from the multi-phase clocks to generate the feedback clock. An analog or a digital front-end may be used to convert analog inputs to digital signals to increment or decrement the counter, or to encode multiple digital bits as phase assignments. For a de-modulator, a digital-to-analog converter (DAC) or a digital decoder produces the final output from the count of the up/down counter.
摘要翻译：多相时钟用于对相位调制的信号进行编码和解码。输入信号与反馈时钟进行相位比较。相位差递增或递减上/下计数器。来自递增/递减计数器的计数值被应用于从一组多相时钟选择一个时钟相位的相位旋转器。多相时钟具有相同的频率，但彼此相位偏移。输出分频器分频所选择的多相时钟以产生相位调制输出。反馈分频器将固定相位时钟与多相时钟分频，以产生反馈时钟。模拟或数字前端可以用于将模拟输入转换为数字信号，以递增或递减计数器，或将多个数字位编码为相位分配。对于解调器，数/模转换器（DAC）或数字解码器从上/下计数器的计数产生最终输出。

63. 发明授权

US07477526B1 Branching fully-buffered memory-module with two downlink and one uplink ports 有权
标题翻译：分支具有两个下行链路和一个上行链路端口的全缓冲内存模块
公开(公告)号：US07477526B1
公开(公告)日：2009-01-13
申请号：US11306481
申请日：2005-12-29
申请人： Ramon S. Co
发明人： Ramon S. Co
IPC分类号： H05K1/11
CPC分类号： G11C5/04
摘要： A branching fully-buffered memory module has one uplink port and two downlink ports. Frames sent downstream by a host processor are received on the uplink port and repeated to the two downlink ports to two branches of memory modules. Frames sent upstream to the processor by a memory module on a downlink port are repeated to the uplink port. A branching Advanced Memory Buffer (AMB) on the branching memory module has re-timing and re-synchronizing buffers that repeat frames to the two downlink ports. Separate northbound and southbound lanes may be replaced by bidirectional lanes to reduce pin count. Sync patterns are added to the start of frames to detect any collisions on bidirectional lines. Point-to-point bus segments have only two endpoints despite branching by the branching AMB. Latency from the host processor to the last memory module is reduced by branching compared with a serial daisy-chain of memory modules.
摘要翻译：分支全缓冲存储器模块具有一个上行链路端口和两个下行链路端口。在主机处理器发送的下游发送的帧在上行链路端口上被接收并重复到两个下行链路端口到存储器模块的两个分支。通过下行链路端口上的存储器模块向处理器上行发送的帧被重复到上行链路端口。分支存储器模块上的分支高级存储器缓冲器（AMB）具有对两个下行链路端口重复帧的重新定时和重新同步缓冲器。分开的北行和南行车道可能会被双向通道取代，以减少针数。同步模式被添加到帧的开始，以检测双向线路上的任何冲突。点对点总线段只有两个端点，尽管分支AMB分支。与内存模块的串行菊花链相比，从主处理器到最后一个内存模块的延迟减少了。

64. 发明授权

US5652531A Phase detector which eliminates frequency ripple 失效
标题翻译：消除频率纹波的相位检测器
公开(公告)号：US5652531A
公开(公告)日：1997-07-29
申请号：US642335
申请日：1996-05-03
申请人： Ramon S. Co , Richard L. Traber
发明人： Ramon S. Co , Richard L. Traber
IPC分类号： H03L7/089 , H04L7/033 , H03K5/22 , H03K5/26
CPC分类号： H04L7/033 , H03L7/089
摘要： A phase detector is disclosed that eliminates frequency ripple in a phase-locked loop circuit. The detector includes first and second circuits for providing UP and DOWN signals respectively. It also includes a delay element for setting the duration of the DOWN signal so as to eliminate phase jitter and static phase offset.
摘要翻译：公开了消除锁相环电路中的频率纹波的相位检测器。检测器包括分别提供UP和DOWN信号的第一和第二电路。它还包括用于设置DOWN信号的持续时间的延迟元件，以消除相位抖动和静态相位偏移。

65. 发明授权

US5491729A Digital phase-locked data recovery circuit 失效
标题翻译：数字锁相数据恢复电路
公开(公告)号：US5491729A
公开(公告)日：1996-02-13
申请号：US337965
申请日：1994-11-14
申请人： Ramon S. Co , Ron Kao
发明人： Ramon S. Co , Ron Kao
IPC分类号： H04L7/033 , H03D3/24
CPC分类号： H04L7/0337
摘要： A digital phase-locked data recovery circuit having improved noise immunity. The data recovery circuit includes a multi-phase clock for supplying clock signals having a predetermined relative phase relationship. A snap shot sampling network takes samples of an input data signal in response to the multi-phase clock signals. The samples are preferably collected during the duration of boundary sampling windows encompassing transitions in the input data signal. The present invention further includes a network for comparing the received data samples with a sample pattern. A phase encoder then generates error signals in response to the phase comparisons. A phase decoder adjusts the phase of the boundary window in response to the error signal.
摘要翻译：一种数字锁相数据恢复电路，具有改善的抗噪声能力。数据恢复电路包括用于提供具有预定相对相位关系的时钟信号的多相时钟。快拍采样网络响应于多相时钟信号来采样输入数据信号。优选地，在包含输入数据信号中的转换的边界采样窗口的持续时间期间收集样本。本发明还包括一个网络，用于将接收到的数据样本与样本模式进行比较。然后，相位编码器响应于相位比较产生误差信号。相位解码器响应于误差信号来调整边界窗口的相位。

66. 发明授权

US5436934A Differential high frequency level detector and data restoration circuit including squelch offset and slicing offset 失效
标题翻译：差分高频电平检测器和数据恢复电路包括静噪偏移和切片偏移
公开(公告)号：US5436934A
公开(公告)日：1995-07-25
申请号：US897277
申请日：1992-08-13
申请人： Ramon S. Co
发明人： Ramon S. Co
IPC分类号： H04B1/10
CPC分类号： H04B1/1027
摘要： An improved circuit topology for implementing level detection and data restoration operations on an input sinusoid. The differential high-frequency level detector and data restoration circuits of the present invention each include a differential input having a pair of circuit nodes for receiving a differential input signal. A slicing offset network is disposed to generate first and second differential signals in response to the differential input signal. The present invention further includes first and second comparators for respectively providing latch set and latch reset signals in response to the first and second offset differential signals. The data restoration circuit of the present invention further includes a latch operative to synthesize a recovered data waveform in accordance with pairs of set and reset signals. Similarly, the inventive level detector includes a latch which utilizes set and reset signals to generate a level detection signal.
摘要翻译：一种改进的电路拓扑，用于在输入正弦波上实现电平检测和数据恢复操作。本发明的差分高频电平检测器和数据恢复电路各自包括具有用于接收差分输入信号的一对电路节点的差分输入。设置切片偏移网络以响应于差分输入信号产生第一和第二差分信号。本发明还包括第一和第二比较器，用于响应于第一和第二偏移差分信号分别提供锁存器组和锁存复位信号。本发明的数据恢复电路还包括一个可操作以根据设定和复位信号对合成恢复的数据波形的锁存器。类似地，本发明的电平检测器包括利用设置和复位信号产生电平检测信号的锁存器。

67. 发明申请

US20130088829A1 Low-Profile Motherboard with Side-Mounted Memory Modules Using a Dual-Opening Edge Connector 有权
标题翻译：带有侧面安装内存模块的小型主板，采用双开口边缘连接器
公开(公告)号：US20130088829A1
公开(公告)日：2013-04-11
申请号：US13269526
申请日：2011-10-07
申请人： Ramon S. Co
发明人： Ramon S. Co
IPC分类号： G06F1/16
CPC分类号： G06F1/185
摘要： A low-profile personal computer (PC) motherboard has memory modules mounted to an edge of the motherboard rather than mounted perpendicular using standard memory module sockets. The PC motherboard has a lower profile since memory module sockets are removed from the top surface of the PC motherboard. Expansion card sockets are also removed by integrating expansion functions into chips on the PC motherboard, or using an edge-mounted connector to the expansion card or to an external peripheral. Motherboard metal contacts are formed on an extended plug region near the edge of the PC motherboard. A first opening or slot of an edge connector fits over the motherboard metal contacts, while a second opening or slot of the edge connector fits over metal contacts on a standard memory module. The memory module and the PC motherboard each have printed-circuit boards (PCBs) that are in the same plane, thus reducing the overall height.
摘要翻译：一个低调的个人计算机（PC）主板具有安装在主板边缘的内存模块，而不是使用标准内存模块插槽垂直安装。 PC主板具有较低的外形，因为内存模块插座从PC主板的顶面移除。扩展卡插槽也可以通过将扩展功能集成到PC主板上的芯片中，或者使用边缘连接器连接到扩展卡或外部外围设备。主板金属触点形成在靠近PC主板边缘的扩展插头区域上。边缘连接器的第一开口或槽口装配在母板金属触点上，而边缘连接器的第二开口或槽适合标准存储器模块上的金属触点。存储器模块和PC主板各自具有位于同一平面中的印刷电路板（PCB），从而降低了整体高度。

68. 发明申请

US20090217102A1 Fault Diagnosis of Serially-Addressed Memory Chips on a Test Adaptor Board To a Middle Memory-Module Slot on a PC Motherboard 有权
标题翻译：将测试适配器板上的串行内存芯片故障诊断到PC主板上的中间内存模块插槽
公开(公告)号：US20090217102A1
公开(公告)日：2009-08-27
申请号：US12101138
申请日：2008-04-10
申请人： Ramon S. Co
发明人： Ramon S. Co
IPC分类号： G06F11/00
CPC分类号： G11C29/56 , G11C5/04 , G11C29/56008 , G11C29/56016
摘要： A standard memory module socket is removed from a target DRAM module slot on the component side and the test adaptor board connects to the target DRAM module slot on the reverse (solder) side of a personal computer motherboard, or an extender card may be used. The target DRAM module slot is a middle slot, such as the second or third of four DRAM module slots. The first and fourth DRAM module slots are populated with known good memory modules storing the BIOS at a high address and an operating system image and a test program at a low address. The test program accesses a memory chip in a test socket on a test adaptor board that is connected to the target DRAM module slot to locate defects. The motherboard does not crash since the BIOS, OS image, and test program are not stored in the memory chip under test.
摘要翻译：标准内存模块插座从组件侧的目标DRAM模块插槽中移除，测试适配器板连接到个人计算机主板背面（焊接）侧的目标DRAM模块插槽，或者可以使用扩展卡。目标DRAM模块插槽是中间插槽，例如四个DRAM模块插槽的第二或第三。第一和第四DRAM模块插槽用已知的良好存储器模块填充存储在高地址处的BIOS，操作系统映像和低地址处的测试程序。测试程序访问连接到目标DRAM模块插槽的测试适配器板上的测试插座中的存储芯片，以定位缺陷。主板不会崩溃，因为BIOS，OS映像和测试程序未被存储在被测芯片内。

69. 发明授权

US07389381B1 Branching memory-bus module with multiple downlink ports to standard fully-buffered memory modules 有权
标题翻译：将具有多个下行链路端口的内存总线模块分支到标准的全缓冲内存模块
公开(公告)号：US07389381B1
公开(公告)日：2008-06-17
申请号：US11308545
申请日：2006-04-05
申请人： Ramon S. Co
发明人： Ramon S. Co
IPC分类号： G06F13/28
CPC分类号： G06F13/1684 , G06F13/1673 , G11C5/04 , Y02D10/14
摘要： A branching memory-bus module has one uplink port and two or more downlink ports. Frames sent downstream by a host processor are received on the uplink port and repeated to the multiple downlink ports to two or more branches of memory modules. Frames sent upstream to the processor by a memory module on a downlink port are repeated to the uplink port. A branching Advanced Memory Buffer (AMB) on the branching memory-bus module has re-timing and re-synchronizing buffers that repeat frames to the multiple downlink ports. Elastic buffers can merge and synchronize frames from different downlink branches. Separate northbound and southbound lanes may be replaced by bidirectional lanes to reduce pin counts. Latency from the host processor to the farthest memory module is reduced by branching compared with a serial daisy-chain of fully-buffered memory modules. Point-to-point bus segments have only two endpoints despite branching by the branching AMB.
摘要翻译：分支存储器总线模块具有一个上行链路端口和两个或更多个下行链路端口。在主机处理器发送的下游的帧在上行链路端口上被接收并且被重复到多个下行链路端口到存储器模块的两个或更多个分支。通过下行链路端口上的存储器模块向处理器上行发送的帧被重复到上行链路端口。分支存储器总线模块上的分支高级存储器缓冲器（AMB）具有对多个下行链路端口重复帧的重新定时和重新同步缓冲器。弹性缓冲区可以合并和同步来自不同下行链路分支的帧。分开的北行和南行车道可以由双向车道代替，以减少销数。与串行菊花链完全缓冲的内存模块相比，从主处理器到最远的内存模块的延迟减少了。点对点总线段只有两个端点，尽管分支AMB分支。

70. 发明授权

US07029297B1 PC-motherboard test socket with levered handles engaging and pushing memory modules into extender-card socket and actuating ejectors for removal 有权
标题翻译：具有杠杆把手的PC主板测试插座将内存模块插入扩展卡插槽并执行驱动器以进行拆卸
公开(公告)号：US07029297B1
公开(公告)日：2006-04-18
申请号：US10905276
申请日：2004-12-23
申请人： Ramon S. Co , Chin-Piao Kuo
发明人： Ramon S. Co , Chin-Piao Kuo
IPC分类号： H01R11/20
CPC分类号： H01R13/62988 , H01R12/721
摘要： A memory module socket requires a reduced insertion force because a notch engager on a levered handle engages a notch on the memory module and applies downward pressure. The notch engager is forced downward as the levered handle pivots about an axis, causing the downward force to be applied to the notch on a memory module, forcing the memory module into a memory module socket on an extender card that plugs into a memory module socket on a personal computer motherboard. An ejector arm is pushed downward by the levered handle during removal. An ejector foot inside the memory module socket is pivoted upward around an ejector pivot when the ejector arm is pushed downward. The upward pivoting ejector foot pushes upward on the inserted edge of the memory module, forcing the memory module out of the memory module socket. Both ejection and insertion forces can be reduced.
摘要翻译：存储器模块插座需要减小的插入力，因为在杠杆柄上的凹口接合存储器模块上的凹口并施加向下的压力。当杠杆式手柄围绕轴旋转时，槽口接合器被迫向下，导致向下的力施加到存储器模块上的凹口，迫使存储器模块进入插入存储器模块插座的扩展卡上的存储器模块插座在个人电脑主板上。拆卸期间，顶杆手柄被向下推动。当推动器臂被向下推动时，存储器模块插座内的弹射器脚围绕推出器枢轴向上枢转。向上旋转的喷射器脚在存储器模块的插入边缘上向上推动，迫使存储器模块离开存储器模块插槽。弹出和插入力都可以减小。

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