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61. 发明授权

US09653358B2 Semiconductor device structure and method for manufacturing the same 有权
公开(公告)号：US09653358B2
公开(公告)日：2017-05-16
申请号：US13133061
申请日：2011-02-25
申请人： Huicai Zhong , Qingqing Liang
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L21/8234 , H01L21/8238 , H01L27/02 , H01L29/10 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823412 , H01L21/823814 , H01L21/823828 , H01L21/823878 , H01L27/0207 , H01L29/1054 , H01L29/66545 , H01L29/66553 , H01L29/66575 , H01L29/66651 , H01L29/78 , H01L29/7848
摘要： The present invention presents a method for manufacturing a semiconductor device structure as well as the semiconductor device structure. Said method comprises: providing a semiconductor substrate; forming a first insulating layer on the semiconductor substrate; forming a shallow trench isolation embedded in the first insulating layer and the semiconductor substrate; forming a channel region embedded in the semiconductor substrate; and forming a gate stack stripe on the channel region. Said method further comprises, before forming the channel region, performing a source/drain implantation on the semiconductor substrate. By means of forming the source/drain regions in a self-aligned manner before forming the channel region and the gate stack, said method achieves the advantageous effects of the replacement gate process without using a dummy gate, thereby simplifying the process and reducing the cost.

62. 发明授权

US08460988B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US08460988B2
公开(公告)日：2013-06-11
申请号：US13061824
申请日：2010-09-26
申请人： Huicai Zhong , Qingqing Liang
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/3086 , H01L21/76897 , H01L29/41783 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/7843 , H01L29/7848
摘要： A method of manufacturing a semiconductor device is provided, in which after forming a gate stack and a first spacer thereof, a second spacer and a third spacer are formed; and then an opening is formed between the first spacer and the third spacer by removing the second spacer. The range of the formation for the raised active area 220 is limited by forming an opening 214 between the first spacer 208 and the third spacer 212. The raised active area 220 is formed in the opening 214 in a self-aligned manner, so that a better profile of the raised active area 220 may be achieved and the possible shorts between adjacent devices caused by an unlimited manner may be avoided. Moreover, based on such a manufacturing method, it is easy to make the gate electrode 204 to be flushed with the raised active area 220, and is also easy to implement the dual stress nitride process so as to increase the mobility of the device.
摘要翻译：提供一种制造半导体器件的方法，其中在形成栅极堆叠及其第一间隔物之后，形成第二间隔物和第三间隔物; 然后通过移除第二间隔件在第一间隔件和第三间隔件之间形成开口。通过在第一间隔件208和第三间隔件212之间形成开口214来限制凸起的有效区域220的形成范围。凸起的有源区域220以自对准的方式形成在开口214中，使得可以实现凸起的有效区域220的更好的轮廓，并且可以避免由无限制的方式引起的相邻设备之间的可能的短路。此外，基于这样的制造方法，可以容易地利用凸起的有源区域220冲洗栅电极204，并且也容易实施双应力氮化物工艺，以增加器件的移动性。

63. 发明申请

US20120223398A1 METHOD FOR MANUFACTURING CONTACT AND SEMICONDUCTOR DEVICE HAVING SAID CONTACT 有权
标题翻译：制造接触器的方法和具有接触的半导体器件
公开(公告)号：US20120223398A1
公开(公告)日：2012-09-06
申请号：US13144887
申请日：2011-02-27
申请人： Huicai Zhong , Qingqing Liang
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L29/78 , H01L21/768
CPC分类号： H01L21/76816 , H01L21/76877 , H01L21/823475 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a method for manufacturing a contact and a semiconductor device having said contact. The present invention proposes to form first a trench contract of relatively large size, then to form one or more dielectric layer(s) within the trench contact, and then to remove the upper part of the dielectric layer(s) and to fill the same with a conductive material. The use of such a method makes it easy to form a trench contact of relatively large size which is easy for manufacturing; besides, since dielectric layer(s) is/are formed in the trench contact, thence capacitance between a source/drain trench contact and a gate electrode is reduced accordingly.
摘要翻译：本发明涉及一种用于制造接触的方法和具有所述接触的半导体器件。本发明提出首先形成相对大尺寸的沟槽接合，然后在沟槽接触中形成一个或多个电介质层，然后去除电介质层的上部并填充相同的电介质层与导电材料。使用这种方法可以容易地形成容易制造的较大尺寸的沟槽接触; 此外，由于在沟槽接触中形成介电层，所以源极/漏极沟槽接触和栅电极之间的电容相应地减小。

64. 发明申请

US20120187497A1 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件结构及其制造方法
公开(公告)号：US20120187497A1
公开(公告)日：2012-07-26
申请号：US13380975
申请日：2011-02-27
申请人： Huicai Zhong , Qingqing Liang
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L27/0207 , H01L21/823437 , H01L21/823475 , H01L27/092 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： The present invention proposes a semiconductor device structure and a method for manufacturing the same, and relates to the semiconductor manufacturing industry. The method comprises: providing a semiconductor substrate; forming gate electrode lines on the semiconductor substrate; forming sidewall spacers on both sides of the gate electrode lines; forming source/drain regions on the semiconductor substrates at both sides of the gate electrode lines; forming contact holes on the gate electrode lines or on the source/drain regions; and cutting off the gate electrode lines to form electrically isolated gate electrodes after formation of the sidewall spacers but before completion of FEOL process for a semiconductor device structure. The embodiments of the present invention are applicable for manufacturing integrated circuits.
摘要翻译：本发明提出一种半导体器件结构及其制造方法，涉及半导体制造业。该方法包括：提供半导体衬底; 在半导体衬底上形成栅电极线; 在栅电极线的两侧形成侧壁间隔物; 在栅极电极线的两侧在半导体基板上形成源极/漏极区域; 在栅电极线或源极/漏极区上形成接触孔; 并且在形成侧壁间隔物之后但在用于半导体器件结构的FEOL处理完成之前，切断栅电极线以形成电隔离的栅电极。本发明的实施例可用于制造集成电路。

65. 发明申请

US20120132923A1 SUBSTRATE FOR INTEGRATED CIRCUIT AND METHOD FOR FORMING THE SAME 有权
标题翻译：用于集成电路的基板及其形成方法
公开(公告)号：US20120132923A1
公开(公告)日：2012-05-31
申请号：US13159351
申请日：2011-06-13
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Zhijiong Luo
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin , Zhijiong Luo
IPC分类号： H01L29/161 , H01L29/20 , H01L21/76
CPC分类号： H01L21/76232 , H01L21/7624 , H01L21/76283
摘要： The present invention relates to substrates for ICs and method for forming the same. The method comprises the steps of: forming a hard mask layer on the bulk silicon material; etching the hard mask layer and the bulk silicon material to form a first part for shallow trench isolation of at least one trench; forming a dielectric film on the sidewall of the at least one trench; further etching the bulk silicon material to deepen the at least one trench so as to form a second part of the at least one trench; completely oxidizing or nitridizing parts of the bulk silicon material which are between the second parts of the trenches, and parts of the bulk silicon material which are between the second parts of the trenches and side surfaces of the bulk silicon substrate; filling dielectric materials in the first and second parts of the at least one trench; and removing the hard mask layer.
摘要翻译：本发明涉及IC的基板及其制造方法。该方法包括以下步骤：在体硅材料上形成硬掩模层; 蚀刻硬掩模层和体硅材料以形成用于至少一个沟槽的浅沟槽隔离的第一部分; 在所述至少一个沟槽的侧壁上形成电介质膜; 进一步蚀刻体硅材料以加深所述至少一个沟槽，以便形成所述至少一个沟槽的第二部分; 在沟槽的第二部分之间的体硅材料的部分和沟槽的第二部分和体硅衬底的侧表面之间的体硅材料的部分完全氧化或氮化; 在所述至少一个沟槽的第一和第二部分中填充介电材料; 并除去硬掩模层。

66. 发明申请

US20120126245A1 SHALLOW TRENCH ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译：浅层分离结构及其形成方法
公开(公告)号：US20120126245A1
公开(公告)日：2012-05-24
申请号：US13132068
申请日：2011-01-27
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin
IPC分类号： H01L21/762 , H01L29/12 , H01L29/06 , H01L29/16 , B82Y40/00 , B82Y99/00
CPC分类号： H01L21/76232
摘要： The invention provides a STI structure and method for forming the same. The STI structure includes a semiconductor substrate; a first trench embedded in the semiconductor substrate and filled up with a first dielectric layer; and a second trench formed on a top surface of the semiconductor substrate and interconnected with the first trench, wherein the second trench is filled up with a second dielectric layer, a top surface of the second dielectric layer is flushed with that of the semiconductor substrate, and the second trench has a width smaller than that of the first trench. The invention reduces dimension of divots and improves performance of the semiconductor device.
摘要翻译：本发明提供一种STI结构及其形成方法。 STI结构包括半导体衬底; 第一沟槽，其嵌入在所述半导体衬底中并填充有第一介电层; 以及形成在所述半导体衬底的顶表面上并与所述第一沟槽互连的第二沟槽，其中所述第二沟槽填充有第二介电层，所述第二介电层的顶表面与所述半导体衬底的顶表面冲洗，并且所述第二沟槽的宽度小于所述第一沟槽的宽度。本发明减小了图形的尺寸并提高了半导体器件的性能。

67. 发明申请

US20120025317A1 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FABRICATING THE SAME 有权
标题翻译：半导体器件结构及其制造方法
公开(公告)号：US20120025317A1
公开(公告)日：2012-02-02
申请号：US13003969
申请日：2010-09-27
申请人： Huicai Zhong , Qingqing Liang , Haizhou Yin
发明人： Huicai Zhong , Qingqing Liang , Haizhou Yin
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/4983 , H01L21/76897 , H01L21/823437 , H01L21/823475 , H01L27/0207 , H01L27/088 , H01L29/66545 , H01L29/78
摘要： A semiconductor device structure and a method for fabricating the same. A method for fabricating semiconductor device structure includes forming gate lines on a semiconductor substrate; forming gate sidewall spacers surrounding the gate lines; forming respective source/drain regions in the semiconductor substrate and on either side of the respective gate lines; forming conductive sidewall spacers surrounding the gate sidewall spacers; and cutting off the gate lines, the gate sidewall spacers and the conductive sidewall spacers at predetermined positions, in which the cut gate lines are electrically isolated gates, and the cut conductive sidewall spacers are electrically isolated lower contacts. The method is applicable to the manufacture of contacts in integrated circuits.
摘要翻译：一种半导体器件结构及其制造方法。一种制造半导体器件结构的方法包括在半导体衬底上形成栅极线; 形成围绕所述栅极线的栅极侧壁间隔物; 在半导体衬底中和各个栅极线的任一侧上形成相应的源/漏区; 形成围绕所述栅极侧壁间隔物的导电侧壁间隔物并且在切割栅极线是电隔离栅极的预定位置处切断栅极线，栅极侧壁间隔物和导电侧壁间隔物，并且切割的导电侧壁间隔物是电隔离的下部触点。该方法适用于集成电路中触点的制造。

68. 发明申请

US20110298053A1 MANUFACTURING METHOD OF GATE STACK AND SEMICONDUCTOR DEVICE 有权
标题翻译：栅极堆叠和半导体器件的制造方法
公开(公告)号：US20110298053A1
公开(公告)日：2011-12-08
申请号：US12997625
申请日：2010-09-19
申请人： Huicai Zhong , Zhijiong Luo , Qingqing Liang
发明人： Huicai Zhong , Zhijiong Luo , Qingqing Liang
IPC分类号： H01L29/78 , H01L21/3205 , B82Y40/00 , B82Y99/00
CPC分类号： H01L29/513 , H01L21/28176 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/78
摘要： A manufacturing method of a gate stack with sacrificial oxygen-scavenging metal spacers includes: forming a gate stack structure consisting of an interfacial oxide layer, a high-K dielectric layer and a metal gate electrode, on a semiconductor substrate; conformally depositing a metal layer covering the semiconductor substrate and the gate stack structure; and selectively etching the metal layer to remove the portions of the metal layer covering the top surface of the gate stack structure and the semiconductor substrate, so as to only keep the sacrificial oxygen-scavenging metal spacers surrounding the gate stack structure in the outer periphery of the gate stack structure. A semiconductor device manufactured by this process.
摘要翻译：具有牺牲氧清除金属间隔物的栅极堆叠的制造方法包括：在半导体衬底上形成由界面氧化物层，高K电介质层和金属栅电极组成的栅叠层结构; 保形地沉积覆盖半导体衬底和栅极堆叠结构的金属层; 并且选择性地蚀刻金属层以去除覆盖栅极堆叠结构和半导体衬底的顶表面的金属层的部分，以便仅将围绕栅极堆叠结构的牺牲氧清除金属间隔物保持在外部周边门堆栈结构。通过该方法制造的半导体器件。

69. 发明授权

US09425288B2 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09425288B2
公开(公告)日：2016-08-23
申请号：US14412237
申请日：2012-07-18
申请人： Huicai Zhong , Qingqing Liang , Chao Zhao
发明人： Huicai Zhong , Qingqing Liang , Chao Zhao
IPC分类号： H01L29/66
CPC分类号： H01L29/66795 , H01L21/268 , H01L21/76283 , H01L29/665 , H01L29/785
摘要： A method of manufacturing a FinFET semiconductor device is provided, wherein the semiconductor fins are formed in a parallel arrangement which intersects the gates arranged in parallel. The polycrystalline silicon layer is deposited and then converted into a single crystal silicon layer such that the single crystal silicon layer and the semiconductor fins are integrated in essence, i.e., the source/drain region in the semiconductor fins is raised and the top area of the semiconductor fins is extended. Subsequently, the single crystal silicon layer above the top of the semiconductor fins is converted into a metal silicide so as to form a source/drain region contact. The source/drain region contact in the present invention has a larger area than that in a conventional FinFET, which decreases the contact resistance and facilitates the formation of a self-aligned metal plug in the follow-up process.
摘要翻译：提供一种制造FinFET半导体器件的方法，其中半导体鳍片形成为与并行布置的栅极相交的平行布置。沉积多晶硅层，然后转换为单晶硅层，使得单晶硅层和半导体鳍片本质上是集成的，即半导体鳍片中的源极/漏极区域被升高，并且顶部区域半导体鳍片延伸。随后，将半导体鳍片顶部上方的单晶硅层转换为金属硅化物，以形成源/漏区接触。本发明中的源极/漏极区域的接触面积大于传统的FinFET的面积，这在以后的过程中降低了接触电阻并且有利于形成自对准的金属插塞。

70. 发明授权

US08716095B2 Manufacturing method of gate stack and semiconductor device 有权
标题翻译：栅极堆叠和半导体器件的制造方法
公开(公告)号：US08716095B2
公开(公告)日：2014-05-06
申请号：US12997625
申请日：2010-09-19
申请人： Huicai Zhong , Zhijiong Luo , Qingqing Liang
发明人： Huicai Zhong , Zhijiong Luo , Qingqing Liang
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/513 , H01L21/28176 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/78
摘要： A manufacturing method of a gate stack with sacrificial oxygen-scavenging metal spacers includes: forming a gate stack structure consisting of an interfacial oxide layer, a high-K dielectric layer and a metal gate electrode, on a semiconductor substrate; conformally depositing a metal layer covering the semiconductor substrate and the gate stack structure; and selectively etching the metal layer to remove the portions of the metal layer covering the top surface of the gate stack structure and the semiconductor substrate, so as to only keep the sacrificial oxygen-scavenging metal spacers surrounding the gate stack structure in the outer periphery of the gate stack structure. A semiconductor device manufactured by this process.
摘要翻译：具有牺牲氧清除金属间隔物的栅极堆叠的制造方法包括：在半导体衬底上形成由界面氧化物层，高K电介质层和金属栅电极组成的栅叠层结构; 保形地沉积覆盖半导体衬底和栅极堆叠结构的金属层; 并且选择性地蚀刻金属层以去除覆盖栅极堆叠结构和半导体衬底的顶表面的金属层的部分，以便仅将围绕栅极堆叠结构的牺牲氧清除金属间隔物保持在外部周边门堆栈结构。通过该方法制造的半导体器件。

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