专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US08637371B2 Non-planar MOSFET structures with asymmetric recessed source drains and methods for making the same 有权
标题翻译：具有非对称凹陷源漏极的非平面MOSFET结构及其制造方法
公开(公告)号：US08637371B2
公开(公告)日：2014-01-28
申请号：US13398339
申请日：2012-02-16
申请人： Josephine B Chang , Paul Chang , Michael A Guillorn , Chung-hsun Lin , Jeffrey W Sleight
发明人： Josephine B Chang , Paul Chang , Michael A Guillorn , Chung-hsun Lin , Jeffrey W Sleight
IPC分类号： H01L21/336
CPC分类号： H01L29/66545 , H01L29/0657 , H01L29/66795
摘要： Non-planar Metal Oxide Field Effect Transistors (MOSFETs) and methods for making non-planar MOSFETs with asymmetric, recessed source and drains having improved extrinsic resistance and fringing capacitance. The methods include a fin-last, replacement gate process to form the non-planar MOSFETs and employ a retrograde metal lift-off process to form the asymmetric source/drain recesses. The lift-off process creates one recess which is off-set from a gate structure while a second recess is aligned with the structure. Thus, source/drain asymmetry is achieved by the physical structure of the source/drains, and not merely by ion implantation. The resulting non-planar device has a first channel of a fin contacting a substantially undoped area on the drain side and a doped area on the source side, thus the first channel is asymmetric. A channel on atop surface of a fin is symmetric because it contacts doped areas on both the drain and source sides.
摘要翻译：非平面金属氧化物场效应晶体管（MOSFET）和用于制造具有改进的外在电阻和边缘电容的具有不对称，凹陷源极和漏极的非平面MOSFET的方法。这些方法包括最后一个替代栅极工艺，以形成非平面MOSFET并且采用逆向金属剥离工艺来形成不对称的源极/漏极凹槽。剥离过程产生一个从门结构偏离的凹槽，而第二凹槽与结构对准。因此，源/漏不对称性通过源极/漏极的物理结构实现，而不仅仅是通过离子注入来实现。所得到的非平面器件具有接触漏极侧的基本上未掺杂的区域和源极侧的掺杂区域的翅片的第一通道，因此第一通道是不对称的。鳍的顶表面上的通道是对称的，因为它接触漏极和源极侧上的掺杂区域。

62. 发明授权

US08586449B1 Raised isolation structure self-aligned to fin structures 有权
标题翻译：升高的隔离结构自对准鳍结构
公开(公告)号：US08586449B1
公开(公告)日：2013-11-19
申请号：US13603872
申请日：2012-09-05
申请人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Effendi Leobandung
发明人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Effendi Leobandung
IPC分类号： H01L21/76
CPC分类号： H01L21/845 , H01L21/76229
摘要： Raised isolation structures can be formed at the same level as semiconductor fins over an insulator layer. A template material layer can be conformally deposited to fill the gaps among the semiconductor fins within each cluster of semiconductor fins on an insulator layer, while the space between adjacent clusters is not filled. After an anisotropic etch, discrete template material portions can be formed within each cluster region, while the buried insulator is physically exposed between cluster regions. A raised isolation dielectric layer is deposited and planarized to form raised isolation structures employing the template material portions as stopping structures. After removal of the template material portions, a cluster of semiconductor fins are located within a trench that is self-aligned to outer edges of the cluster of semiconductor fins. The trench can be employed to confine raised source/drain regions to be formed on the cluster of semiconductor fins.
摘要翻译：升高的隔离结构可以在与绝缘体层上的半导体鳍片相同的水平上形成。可以共形沉积模板材料层以填充绝缘体层上的每个半导体翅片簇内的半导体鳍片之间的间隙，而相邻簇之间的空间未被填充。在各向异性蚀刻之后，可以在每个簇区域内形成离散的模板材料部分，而埋入的绝缘体在簇区域之间物理暴露。沉积并平坦化凸起的隔离介电层以形成采用模板材料部分作为停止结构的凸起隔离结构。在去除模板材料部分之后，一组半导体鳍片位于与半导体鳍片簇的外边缘自对准的沟槽内。沟槽可以用来限制要形成在半导体鳍片簇上的凸起的源极/漏极区域。

63. 发明授权

US08557648B2 Recessed source and drain regions for FinFETs 有权
公开(公告)号：US08557648B2
公开(公告)日：2013-10-15
申请号：US13348188
申请日：2012-01-11
申请人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Chung-Hsun Lin , Jeffrey W. Sleight
发明人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Chung-Hsun Lin , Jeffrey W. Sleight
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/785
摘要： Semiconductor devices and methods that include forming a fin field effect transistor by defining a fin hardmask on a semiconductor layer, forming a dummy structure over the fin hardmask to establish a planar area on the semiconductor layer, removing a portion of the fin hardmask that extends beyond the dummy structure, etching a semiconductor layer adjacent to the dummy structure to produce recessed source and drain regions, removing the dummy structure, etching the semiconductor layer in the planar area to produce fins, and forming a gate stack over the fins.

64. 发明申请

US20130265411A1 SYSTEM AND METHOD FOR INSPECTING SCRAPED SURFACE OF A WORKPIECE 审中-公开
标题翻译：检查工件的切割表面的系统和方法
公开(公告)号：US20130265411A1
公开(公告)日：2013-10-10
申请号：US13442391
申请日：2012-04-09
申请人： Ching-Wei Wu , Ying-Shing Shiao , Chia-Hui Tang , Paul Chang
发明人： Ching-Wei Wu , Ying-Shing Shiao , Chia-Hui Tang , Paul Chang
IPC分类号： G06K9/62 , H04N9/04 , H04N7/18
CPC分类号： G06T7/0004 , G06T2207/10024 , G06T2207/20036 , G06T2207/30164 , H04N5/225
摘要： A system for inspecting a scraped surface of a workpiece performs steps of: a) capturing an image of the scraped surface to obtain a original image section; b) removing high point regions whose areas are outside of a predetermined area range to obtain a base image; c) processing pixels of the base image using a first imaging mask to generate a judgment image; d) determining whether uniformity of the high point regions in the base image conforms a standard; e) determining whether a number of the high point regions in the base image falls within a predetermined number range; and f) evaluating whether or not a portion of the scraped surface conforms with the standard based on results of determinations made in steps d) and e).
摘要翻译：用于检查工件的刮削表面的系统执行以下步骤：a）捕获刮削表面的图像以获得原始图像部分; b）去除区域在预定区域范围之外的高点区域以获得基本图像; c）使用第一成像掩模处理所述基本图像的像素以产生判断图像; d）确定基本图像中的高点区域的均匀度是否符合标准; e）确定所述基本图像中的所述高点区域的数量是否在预定数量范围内; 以及f）基于步骤d）和e）中确定的结果来评估刮削表面的一部分是否符合标准。

65. 外观设计

USD686175S1 Wafer carrier having pockets 有权
公开(公告)号：USD686175S1
公开(公告)日：2013-07-16
申请号：US29416224
申请日：2012-03-20
申请人： Alexander I. Gurary , Keng Moy , Paul Chang
设计人： Alexander I. Gurary , Keng Moy , Paul Chang

66. 发明授权

US08466451B2 Single gate inverter nanowire mesh 失效
标题翻译：单门逆变器纳米线网
公开(公告)号：US08466451B2
公开(公告)日：2013-06-18
申请号：US13316515
申请日：2011-12-11
申请人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
发明人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
IPC分类号： H01L29/06 , H01L31/00 , H01L27/105 , H01L27/148
CPC分类号： H01L27/1203 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A FET inverter is provided that includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.
摘要翻译：提供一种FET逆变器，其包括在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和多个纳米线通道，其中一个或多个器件层的源极和漏极区掺杂有n型掺杂剂，并且一个或多个其它器件层的源极和漏极区掺杂有p型掺杂剂; 围绕纳米线通道的每个器件层共用的栅极; 与掺杂有n型掺杂剂的一个或多个器件层的源极区的第一接触; 与掺杂有p型掺杂剂的一个或多个器件层的源极区的第二接触; 以及每个器件层的漏极区域共同的第三接触。还提供了用于制造FET逆变器的技术。

67. 发明授权

US08422273B2 Nanowire mesh FET with multiple threshold voltages 有权
标题翻译：具有多个阈值电压的纳米线网状FET
公开(公告)号：US08422273B2
公开(公告)日：2013-04-16
申请号：US12470159
申请日：2009-05-21
申请人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
发明人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
IPC分类号： G11C11/00
CPC分类号： H01L29/0665 , B82Y10/00 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/775 , H01L29/78696
摘要： Nanowire-based field-effect transistors (FETs) and techniques for the fabrication thereof are provided. In one aspect, a FET is provided having a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels connecting the source region and the drain region, wherein one or more of the device layers are configured to have a different threshold voltage from one or more other of the device layers; and a gate common to each of the device layers surrounding the nanowire channels.
摘要翻译：提供了基于纳米线的场效应晶体管（FET）及其制造技术。在一个方面，提供了一种FET，其具有在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和连接源区和漏区的多个纳米线通道，其中一个或多个的器件层被配置为具有来自一个或多个其它器件层的不同阈值电压; 以及围绕纳米线通道的每个器件层共用的栅极。

68. 发明申请

US20120326127A1 COLLAPSABLE GATE FOR DEPOSITED NANOSTRUCTURES 失效
标题翻译：沉积式纳米结构的可收缩门
公开(公告)号：US20120326127A1
公开(公告)日：2012-12-27
申请号：US13169542
申请日：2011-06-27
申请人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Philip S. Waggoner
发明人： Josephine B. Chang , Paul Chang , Michael A. Guillorn , Philip S. Waggoner
IPC分类号： H01L51/10 , H01L51/40
CPC分类号： H01L29/66045 , H01L51/055
摘要： A disposable material layer is first deposited on a graphene layer or a carbon nanotube (CNT). The disposable material layer includes a material that is less inert than graphene or CNT so that a contiguous dielectric material layer can be deposited at a target dielectric thickness without pinholes therein. A gate stack is formed by patterning the contiguous dielectric material layer and a gate conductor layer deposited thereupon. The disposable material layer shields and protects the graphene layer or the CNT during formation of the gate stack. The disposable material layer is then removed by a selective etch, releasing a free-standing gate structure. The free-standing gate structure is collapsed onto the graphene layer or the CNT below at the end of the selective etch so that the bottom surface of the contiguous dielectric material layer contacts an upper surface of the graphene layer or the CNT.
摘要翻译：一次性材料层首先沉积在石墨烯层或碳纳米管（CNT）上。一次性材料层包括比石墨烯或CNT更不惰性的材料，使得可以以目标电介质厚度沉积连续的电介质材料层而没有针孔。通过图案化连续的介电材料层和沉积在其上的栅极导体层来形成栅极叠层。一次性材料层在形成栅极叠层期间屏蔽并保护石墨烯层或CNT。然后通过选择性蚀刻去除一次性材料层，释放独立的栅极结构。独立栅极结构在选择性蚀刻结束时在石墨烯层或CNT上折叠，使得连续介电材料层的底表面接触石墨烯层或CNT的上表面。

69. 发明申请

US20120138888A1 Single Gate Inverter Nanowire Mesh 失效
标题翻译：单门逆变器纳米线网
公开(公告)号：US20120138888A1
公开(公告)日：2012-06-07
申请号：US13316515
申请日：2011-12-11
申请人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
发明人： Josephine Chang , Paul Chang , Michael A. Guillorn , Jeffrey Sleight
IPC分类号： H01L27/088 , H01L29/775 , B82Y99/00
CPC分类号： H01L27/1203 , H01L27/092 , H01L29/0673 , H01L29/42392 , H01L29/78696 , Y10S977/762 , Y10S977/938
摘要： A FET inverter is provided that includes a plurality of device layers oriented vertically in a stack, each device layer having a source region, a drain region and a plurality of nanowire channels, wherein the source and drain regions of one or more of the device layers are doped with an n-type dopant and the source and drain regions of one or more other of the device layers are doped with a p-type dopant; a gate common to each of the device layers surrounding the nanowire channels; a first contact to the source regions of the one or more device layers doped with an n-type dopant; a second contact to the source regions of the one or more device layers doped with a p-type dopant; and a third contact common to the drain regions of each of the device layers. Techniques for fabricating a FET inverter are also provided.
摘要翻译：提供一种FET逆变器，其包括在堆叠中垂直取向的多个器件层，每个器件层具有源极区，漏极区和多个纳米线通道，其中一个或多个器件层的源极和漏极区掺杂有n型掺杂剂，并且一个或多个其它器件层的源极和漏极区掺杂有p型掺杂剂; 围绕纳米线通道的每个器件层共用的栅极; 与掺杂有n型掺杂剂的一个或多个器件层的源极区的第一接触; 与掺杂有p型掺杂剂的一个或多个器件层的源极区的第二接触; 以及每个器件层的漏极区域共同的第三接触。还提供了用于制造FET逆变器的技术。

70. 发明授权

US08051346B2 Fault injection 有权
标题翻译：故障注入
公开(公告)号：US08051346B2
公开(公告)日：2011-11-01
申请号：US12392468
申请日：2009-02-25
申请人： Senthil Somasundaram , Jun Qian , Paul Chang , Thomas A. Hamilton
发明人： Senthil Somasundaram , Jun Qian , Paul Chang , Thomas A. Hamilton
IPC分类号： G01R31/28 , G01R31/08 , G01R27/28 , G01R31/00 , G01R31/14 , G11C7/00 , G11C29/00
CPC分类号： G01R31/31716 , G01R31/31706 , G01R31/31717
摘要： Systems, methods, and other embodiments associated with programmable application specific integrated circuit (ASIC) fault injection are described. One example ASIC includes a serializer de-serializer (SERDES). The example ASIC may also include logics to process data in the ASIC. At least one of the logics either receives data from the SERDES and/or provides data to the SERDES. The example ASIC may also include an embedded fault injection logic (EFIL) to control injection of a fault to a path (e.g., data, control) associated with at least one of the logics. The example ASIC may also include an embedded set of multiplexers (ESOMs) controlled by the EFIL. The ESOMs are controllable by the EFIL to inject a fault signal to the data path.
摘要翻译：描述了与可编程应用专用集成电路（ASIC）故障注入相关联的系统，方法和其他实施例。一个示例性ASIC包括串行器解串器（SERDES）。示例ASIC还可以包括用于处理ASIC中的数据的逻辑。至少有一个逻辑可以从SERDES接收数据和/或向SERDES提供数据。示例性ASIC还可以包括嵌入式故障注入逻辑（EFIL），以控制将故障注入与至少一个逻辑相关联的路径（例如，数据，控制）。示例性ASIC还可以包括由EFIL控制的嵌入式多路复用器集合（ESOM）。 ESOM可由EFIL控制，以将故障信号注入数据通路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式