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61. 发明授权

US07647477B2 Branch target aware instruction prefetching technique 有权
标题翻译：分支目标感知指令预取技术
公开(公告)号：US07647477B2
公开(公告)日：2010-01-12
申请号：US10996027
申请日：2004-11-23
申请人： Paul Caprioli , Shailender Chaudhry
发明人： Paul Caprioli , Shailender Chaudhry
IPC分类号： G06F15/00
CPC分类号： G06F9/3804 , G06F9/382 , G06F9/3844 , G06F9/3846
摘要： Inspecting a currently fetched instruction group and determining branching behavior of the currently fetched instruction group, allows for intelligent instruction prefetching. A currently fetched instruction group is predecoded and, assuming the currently fetch instruction group includes a branch type instruction, a branch target is characterized in relation to a fetch boundary, which delimits a memory region contiguous with the memory region that hosts the currently fetched instruction group. Instruction prefetching is included based, at least in part, on the predecoded characterization of the branch target.
摘要翻译：检查当前获取的指令组并确定当前获取的指令组的分支行为，允许智能指令预取。当前获取的指令组被预解码，并且假设当前获取指令组包括分支类型指令，则分支目标与获取边界相关，其限定与承载当前获取的指令组的存储器区域相邻的存储器区域。基于至少部分地基于分支目标的预解码特征来包括指令预取。

62. 发明申请

US20090265532A1 ANTI-PREFETCH INSTRUCTION 有权
标题翻译：防伪指示
公开(公告)号：US20090265532A1
公开(公告)日：2009-10-22
申请号：US12104159
申请日：2008-04-16
申请人： Paul Caprioli , Sherman H. Yip , Gideon Levinsky
发明人： Paul Caprioli , Sherman H. Yip , Gideon Levinsky
IPC分类号： G06F9/38
CPC分类号： G06F9/3802 , G06F9/3004 , G06F9/30047 , G06F9/30087 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3863 , G06F9/3867 , G06F12/0862
摘要： Embodiments of the present invention execute an anti-prefetch instruction. These embodiments start by decoding instructions in a decode unit in a processor to prepare the instructions for execution. Upon decoding an anti-prefetch instruction, these embodiments stall the decode unit to prevent decoding subsequent instructions. These embodiments then execute the anti-prefetch instruction, wherein executing the anti-prefetch instruction involves: (1) sending a prefetch request for a cache line in an L1 cache; (2) determining if the prefetch request hits in the L1 cache; (3) if the prefetch request hits in the L1 cache, determining if the cache line contains a predetermined value; and (4) conditionally performing subsequent operations based on whether the prefetch request hits in the L1 cache or the value of the data in the cache line.
摘要翻译：本发明的实施例执行反预取指令。这些实施例首先解码处理器中的解码单元中的指令，以准备执行指令。在对反预取指令进行解码时，这些实施例使解码单元停止以防止解码后续指令。这些实施例然后执行反预取指令，其中执行反预取指令涉及：（1）在L1高速缓存中发送用于高速缓存行的预取请求; （2）确定预取请求是否在L1高速缓存中命中; （3）如果预取请求命中在L1高速缓存中，则确定高速缓存线是否包含预定值; 以及（4）基于所述预提取请求是否在所述L1高速缓存中的命中或所述高速缓存行中的数据的值有条件地执行后续操作。

63. 发明授权

US07590830B2 Method and structure for concurrent branch prediction in a processor 有权
标题翻译：处理器中并行分支预测的方法和结构
公开(公告)号：US07590830B2
公开(公告)日：2009-09-15
申请号：US11068626
申请日：2005-02-28
申请人： Shailender Chaudhry , Paul Caprioli
发明人： Shailender Chaudhry , Paul Caprioli
IPC分类号： G06F9/00 , G06F9/26
CPC分类号： G06F9/3806 , G06F9/3848
摘要： Concurrently branch predicting for multiple branch-type instructions demands of high performance environments. Concurrently branch predicting for multiple branch-type instructions provides the instruction flow for a high bandwidth pipeline utilized in advanced performance environments. Branch predictions are concurrently generated for multiple branch-type instructions. The concurrently generated branch predictions are then supplied for further processing of the corresponding branch-type instructions.
摘要翻译：同时分支预测多种分支式指令对高性能环境的要求。多分支式指令的并行预测为高级性能环境中使用的高带宽管道提供了指令流程。对于多个分支类型的指令同时生成分支预测。然后提供同时产生的分支预测用于进一步处理对应的分支型指令。

64. 发明申请

US20090217013A1 METHOD AND APPARATUS FOR PROGRAMMATICALLY REWINDING A REGISTER INSIDE A TRANSACTION 有权
标题翻译：用于在交易中编程注册的方法和装置
公开(公告)号：US20090217013A1
公开(公告)日：2009-08-27
申请号：US12037636
申请日：2008-02-26
申请人： Paul Caprioli
发明人： Paul Caprioli
IPC分类号： G06F9/30
CPC分类号： G06F9/30123 , G06F9/3004 , G06F9/30087 , G06F9/3013 , G06F9/30145 , G06F9/3834 , G06F9/3863 , G06F9/462
摘要： Embodiments of the present invention provide a system that allocates registers in a processor. The system starts by commencing a transaction, wherein commencing the transaction involves preserving a pre-transactional state of registers in a first register file. The system then allocates one or more registers for temporary use during the transaction. Upon finishing using each allocated register during the transaction, the system executes an instruction that restores the allocated register to the pre-transactional state.
摘要翻译：本发明的实施例提供一种在处理器中分配寄存器的系统。系统从开始事务开始，其中开始事务涉及在第一寄存器文件中保留寄存器的事务前状态。然后系统在事务期间分配一个或多个临时使用的寄存器。一旦完成了在交易过程中使用每个分配的寄存器，系统将执行将所分配的寄存器恢复到事务前状态的指令。

65. 发明申请

US20090187727A1 INDEX GENERATION FOR CACHE MEMORIES 有权
标题翻译：高速缓存记录的索引生成
公开(公告)号：US20090187727A1
公开(公告)日：2009-07-23
申请号：US12018407
申请日：2008-01-23
申请人： Paul Caprioli , Martin Karlsson , Shailender Chaudhry
发明人： Paul Caprioli , Martin Karlsson , Shailender Chaudhry
IPC分类号： G06F12/08 , G06F12/10
CPC分类号： G06F12/0864 , G06F2212/6082
摘要： Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index using the address information and the non-address information. The system then uses the index to fulfill access the cache memory.
摘要翻译：本发明的实施例提供一种生成高速缓冲存储器的索引的系统。系统通过接收访问高速缓冲存储器的请求开始，其中请求包括地址信息。然后系统获得与请求相关联的非地址信息。接下来，系统使用地址信息和非地址信息来生成索引。然后，系统使用索引来实现对高速缓存的访问。

66. 发明申请

US20090182956A1 METHOD AND APPARATUS FOR IMPROVING TRANSACTIONAL MEMORY COMMIT LATENCY 有权
标题翻译：用于改进交易记忆提交延迟的方法和装置
公开(公告)号：US20090182956A1
公开(公告)日：2009-07-16
申请号：US12014217
申请日：2008-01-15
申请人： Paul Caprioli , Martin Karlsson , Sherman H. Yip
发明人： Paul Caprioli , Martin Karlsson , Sherman H. Yip
IPC分类号： G06F9/46 , G06F12/08
CPC分类号： G06F12/084 , G06F9/30087 , G06F9/3834 , G06F9/3857 , G06F9/467 , G06F12/126 , G06F2212/1016
摘要： Embodiments of the present invention provide a system that executes transactions on a processor that supports transactional memory. The system starts by executing the transaction on the processor. During execution of the transactions, the system places stores in a store buffer. In addition, the system sets a stores_encountered indicator when a first store is placed in the store buffer during the transaction. Upon completing the transaction, the system determines if the stores_encountered indicator is set. If so, the system signals a cache to commit the stores placed in the store buffer during the transaction to the cache and then resumes execution of program code following the transaction when the stores have been committed. Otherwise, the system resumes execution of program code following the transaction without signaling the cache.
摘要翻译：本发明的实施例提供一种在支持事务存储器的处理器上执行事务的系统。系统通过在处理器上执行事务来启动。在执行事务期间，系统将存储放在存储缓冲区中。此外，当事务期间第一个存储被放置在存储缓冲区中时，系统设置stores_en遇到的指示符。完成交易后，系统确定是否设置了stores_en遭遇指示符。如果是这样，系统就会发出一个缓存，将事务期间放置在存储缓冲区中的存储提交到高速缓存，然后在存储已提交后，在事务之后恢复执行程序代码。否则，系统将在事务之后恢复执行程序代码，而不发出缓存信号。

67. 发明授权

US07472264B2 Predicting a jump target based on a program counter and state information for a process 有权
标题翻译：基于程序计数器和进程的状态信息预测跳转目标
公开(公告)号：US07472264B2
公开(公告)日：2008-12-30
申请号：US11479890
申请日：2006-06-30
申请人： Edmond H. Yip , Paul Caprioli , Shailender Chaudhry , Jiejun Lu
发明人： Edmond H. Yip , Paul Caprioli , Shailender Chaudhry , Jiejun Lu
IPC分类号： G06F9/42
CPC分类号： G06F9/3844 , G06F9/30054 , G06F9/3806
摘要： One embodiment of the present invention provides a system that predicts a jump target for a jump instruction. During operation, the system starts fetching the jump instruction while executing a process. Next, the system uses a program counter for the process and uses state information that is specific to the process to look up the jump target for the jump instruction. Finally, the system uses the jump target returned by the lookup as a predicted jump target for the jump instruction.
摘要翻译：本发明的一个实施例提供一种预测跳转指令的跳转目标的系统。在运行过程中，系统在执行进程时开始获取跳转指令。接下来，系统使用用于该过程的程序计数器，并且使用特定于处理的状态信息来查找跳转指令的跳转目标。最后，系统使用查找返回的跳转目标作为跳转指令的预测跳转目标。

68. 发明申请

US20080172549A1 Method and apparatus for counting instructions during speculative execution 有权
标题翻译：在推测执行期间计数指令的方法和装置
公开(公告)号：US20080172549A1
公开(公告)日：2008-07-17
申请号：US11654271
申请日：2007-01-16
申请人： Paul Caprioli , Shailender Chaudhry , Sherman H. Yip
发明人： Paul Caprioli , Shailender Chaudhry , Sherman H. Yip
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30181 , G06F9/30189 , G06F11/3612
摘要： One embodiment of the present invention provides a system that counts speculatively-executed instructions for performance analysis purposes. During operation, the system counts instructions which are normally executed during a normal-execution mode. Next, the system enters a speculative-execution mode wherein instructions are speculatively executed without being committed to the architectural state of the processor. During the speculative-execution mode, the system counts the speculatively-executed instructions in a manner that enables the count of speculatively-executed instructions to be reset if the speculative execution fails.
摘要翻译：本发明的一个实施例提供了一种用于对性能分析目的进行推测执行的指令的计数的系统。在运行期间，系统对通常在正常执行模式下执行的指令进行计数。接下来，系统进入推测执行模式，其中指令被推测地执行而不被提交到处理器的架构状态。在推测执行模式期间，如果推测执行失败，系统会以推测式执行指令的计数复位的方式对推测式执行的指令进行计数。

69. 发明授权

US07293161B1 Deferring loads and stores when a load buffer or store buffer fills during execute-ahead mode 有权
标题翻译：在执行提前模式下，当加载缓冲区或存储缓冲区填满时，延迟加载和存储
公开(公告)号：US07293161B1
公开(公告)日：2007-11-06
申请号：US11106180
申请日：2005-04-13
申请人： Shailender Chaudhry , Paul Caprioli , Marc Tremblay
发明人： Shailender Chaudhry , Paul Caprioli , Marc Tremblay
IPC分类号： G06F9/48
CPC分类号： G06F9/383 , G06F9/30181 , G06F9/3814 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3842 , G06F9/3863 , G06F12/0862
摘要： One embodiment of the present invention provides a system that facilitates deferring execution of instructions with unresolved data dependencies as they are issued for execution in program order. During a normal execution mode, the system issues instructions for execution in program order. Upon encountering an unresolved data dependency during execution of an instruction, the system generates a checkpoint that can subsequently be used to return execution of the program to the point of the instruction. Next, the system executes the instruction and subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of an unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. Upon encountering a store during the execute-ahead mode, the system determines if the store buffer is full. If so, the system prefetches a cache line for the store, and defers execution of the store.
摘要翻译：本发明的一个实施例提供了一种系统，其有助于在按照程序顺序执行时，推迟执行具有未解决的数据依赖性的指令。在正常执行模式下，系统以程序顺序发出执行指令。在执行指令期间遇到未解决的数据依赖性时，系统产生一个检查点，随后可以使用该检查点将程序的执行返回到指令点。接下来，系统以执行模式执行指令和后续指令，其中由于未解决的数据依赖性而不能执行的指令被延迟，并且其中以程序顺序执行其他非延迟指令。在执行提前模式期间遇到存储器时，系统确定存储缓冲区是否已满。如果是这样，系统将预取商店的高速缓存线，并延迟商店的执行。

70. 发明授权

US07293160B2 Mechanism for eliminating the restart penalty when reissuing deferred instructions 有权
标题翻译：重新发布延期指示时消除重启罚款的机制
公开(公告)号：US07293160B2
公开(公告)日：2007-11-06
申请号：US11058521
申请日：2005-02-14
申请人： Shailender Chaudhry , Paul Caprioli , Marc Tremblay
发明人： Shailender Chaudhry , Paul Caprioli , Marc Tremblay
IPC分类号： G06F9/30 , G06F9/40
CPC分类号： G06F9/3842 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857 , G06F9/3863
摘要： One embodiment of the present invention provides a system which facilitates eliminating a restart penalty when reissuing deferred instructions in a processor that supports speculative-execution. During a normal execution mode, the system issues instructions for execution in program order, wherein issuing the instructions involves decoding the instructions. Upon encountering an unresolved data dependency during execution of an instruction, the processor performs a checkpointing operation and executes subsequent instructions in an execute-ahead mode, wherein instructions that cannot be executed because of the unresolved data dependency are deferred, and wherein other non-deferred instructions are executed in program order. When an unresolved data dependency is resolved during execute-ahead mode, the processor begins to execute the deferred instructions in a deferred mode. In doing so, the processor initially issues deferred instructions, which have already been decoded, from a deferred queue. Simultaneously, the processor feeds instructions from a deferred SRAM into the decode unit, and these instructions eventually pass into the deferred queue. In this way, at the start of deferred mode, deferred instructions can issue from the deferred queue without having to pass through the decode unit, thereby providing time for deferred instructions from the deferred SRAM to progress through a decode unit in order to read input values for the decoded instruction, but not to be re-decoded.
摘要翻译：本发明的一个实施例提供了一种在支持推测执行的处理器中重新发布延迟指令时有助于消除重新启动损失的系统。在正常执行模式期间，系统以程序顺序发出执行指令，其中发出指令涉及解码指令。在执行指令期间遇到未解决的数据依赖性时，处理器执行检查点操作并以执行模式执行后续指令，其中由于未解决的数据依赖性而不能执行的指令被推迟，并且其中其他非延迟指令以程序顺序执行。当在执行提前模式下解决未解决的数据依赖关系时，处理器开始以延迟模式执行延迟指令。在这样做时，处理器最初从延迟队列中发出已被解码的延迟指令。同时，处理器将来自延迟SRAM的指令送入解码单元，并且这些指令最终进入延迟队列。以这种方式，在延迟模式开始时，延迟指令可以从延迟队列中发出，而不必通过解码单元，从而为延迟的SRAM提供延迟指令的时间，以进行解码单元以便读取输入值对于解码的指令，但不被重新解码。

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