专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20060014347A1 Semiconductor integrated circuit device having single-element type non-volatile memory elements 失效
公开(公告)号：US20060014347A1
公开(公告)日：2006-01-19
申请号：US11220723
申请日：2005-09-08
申请人： Kazuhiro Komori , Toshiaki Nishimoto , Satoshi Meguro , Hitoshi Kume , Yoshiaki Kamigaki
发明人： Kazuhiro Komori , Toshiaki Nishimoto , Satoshi Meguro , Hitoshi Kume , Yoshiaki Kamigaki
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , G11C16/0416 , H01L27/0688 , H01L27/1052 , H01L27/11526 , H01L27/11546 , H01L29/66659 , H01L29/7835 , H01L29/7885 , H01L29/7886
摘要： A semiconductor memory device having nonvolatile memory cells each formed of a MISFET having both a floating gate and a control gate and first and second semiconductor regions serving as the source and drain regions, respectively. In accordance with the method of manufacture thereof, an impurity, for example, arsenic, is introduced to form both the first and second semiconductor regions but with the second semiconductor region having a lower dose thereof so that the first semiconductor region formed attains a junction depth greater than that of the second semiconductor region, and both the first and second semiconductor regions have portions thereof extending under the floating gate electrode. The device and method therefor further feature the formation of MISFETs of peripheral circuits.

62. 发明授权

US06815761B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06815761B2
公开(公告)日：2004-11-09
申请号：US10419944
申请日：2003-04-22
申请人： Toshiaki Nishimoto , Takashi Aoyagi , Shogo Kiyota
发明人： Toshiaki Nishimoto , Takashi Aoyagi , Shogo Kiyota
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0483 , H01L21/76229 , H01L21/823412 , H01L21/823481 , H01L27/115
摘要： In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.

63. 发明授权

US06583467B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06583467B2
公开(公告)日：2003-06-24
申请号：US10179217
申请日：2002-06-26
申请人： Toshiaki Nishimoto , Takashi Aoyagi , Shogo Kiyota
发明人： Toshiaki Nishimoto , Takashi Aoyagi , Shogo Kiyota
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/0483 , H01L21/76229 , H01L21/823412 , H01L21/823481 , H01L27/115
摘要： In the semiconductor integrated circuit device, an AND-type flash memory is formed on a substrate in which stripe-like element separation regions 5 are formed and active regions L sandwiched between the element separation regions 5 are formed like stripes. A silicon monocrystal substrate containing nitrogen or carbon is used as the semiconductor substrate, to reduce dislocation defects and junction leakages so that the reliability and yield are improved.
摘要翻译：在半导体集成电路装置中，在形成有条状元件分离区域5的基板上形成有AND型闪速存储器，并且夹持在元件分离区域5之间的有源区域L形成为条状。使用含有氮或碳的硅单晶衬底作为半导体衬底，以减少错位缺陷和接头泄漏，从而提高可靠性和产率。

64. 发明授权

US5978270A Semiconductor non-volatile memory device and computer system using the same 失效
标题翻译：半导体非易失性存储器件和使用其的计算机系统
公开(公告)号：US5978270A
公开(公告)日：1999-11-02
申请号：US29748
申请日：1998-03-02
申请人： Toshihiro Tanaka , Masataka Kato , Osamu Tsuchiya , Toshiaki Nishimoto
发明人： Toshihiro Tanaka , Masataka Kato , Osamu Tsuchiya , Toshiaki Nishimoto
IPC分类号： G11C16/04 , G11C16/28 , G11C16/34 , G11C16/06
CPC分类号： G11C16/3413 , G11C16/0416 , G11C16/28 , G11C16/3404 , G11C16/3409 , G11C16/3459
摘要： After decreasing the threshold voltages of a plurality of memory cells collectively or selectively, the presence or absence of any memory cell of which the threshold voltage has dropped below a predetermined voltage verified collectively for each of memory cell groups connected to word line (low-threshold value verification), and any memory cell of which the threshold voltage has excessively dropped is selectively written. Also, the well of each of memory cell is formed in the region of an element isolation layer for isolating it from the substrate of a memory apparatus, and a negative voltage is supplied to the memory well distributively with a positive voltage applied as a word line voltage, thus supplying them as erase operation voltages. The absolute value of the memory well voltage is set substantially equal to or lower than the word line voltage for the read operation. Sectors constituting each memory mat includes a sector (selected sector) selected for the erase operation with each word line thereof supplied with a positive voltage, a sector (non-selected sector) not selected for the erase operation with a word line voltage different from a memory well voltage, and further a sector (completely non-selected sector) not selected for the erase operation with a word line voltage equal to the voltage between a source and a drain of the memory cell.
摘要翻译： PCT No.PCT / JP96 / 02419 Sec。 371日期1998年3月2日 102（e）1998年3月2日PCT PCT 1996年8月29日PCT公布。公开号WO97 / 08707 日期1997年3月6日在集体或选择性地降低多个存储器单元的阈值电压之后，存在或不存在阈值电压已经下降到预定电压以下的任何存储单元，该存储单元对于连接到字的每个存储单元组线路（低阈值验证），并且选择性地写入阈值电压过度下降的任何存储单元。此外，存储单元的阱形成在用于将其与存储装置的基板隔离的元件隔离层的区域中，并且以施加作为字线的正电压将负电压分配地提供给存储器电压，从而将其提供为擦除操作电压。存储器阱电压的绝对值被设定为基本上等于或低于读取操作的字线电压。构成每个存储器垫的扇区包括为其擦除操作选择的扇区（选择的扇区），其每个字线被提供有正电压，未被选择用于擦除操作的扇区（未选择的扇区），字线电压不同于存储器阱电压，以及未被选择用于具有等于存储器单元的源极和漏极之间的电压的字线电压的擦除操作的扇区（完全未选择的扇区）。

65. 发明授权

US5629541A Semiconductor memory device constituted by single transistor type non-volatile cells and facilitated for both electrical erasing and writing of data 失效
标题翻译：半导体存储器件由单晶体管类型的非易失性单元构成，并且便于数据的电擦除和写入
公开(公告)号：US5629541A
公开(公告)日：1997-05-13
申请号：US422940
申请日：1995-04-17
申请人： Kazuhiro Komori , Toshiaki Nishimoto , Satoshi Meguro , Hitoshi Kume , Yoshiaki Kamigaki
发明人： Kazuhiro Komori , Toshiaki Nishimoto , Satoshi Meguro , Hitoshi Kume , Yoshiaki Kamigaki
IPC分类号： H01L21/8247 , H01L27/06 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/105 , H01L27/1052 , H01L27/11526 , H01L27/11546 , H01L29/66659 , H01L29/7835 , H01L29/7885 , H01L29/7886 , G11C16/0416 , H01L27/0688
摘要： A semiconductor integrated device having a non-volatile memory element or memory cell of a single-element type in a non-volatile memory circuit employing a field effect transistor which has, in addition to a floating gate electrode for storage of information and a controlling gate electrode, a source which includes a heavily doped region having a depth into the semiconductor substrate extending from the major surface thereof which is large. The single-element type field effect transistor, furthermore, has a drain which includes a lightly doped region which has a depth extending into the semiconductor substrate from the major surface thereof which is small.
摘要翻译：在具有场效应晶体管的非易失性存储器电路中具有非易失性存储元件或单元型存储单元的半导体集成器件，除了用于存储信息的浮栅电极和控制栅极之外，电极，其包括具有从其主表面延伸的半导体衬底的深度的重掺杂区域。此外，单元件型场效应晶体管具有漏极，其包括从其主表面延伸到半导体衬底中的深度较小的轻掺杂区域。

66. 发明授权

US5445980A Method of making a semiconductor memory device 失效
标题翻译：制造半导体存储器件的方法
公开(公告)号：US5445980A
公开(公告)日：1995-08-29
申请号：US147037
申请日：1993-11-04
申请人： Kazuhiro Komori , Satoshi Meguro , Toshiaki Nishimoto , Hitoshi Kume , Hideaki Yamamoto
发明人： Kazuhiro Komori , Satoshi Meguro , Toshiaki Nishimoto , Hitoshi Kume , Hideaki Yamamoto
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/105 , H01L29/423
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/11546 , H01L29/42324
摘要： An EEPROM (Electrically Erasable Programmable Read Only Memory) has a structure in which the corners of a floating gate electrode of each memory cell MISFET near the source region thereof are rounded.The EEPROM is manufactured by a method characterized in that the ions of an impurity at a high dose are implanted in self-alignment with the floating gate electrode and control gate electrode of the memory cell MISFET so as to form the source and drain regions thereof, whereupon an oxidizing treatment is carried out.
摘要翻译： EEPROM（电可擦除可编程只读存储器）具有其源极区域附近的每个存储单元MISFET的浮置栅极的角部为圆形的结构。通过以下方法制造EEPROM：其特征在于，高浓度杂质的离子与存储单元MISFET的浮置栅极电极和控制栅极电极自对准，以形成其源极和漏极区域，于是进行氧化处理。

67. 发明授权

US5153144A Method of making tunnel EEPROM 失效
标题翻译：隧道EEPROM的制作方法
公开(公告)号：US5153144A
公开(公告)日：1992-10-06
申请号：US794648
申请日：1991-11-18
申请人： Kazuhiro Komori , Satoshi Meguro , Toshiaki Nishimoto , Hitoshi Kume , Hideaki Yamamoto
发明人： Kazuhiro Komori , Satoshi Meguro , Toshiaki Nishimoto , Hitoshi Kume , Hideaki Yamamoto
IPC分类号： H01L21/28 , H01L21/8247 , H01L27/105 , H01L29/423
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/11546 , H01L29/42324
摘要： An EEPROM (Electrically Erasable Programmable Read Only Memory) has a structure in which the corners of a floating gate electrode of each memory cell MISFET near the source region thereof are rounded.The EEPROM is manufactured by a method characterized in that the ions of an impurity at a high dose are implanted in self-alignment with the floating gate electrode and control gate electrode of the memory cell MISFET so as to form the source and drain regions thereof, whereupon an oxidizing treatment is carried out.
摘要翻译： EEPROM（电可擦除可编程只读存储器）具有其源极区域附近的每个存储单元MISFET的浮置栅极的角部为圆形的结构。通过以下方法制造EEPROM：其特征在于，将高剂量杂质的离子与存储单元MISFET的浮置栅电极和控制栅电极自对准地注入，以形成其源区和漏区，于是进行氧化处理。

68. 发明授权

US4996571A Non-volatile semiconductor memory device erasing operation 失效
标题翻译：非易失性半导体存储器件擦除操作
公开(公告)号：US4996571A
公开(公告)日：1991-02-26
申请号：US375956
申请日：1989-07-06
申请人： Hitoshi Kume , Yoshiaki Kamigaki , Tetsuo Adachi , Toshihisa Tsukada , Kazuhiro Komori , Toshiaki Nishimoto , Tadashi Muto , Toshiko Koizumi
发明人： Hitoshi Kume , Yoshiaki Kamigaki , Tetsuo Adachi , Toshihisa Tsukada , Kazuhiro Komori , Toshiaki Nishimoto , Tadashi Muto , Toshiko Koizumi
IPC分类号： G11C17/00 , G11C16/04 , G11C16/14 , H01L29/788
CPC分类号： G11C16/3477 , G11C16/14 , H01L29/7884
摘要： The invention relates to a tunnel erasing device for a non-volatile semiconductor memory device comprising a source region and a drain region, a floating gate electrode having a part superposed on at least one of them through a gate insulating layer, and a control gate electrode disposed over the floating gate electrode through an interlayer insulating layer and is characterized as having a preliminary erasing operation in which a voltage is so applied to at least one of the source or drain region, with the control gate electrode grounded, that a relatively lower voltage than a predetermined voltage is applied preliminarily prior to applying thereto the predetermined voltage.
摘要翻译：本发明涉及一种用于非易失性半导体存储器件的隧道擦除装置，包括源极区和漏极区，通过栅极绝缘层将具有重叠在其中的至少一个上的部分的浮栅电极和控制栅电极通过层间绝缘层设置在浮栅上，并且其特征在于具有预先擦除操作，其中电压被施加到源区或漏区中的至少一个，控制栅电极接地，相对较低的电压预先施加预定电压之前施加预定电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式