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61. 发明申请

US20080084762A1 Method of identifying logical information in a programming and erasing cell by on-side reading scheme 有权
标题翻译：通过旁路读取方案识别编程和擦除单元中的逻辑信息的方法
公开(公告)号：US20080084762A1
公开(公告)日：2008-04-10
申请号：US11601710
申请日：2006-11-20
申请人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
发明人： Chao-I Wu , Ming-Hsiu Lee , Tzu-Hsuan Hsu
IPC分类号： G11C11/34
CPC分类号： G11C16/0475
摘要： A method of identifying logical information in a cell, particularly in a programming by hot hole injection nitride electron storage (PHINES) cell by one-side reading scheme is disclosed. The method comprise steps of: erasing the first region and the second region of PHINES cell by increasing a local threshold voltage (Vt) to a certain value; programming at least one of the first region and the second region of the PHINES cell by hot hole injection; and reading a logical state of the PHINES cell by measuring an output current of one of the first region and the second region; wherein different quantity of the output current is caused by interaction between different quantity of the hot hole stored in the first region and the second region, so as to determine the logical state of the PHINES cell by one-side reading scheme.
摘要翻译：公开了一种识别单元中的逻辑信息的方法，特别是在通过单孔读取方案通过热空穴注入氮化物电子存储（PHINES）单元编程中的方法。该方法包括以下步骤：通过将局部阈值电压（Vt）增加到一定值来擦除PHINES单元的第一区域和第二区域; 通过热空穴注入来编程PHINES单元的第一区域和第二区域中的至少一个; 以及通过测量所述第一区域和所述第二区域之一的输出电流来读取所述PHINES单元的逻辑状态; 其中，通过存储在第一区域和第二区域中的不同量的热孔之间的相互作用引起不同量的输出电流，以便通过单面读取方案确定PHINES单元的逻辑状态。

62. 发明申请

US20080023699A1 A TEST STRUCTURE AND METHOD FOR DETECTING CHARGE EFFECTS DURING SEMICONDUCTOR PROCESSING 审中-公开
标题翻译：用于检测半导体加工过程中的充电效应的测试结构和方法
公开(公告)号：US20080023699A1
公开(公告)日：2008-01-31
申请号：US11460209
申请日：2006-07-26
申请人： Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L23/58
CPC分类号： H01L22/34 , H01L2224/73204 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor process test structure comprises an electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. Gate-induced drain leakage (GIDL) measurement techniques can then be used to characterize the charging status of the test structure.
摘要翻译：半导体工艺测试结构包括电极，电荷俘获层和扩散区域。测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。然后可以使用栅极漏极泄漏（GIDL）测量技术来表征测试结构的充电状态。

63. 发明申请

US20070285976A1 Intergrated circuit having a precharging circuit 有权
标题翻译：具有预充电电路的集成电路
公开(公告)号：US20070285976A1
公开(公告)日：2007-12-13
申请号：US11450605
申请日：2006-06-09
申请人： Thomas Happ , Jan Boris Philipp , Ming-Hsiu Lee
发明人： Thomas Happ , Jan Boris Philipp , Ming-Hsiu Lee
IPC分类号： G11C11/00
CPC分类号： G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0071 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： A memory includes a phase change element having a first side and a second side and a first line coupled to the first side of the element. The memory includes an access device coupled to the second side of the element and a second line coupled to the access device for controlling the access device. The memory includes a circuit for precharging the first line to a first voltage and for applying a voltage pulse to the second line such that a current pulse is generated through the access device to the element to program the element to a selected one of more than two states. The voltage pulse has an amplitude based on the selected state.
摘要翻译：存储器包括具有第一侧和第二侧以及耦合到元件的第一侧的第一线的相变元件。存储器包括耦合到元件的第二侧的访问设备和耦合到访问设备的用于控制访问设备的第二行。存储器包括用于将第一线路预充电到第一电压并且用于将电压脉冲施加到第二线路的电路，使得通过该接入装置向该元件生成电流脉冲以将该元件编程为多于两个中的所选择的一个状态。电压脉冲具有基于选择状态的幅度。

64. 发明申请

US20070236237A1 A TEST STRUCTURE AND METHOD FOR DETECTING CHARGE EFFECTS DURING SEMICONDUCTOR PROCESSING USING A DELAYED INVERSION POINT TECHNIQUE 有权
标题翻译：使用延迟反转点技术在半导体处理期间检测充电效应的测试结构和方法
公开(公告)号：US20070236237A1
公开(公告)日：2007-10-11
申请号：US11279224
申请日：2006-04-10
申请人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-l Wu
发明人： Ming-Chang Kuo , Ming-Hsiu Lee , Chao-l Wu
IPC分类号： G01R31/26
CPC分类号： H01L22/14 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor process test structure comprises a gate electrode, a charge-trapping layer, and a diffusion region. The test structure is a capacitor-like structure in which the charge-trapping layer will trap charges during various processing steps. A CV measurement can then be used to detect whether a Vfb shift has occurred. If the process step resulted in a charge effect, then the induced charge will not be uniform. If the charging of the test structure is not uniform, then there will not be a Vfb shift. A delayed inversion point technique can then be used to monitor the charging status.
摘要翻译：半导体工艺测试结构包括栅电极，电荷捕获层和扩散区。测试结构是电容器状结构，其中电荷捕获层将在各种处理步骤期间捕获电荷。然后可以使用CV测量来检测是否发生了Vfb偏移。如果处理步骤导致电荷效应，则感应电荷将不均匀。如果测试结构的充电不均匀，则不会有Vfb偏移。然后可以使用延迟反转点技术来监视充电状态。

65. 发明申请

US20070161193A1 Systems and methods for a high density, compact memory array 有权
标题翻译：用于高密度，紧凑型存储器阵列的系统和方法
公开(公告)号：US20070161193A1
公开(公告)日：2007-07-12
申请号：US11327792
申请日：2006-01-06
申请人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
发明人： Tzu-Hsuan Hsu , Ming-Hsiu Lee , Chao-I Wu , Ming-Chang Kuo
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , G11C16/0475 , H01L27/11568 , H01L29/66833 , H01L29/792 , H01L29/7926
摘要： A memory array comprising vertical memory cells does not require any isolation layers between cells. Thus, a very compact, high density memory array can be achieved. Each memory cell in the memory array is configured to store 4 bits of data per cell. Multi-level charge techniques can be used to increase the number of bit per cell and achieve further increased density for the memory array.
摘要翻译：包括垂直存储单元的存储器阵列不需要单元之间的任何隔离层。因此，可以实现非常紧凑，高密度的存储器阵列。存储器阵列中的每个存储单元被配置为存储每个单元的4位数据。可以使用多电平充电技术来增加每个单元的位数，并实现对存储器阵列的进一步增加的密度。

66. 发明授权

US07092038B2 Adaptive Y/C separation circuit 有权
标题翻译：自适应Y / C分离电路
公开(公告)号：US07092038B2
公开(公告)日：2006-08-15
申请号：US10370450
申请日：2003-02-24
申请人： Yang-Hong Shih , Ming-Hsiu Lee
发明人： Yang-Hong Shih , Ming-Hsiu Lee
IPC分类号： H04N9/78
CPC分类号： H04N9/78
摘要： The present invention provides an adaptive Y/C separation circuit for video signal processing that is capable of correcting previous color discrepancy in separating the luminance (Y) and chrominance (C) signals from the color video signals. In the process, the correlation of video signals on referencing scanning lines is analyzed by transposing the chrominance signals onto a two-dimensional UV plane. A correlation coefficient is obtained through the analysis for adjusting the video signals in the direction of the actual chrominance level, thus separating the luminance and chrominance signals with relatively low cost circuit implementation.
摘要翻译：本发明提供了一种用于视频信号处理的自适应Y / C分离电路，其能够校正从彩色视频信号中分离亮度（Y）和色度（C）信号的先前颜色差异。在该过程中，通过将色度信号转换到二维UV平面来分析参考扫描线上的视频信号的相关性。通过用于在实际色度电平方向上调整视频信号的分析获得相关系数，从而以相对低成本的电路实现分离亮度和色度信号。

67. 发明申请

US20050254296A1 Method for controlling current during read and program operations of programmable diode 有权
标题翻译：用于在可编程二极管的读取和编程操作期间控制电流的方法
公开(公告)号：US20050254296A1
公开(公告)日：2005-11-17
申请号：US10846006
申请日：2004-05-14
申请人： Hang-Ting Lue , Ming-Hsiu Lee
发明人： Hang-Ting Lue , Ming-Hsiu Lee
IPC分类号： G11C5/14 , G11C11/36
CPC分类号： G11C5/147
摘要： A method for controlling current fluctuations during read and program operations in a memory structure is provided. The method includes applying a first voltage to a first gate of a word line decoder transistor. The method further includes applying a second voltage to a second gate of a bit line decoder transistor such that the first voltage is greater than the second voltage. The method also includes maintaining the source voltage of the bit line decoder transistor at about zero.
摘要翻译：提供了一种用于在存储器结构中的读取和编程操作期间控制电流波动的方法。该方法包括将第一电压施加到字线解码晶体管的第一栅极。该方法还包括将第二电压施加到位线解码晶体管的第二栅极，使得第一电压大于第二电压。该方法还包括将位线解码晶体管的源电压保持在大约零。

68. 发明授权

US06903410B1 Electrically erasable programmable read only memory cell and programming method thereof 有权
标题翻译：电可擦除可编程只读存储单元及其编程方法
公开(公告)号：US06903410B1
公开(公告)日：2005-06-07
申请号：US10710765
申请日：2004-08-02
申请人： Chao-I Wu , Ming-Hsiu Lee
发明人： Chao-I Wu , Ming-Hsiu Lee
IPC分类号： H01L29/792
CPC分类号： H01L29/7923
摘要： An electrically erasable programmable read only memory cell has a stacking layer, a gate conductive layer, a first source/drain region, a second source/drain region, a first pocket implant doping region, and a second pocket implant doping region. The stacking layer is disposed over a substrate. The gate conductive layer is located on the stacking layer. The first source/drain region and the second source/drain region are respectively disposed over the substrate on two sides of the gate conductive layer. The first pocket implant doping region is disposed over the substrate under the stacking layer, and adjacent to the first source/drain region. The second pocket implant doping region is disposed over the substrate under the stacking layer, and adjacent to the second source/drain region, wherein the doping concentration of the first pocket implant region is different from that of the second pocket implant region.
摘要翻译：电可擦除可编程只读存储器单元具有堆叠层，栅极导电层，第一源极/漏极区域，第二源极/漏极区域，第一腔体注入掺杂区域和第二凹穴注入掺杂区域。堆叠层设置在基板上。栅极导电层位于堆叠层上。第一源极/漏极区域和第二源极/漏极区域分别设置在栅极导电层的两侧上的衬底上。第一凹穴注入掺杂区域设置在堆叠层下面的衬底上，并且与第一源极/漏极区域相邻。第二袋状注入掺杂区域设置在堆叠层下面的衬底上，并且与第二源极/漏极区域相邻，其中第一凹穴注入区域的掺杂浓度不同于第二凹穴注入区域的掺杂浓度。

69. 发明授权

US06890819B2 Methods for forming PN junction, one-time programmable read-only memory and fabricating processes thereof 有权
标题翻译：用于形成PN结的方法，一次可编程只读存储器及其制造方法
公开(公告)号：US06890819B2
公开(公告)日：2005-05-10
申请号：US10605253
申请日：2003-09-18
申请人： Chao-I Wu , Ming-Hsiu Lee
发明人： Chao-I Wu , Ming-Hsiu Lee
IPC分类号： H01L21/336 , H01L27/10
CPC分类号： H01L27/10
摘要： A method for forming a PN junction is described. A stacked structure consisting of an N-doped (or P-doped) layer, a dielectric layer and a nucleation layer is formed, and then an insulating layer is formed having an opening therein. A P-doped (or N-doped) polysilicon or amorphous silicon layer is filled into the opening, and then annealed to convert into a single-crystal silicon layer. Then, the dielectric layer is broken down to form a PN junction.
摘要翻译：描述了形成PN结的方法。形成由N掺杂（或P掺杂）层，电介质层和成核层组成的堆叠结构，然后形成其中具有开口的绝缘层。将p掺杂（或N掺杂）多晶硅或非晶硅层填充到开口中，然后退火以转化为单晶硅层。然后，介电层被分解以形成PN结。

70. 发明授权

US6002114A Control device for an electric water heater 失效
标题翻译：电热水器控制装置
公开(公告)号：US6002114A
公开(公告)日：1999-12-14
申请号：US153044
申请日：1998-09-15
申请人： Ming-Hsiu Lee
发明人： Ming-Hsiu Lee
IPC分类号： F24H9/20 , G05D23/19 , H05B1/02
CPC分类号： G05D23/1931 , F24H9/2028
摘要： A control device installed in an electric water heater to control its operation, the control device including a water temperature control circuit and a power control circuit, the water temperature control circuit being formed of a water temperature detection circuit, which detects water temperature at the water inlet and the water outlet of the electric water heater, a water flow rate detection circuit, which detects the flow rate of water passing through the water inlet, a CPU, an indicator circuit controlled by the CPU to indicate the working conditions of the electric water heater, and a digital display controlled by the CPU to show the value of water temperature at the water outlet, the power control circuit being formed of a power supply circuit, a TRAIC triggering control circuit, which turns on the heating elements of the electric water heater alternatively subject AC phase change, a TRAIC power circuit, which provides the TRAIC triggering control circuit with the base power, an AC phase detection input circuit, a relay circuit controlled by the CPU to cut off power supply from the electric water heater when an abnormal condition occurs, a failure detection circuit, which outputs a signal to the CPU when an abnormal condition of the electric water heater is detected, causing the CPU to cut off power supply from the electric water heater, and an overheat protection circuit for overheat protection.
摘要翻译：一种安装在电热水器中以控制其操作的控制装置，所述控制装置包括水温控制电路和功率控制电路，所述水温控制电路由水温检测电路形成，所述水温检测电路检测所述水的水温电热水器的入口和出水口，检测通过入水口的水的流量的水流量检测电路，CPU，由CPU控制的指示电路，以指示电水的工作条件加热器和由CPU控制的数字显示器，以显示出水口的水温值，功率控制电路由电源电路，TRAIC触发控制电路构成，TRAIC触发控制电路接通电水的加热元件加热器交替相位变化，TRAIC电源电路，为TRAIC触发控制电路提供基本功率，a 交流相位检测输入电路，由CPU控制的继电器电路，当异常状态发生时切断电热水器的电源;故障检测电路，当电热水器的异常情况发生时，向CPU输出信号被检测到，导致CPU切断来自电热水器的电源，以及用于过热保护的过热保护电路。

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