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61. 发明授权

US5592496A Semiconductor test equipment 失效
标题翻译：半导体测试设备
公开(公告)号：US5592496A
公开(公告)日：1997-01-07
申请号：US416048
申请日：1995-04-04
申请人： Masao Shimizu , Kenji Yoshida
发明人： Masao Shimizu , Kenji Yoshida
IPC分类号： G01R31/28 , G01R31/319 , G06F11/00
CPC分类号： G01R31/31922 , G01R31/2851 , G01R31/31928
摘要： A semiconductor test equipment for testing a semiconductor device which is capable of reducing the cost and size is disclosed. The semiconductor test equipment includes a main clock generator for generating a main clock signal having the highest frequency, a first pattern generator which receives the main clock signal for generating a first test pattern signal, a clock divider which divides the main clock signal to generate a lower frequency clock signal, and a second pattern generator which receives the lower frequency clock for generating a second test pattern. The semiconductor test equipment further includes a first wave formatter which receives the first pattern signal for forming a predetermined wave shape, and a second wave formatter which receives the second pattern signal for forming a predetermined wave shape, a first comparator circuit which receives a first output signal from the device under test and compares the first output signal with a first expected pattern from the first pattern generator, and a second comparator circuit which receives a second output signal from the device under test and compares the second output signal with a second expected pattern from the second pattern generator.
摘要翻译：公开了一种用于测试能够降低成本和尺寸的半导体器件的半导体测试设备。半导体测试设备包括用于产生具有最高频率的主时钟信号的主时钟发生器，接收用于产生第一测试图形信号的主时钟信号的第一模式发生器，分频主时钟信号以产生低频时钟信号，以及接收用于产生第二测试图案的较低频率时钟的第二模式发生器。半导体测试设备还包括接收用于形成预定波形的第一图案信号的第一波形格式器和接收用于形成预定波形的第二图案信号的第二波形格式器，接收第一输出信号，并且将第一输出信号与来自第一模式发生器的第一预期模式进行比较，以及第二比较器电路，其从被测器件接收第二输出信号，并将第二输出信号与第二预期模式进行比较从第二模式发生器。

62. 发明授权

US5508838A Slit system 失效
标题翻译：狭缝系统
公开(公告)号：US5508838A
公开(公告)日：1996-04-16
申请号：US292735
申请日：1994-08-18
申请人： Masao Shimizu , Kenji Ishikawa
发明人： Masao Shimizu , Kenji Ishikawa
IPC分类号： H01J49/06 , G02B26/02
CPC分类号： H01J49/06
摘要： A small-sized, simple, high-resolution slit system adapted for use in a mass spectrometer. The slit system forms a slit whose width can be electrically controlled. The slit system comprises two displacement-enlarging mechanisms disposed in rotation symmetry. Each displacement-enlarging mechanism comprises two levers disposed in series. Each displacement-enlarging mechanism is formed by one flange provided with a groove extending therethrough. A piezoelectric device which expands and contracts along one axis is mounted to the input end of each displacement-enlarging mechanism. A blade is mounted to the output end of each displacement-enlarging mechanism. Both blades together form the slit which can be opened and closed.
摘要翻译：适用于质谱仪的小尺寸，简单，高分辨率的狭缝系统。狭缝系统形成其宽度可以被电控制的狭缝。狭缝系统包括以旋转对称设置的两个位移放大机构。每个位移放大机构包括串联布置的两个杠杆。每个位移放大机构由设有延伸穿过其中的槽的一个凸缘形成。沿着一个轴线膨胀和收缩的压电装置安装到每个位移放大机构的输入端。叶片安装到每个位移放大机构的输出端。两个叶片一起形成可以打开和关闭的狭缝。

63. 发明授权

US5165047A Driving circuit for vibration wave driven motor 失效
标题翻译：振动波驱动电机驱动电路
公开(公告)号：US5165047A
公开(公告)日：1992-11-17
申请号：US839280
申请日：1992-02-25
申请人： Masao Shimizu
发明人： Masao Shimizu
IPC分类号： H02N2/00 , H01L41/04 , H02N2/14
CPC分类号： H02N2/14 , H02N2/142
摘要： A driving circuit for a vibration wave driven motor, having a comparator detecting the drive state of the motor, and the drive frequency somewhat increased immediately before the motor reaches the resonance drive state. Also a second comparator is additionally provided for detecting the drive state of the motor at a second frequency higher than the frequency detected by the first-mentioned comparator, and the drive frequency of the motor is retained if the second comparator detects that the motor is driven with the second frequency.
摘要翻译：一种用于振动波驱动电动机的驱动电路，具有检测电动机的驱动状态的比较器，并且驱动频率在马达到达共振驱动状态之前稍微增加。此外，还提供了第二比较器，用于以比由首先提及的比较器检测到的频率高的第二频率来检测电动机的驱动状态，并且如果第二比较器检测到电动机被驱动，则保持电动机的驱动频率具有第二频率。

64. 发明授权

US4952712A Process for the preparation of 2,3-dimethoxy-5-methylbenzoquinone 失效
标题翻译： 2,3-二甲氧基-5-甲基苯醌的制备方法
公开(公告)号：US4952712A
公开(公告)日：1990-08-28
申请号：US322416
申请日：1989-03-13
申请人： Hideo Orita , Masao Shimizu , Takashi Hayakawa , Katsuomi Takehira
发明人： Hideo Orita , Masao Shimizu , Takashi Hayakawa , Katsuomi Takehira
IPC分类号： B01J27/188 , C07B61/00 , C07C45/00 , C07C46/02 , C07C46/04 , C07C50/28 , C07C50/30 , C07C67/00
CPC分类号： C07C50/28 , C07C46/02
摘要： 2,3-Dimethoxy-5-methylbenzoquinone is prepared by oxidizing 3,4,5-trimethoxytoluene by reaction with hydrogen peroxide in the presence of a catalyst which is a heteropolyacid selected from phosphomolybdic acids, phosphotungstic acids, silicomolybdic acids and silicotungstic acids or a salt thereof.

65. 发明授权

US4794294A Vibration wave motor 失效
标题翻译：振动马达
公开(公告)号：US4794294A
公开(公告)日：1988-12-27
申请号：US59782
申请日：1987-06-08
申请人： Masao Shimizu , Nobuyuki Suzuki , Mitsuhiro Katsuragawa
发明人： Masao Shimizu , Nobuyuki Suzuki , Mitsuhiro Katsuragawa
IPC分类号： H01L41/04 , H01L41/09 , H02N2/14 , H01L41/08
CPC分类号： H02N2/163 , H02N2/14 , H02N2/142
摘要： A vibration wave motor generates a travelling vibration wave by applying periodic voltages of different phases to electro-mechanical energy transducers located at two different positions on a stator, and drives a movable member by the vibration wave. In order to adjust the speed of the vibration wave motor, the phase difference between the periodic voltages applied to the transducer is adjusted or the application of the periodic voltage to one or both of the transducers is selectively blocked.
摘要翻译：振动波马达通过对位于定子上的两个不同位置的机电能量换能器施加不同相位的周期性电压来产生行进振动波，并通过振动波驱动可移动部件。为了调整振动波马达的速度，调整施加到换能器的周期性电压之间的相位差，或者选择性地阻挡向一个或两个换能器施加周期性电压。

66. 发明授权

US4586181A Test pattern generating apparatus 失效
标题翻译：测试图案生成装置
公开(公告)号：US4586181A
公开(公告)日：1986-04-29
申请号：US551429
申请日：1983-11-14
申请人： Masao Shimizu
发明人： Masao Shimizu
IPC分类号： G01R31/28 , G01R31/3183 , G01R31/319
CPC分类号： G01R31/31921
摘要： A test pattern generator includes means for reading out a plurality of memories non-successively while outputting the test patterns stored identically in the addresses of the memories, such as for sequentially repeating the test patterns that are provided to a logic circuit being tested. The sequence of test patterns is determined by a series of instructions which are accessed by a program counter, and the instructions can cause a jump in the counting of the program counter, for instance to repeat addresses of the memories for repeating a desired sequence of test patterns a predetermined number of times. The timing of the addressing of the memories for the reading out of the test patterns can be faster than the timing for writing the test patterns into the memories for storage.
摘要翻译：测试图形发生器包括用于在输出在存储器的地址中相同存储的测试图案的同时非连续读出多个存储器的装置，例如用于顺序重复提供给被测试的逻辑电路的测试图案。测试图案的顺序由程序计数器访问的一系列指令确定，并且指令可以导致程序计数器的计数中的跳转，例如重复存储器的地址以重复所需的测试序列模式预定次数。用于读出测试图案的存储器寻址的定时可以比将测试图案写入存储器的时间更快。

67. 发明授权

US4555663A Test pattern generating apparatus 失效
标题翻译：测试图案生成装置
公开(公告)号：US4555663A
公开(公告)日：1985-11-26
申请号：US552374
申请日：1983-11-16
申请人： Masao Shimizu
发明人： Masao Shimizu
IPC分类号： G01R31/28 , G01R31/3183 , G01R31/319 , G06F11/00
CPC分类号： G01R31/31908
摘要： A word of a test pattern is divided into blocks and stored in a storage device of a test pattern generator for testing a logic device. The test pattern blocks are sequentially provided to respective blocks of a pattern generator, which provides at respective outputs all of the blocks of a test pattern word at the same time. If a block of the pattern generator is faulty, or if another component of the test pattern generator corresponding to a block of the pattern generator is faulty, the respective block of each test pattern word can be provided to an unused block of the pattern generator, for providing the test patterns for testing the logic device without the need for reprogramming the test pattern blocks to be stored in the storage device. The data stored in the storage device identifies the position of each respective block of the test pattern words, for controlling the transferring of the test pattern blocks from the storage device to the pattern generator.
摘要翻译：测试模式的字被分成块并存储在用于测试逻辑设备的测试码型发生器的存储设备中。测试图案块被顺序地提供给模式生成器的各个块，它们在相应的输出端同时提供测试模式字的所有块。如果模式发生器的块有故障，或者如果与模式发生器的块相对应的测试码型发生器的另一个组件有故障，则可以将每个测试模式字的相应块提供给模式生成器的未使用块，用于提供用于测试逻辑器件的测试模式，而不需要重新编程要存储在存储设备中的测试模式块。存储在存储装置中的数据识别测试图案字的每个相应块的位置，用于控制将测试图案块从存储装置传送到图案生成器。

68. 发明授权

US4300234A Address pattern generator for testing a memory 失效
标题翻译：用于测试内存的地址模式生成器
公开(公告)号：US4300234A
公开(公告)日：1981-11-10
申请号：US83527
申请日：1979-10-10
申请人： Hiromi Maruyama , Takashi Tokuno , Masao Shimizu , Kohji Ishikawa , Naoaki Narumi , Osamu Ohguchi
发明人： Hiromi Maruyama , Takashi Tokuno , Masao Shimizu , Kohji Ishikawa , Naoaki Narumi , Osamu Ohguchi
IPC分类号： G06F11/22 , G01R31/3181 , G01R31/3183 , G11C8/00 , G11C29/10 , G11C29/56 , G01R31/28
CPC分类号： G11C29/56 , G01R31/31813
摘要： An address pattern generator for use in a test pattern generator for generating various patterns for testing semiconductor memories. A plurality of fixed registers for storing an initial value at the start of a test, a boundary value and an operand indicating the amount of change of an address are provided in common to at least two address operating circuits. The address operating circuits are each capable of taking therein the content of a desired one of the fixed registers. At least two output registers are provided, which are each capable of taking therein the operation result of a desired one of the address operating circuit. The contents of these output registers are supplied as addresses to a memory under test.
摘要翻译：一种用于测试图形发生器的地址模式发生器，用于产生用于测试半导体存储器的各种模式。多个固定寄存器用于在测试开始时存储初始值，边界值和指示地址变化量的操作数被共同地提供给至少两个地址操作电路。地址操作电路各自能够在其中接收期望的一个固定寄存器的内容。提供至少两个输出寄存器，每个输出寄存器能够在其中接收所需地址操作电路的操作结果。这些输出寄存器的内容作为地址提供给被测内存。

69. 发明授权

US4293950A Test pattern generating apparatus 失效
标题翻译：测试图案生成装置
公开(公告)号：US4293950A
公开(公告)日：1981-10-06
申请号：US26246
申请日：1979-04-02
申请人： Masao Shimizu , Takashi Tokuno , Kohji Ishikawa , Naoaki Narumi , Osamu Ohguchi
发明人： Masao Shimizu , Takashi Tokuno , Kohji Ishikawa , Naoaki Narumi , Osamu Ohguchi
IPC分类号： G01R31/3181 , G01R31/319 , G11C29/10 , G11C29/56 , G06F11/00 , G01R31/28
CPC分类号： G01R31/31921 , G11C29/10 , G11C29/56 , G01R31/31813
摘要： A test pattern generating apparatus in which a microprogram describing a test pattern to be generated is read for interpretation and execution, address and data patterns are generated by arithmetic operations and a memory control signal is produced, the address and data patterns and the memory control signal being applied to a memory under test. The address pattern is provided to an area inversion control signal generation section to produce an inversion control signal corresponding to the address pattern, by which the data pattern may be inverted and then outputted.
摘要翻译：读取描述要生成的测试图案的微程序的测试图形生成装置，用于解释和执行，地址和数据模式通过算术运算产生，并且产生存储器控制信号，地址和数据模式以及存储器控制信号被应用于被测记忆体。地址模式被提供给区域反转控制信号产生部分，以产生对应于地址模式的反转控制信号，由此可以将数据模式反转并输出。

70. 发明授权

US08730248B2 Multi-graphics processor system, graphics processor and data transfer method 有权
标题翻译：多图形处理器系统，图形处理器和数据传输方式
公开(公告)号：US08730248B2
公开(公告)日：2014-05-20
申请号：US11805165
申请日：2007-05-22
申请人： Nobuo Sasaki , Masao Shimizu
发明人： Nobuo Sasaki , Masao Shimizu
IPC分类号： G06F15/16 , G09G5/399 , G09G5/36
CPC分类号： G06T1/20 , G06F9/3879
摘要： A multi-graphics processor system includes a CPU; a first GPU connected to the CPU via an input/output interface; and a second GPU connected to the first GPU via a second-GPU interface. The first GPU is provided with a second-GPU bus for communicating the CPU and the second GPU via the second-GPU interface. The CPU communicates with the second GPU via the second-GPU bus after receiving a signal indicating the timing of the data communication.
摘要翻译：多图形处理器系统包括CPU; 通过输入/输出接口连接到CPU的第一个GPU; 以及经由第二GPU接口连接到第一GPU的第二GPU。第一GPU具有第二GPU总线，用于经由第二GPU接口来通信CPU和第二GPU。在接收到指示数据通信的定时的信号之后，CPU经由第二GPU总线与第二GPU进行通信。

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