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61. 发明授权

US06204527B1 Semiconductor memory device and method for producing same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US06204527B1
公开(公告)日：2001-03-20
申请号：US09201913
申请日：1998-11-30
申请人： Akira Sudo , Kazumasa Sunouchi , Akihiro Nitayama
发明人： Akira Sudo , Kazumasa Sunouchi , Akihiro Nitayama
IPC分类号： H01L2972
CPC分类号： H01L27/10867 , H01L29/945
摘要： A semiconductor memory device comprises: a semiconductor substrate; a semiconductor region of a first conductive type formed in the semiconductor substrate; a diffusion region of a second conductive type different from the first conductive type, the diffusion region being formed on the surface of the semiconductor region; a trench formed in the semiconductor substrate so as to be adjacent to the diffusion region; a capacitor insulator film formed on a portion of a side surface of the trench, which extends from a position at a predetermined depth of the trench to a bottom portion of the trench, and on a bottom surface of the trench; a storage node formed so that a surface of the storage node buried in the trench has the same depth as that of the predetermined depth; a first insulator film formed in a portion of the side surface of the trench above the position of the predetermined depth of the trench, the first insulator having a window in a region contacting the diffusion region; and a storage node electrode formed on the storage node so as to bury the trench, the uppermost surface of a region of the storage node electrode contacting the diffusion region via the window being formed of a mono-crystalline silicon region. Thus, it is possible to improve the charge holding characteristic of a memory cell without deteriorating the performance of a cell transistor.
摘要翻译：半导体存储器件包括：半导体衬底; 形成在半导体衬底中的第一导电类型的半导体区域; 与所述第一导电类型不同的第二导电类型的扩散区域，所述扩散区域形成在所述半导体区域的表面上; 形成在半导体衬底中以与扩散区相邻的沟槽; 形成在所述沟槽的侧表面的从所述沟槽的预定深度的位置延伸到所述沟槽的底部的位置的一部分上的电容器绝缘膜，以及所述沟槽的底表面; 形成为使得埋在沟槽中的存储节点的表面具有与预定深度相同的深度的存储节点; 第一绝缘体膜，形成在所述沟槽的所述预定深度的位置的所述沟槽的侧表面的一部分中，所述第一绝缘体在与所述扩散区接触的区域中具有窗口; 以及存储节点电极，形成在所述存储节点上，以便掩埋所述沟槽，所述存储节点电极的与扩散区域接触的区域的最上表面经由由单晶硅区域形成的窗口。因此，可以改善存储单元的电荷保持特性，而不会降低单元晶体管的性能。

62. 发明授权

US5998821A Dynamic ram structure having a trench capacitor 失效
标题翻译：具有沟槽电容器的动态压头结构
公开(公告)号：US5998821A
公开(公告)日：1999-12-07
申请号：US859851
申请日：1997-05-21
申请人： Katsuhiko Hieda , Akihiro Nitayama
发明人： Katsuhiko Hieda , Akihiro Nitayama
IPC分类号： H01L27/108 , H01L21/8242 , H01L29/94 , H01L29/76 , H01L31/119
CPC分类号： H01L27/10861 , H01L29/945
摘要： A dynamic RAM structure comprises a trench formed on a p-type Si substrate, a capacitor oxide film formed in such a manner as to cover an inner wall of the trench, a polysilicon film being a capacitor storage node electrode for burying the trench covered with the capacitor oxide film, an epitaxial Si layer formed on the Si substrate including an upper portion of the polysilicon film, a source/drain layer of a MOS transistor formed in the epitaxial Si layer, and a surface strap diffusion layer formed in the epitaxial Si layer in such a manner as to come in contact with the source/drain layer.
摘要翻译：动态RAM结构包括形成在p型Si衬底上的沟槽，以覆盖沟槽内壁的方式形成的电容器氧化膜;多晶硅膜，其是用于埋入覆盖有沟槽的沟槽的电容器存储节点电极电容器氧化膜，形成在包括多晶硅膜的上部的Si衬底上的外延Si层，形成在外延Si层中的MOS晶体管的源极/漏极层和形成在外延Si中的表面带扩散层以与源极/漏极层接触的方式。

63. 发明授权

US5578847A Dynamic semiconductor memory device with higher density bit line/word line layout 失效
标题翻译：具有更高密度位线/字线布局的动态半导体存储器件
公开(公告)号：US5578847A
公开(公告)日：1996-11-26
申请号：US402570
申请日：1995-03-13
申请人： Masami Aoki , Takashi Yamada , Hiroshi Takato , Tohru Ozaki , Katsuhiko Hieda , Akihiro Nitayama
发明人： Masami Aoki , Takashi Yamada , Hiroshi Takato , Tohru Ozaki , Katsuhiko Hieda , Akihiro Nitayama
IPC分类号： H01L21/822 , G11C11/401 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10817 , H01L27/0207 , H01L27/10852 , H01L27/10882 , Y10S257/907
摘要： A plurality of bit line contacts provided on one bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL and a plurality of bit line contacts provided on an adjacent bit line BL are arranged on every other one of spaces each provided between every adjacent two of word lines WL which is different from the space in which a corresponding one of the bit line contacts formed on the former bit line is arranged.
摘要翻译：设置在一个位线BL上的多个位线触点布置在每个设置在每个相邻的两个字线WL之间的每隔一个空间中，并且设置在相邻位线BL上的多个位线触点彼此布置每个相邻的两个字线WL之间的空间不同于其中布置在前位线上形成的位线触点中的相应一个的空间。

64. 发明授权

US5488242A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5488242A
公开(公告)日：1996-01-30
申请号：US156931
申请日：1993-11-24
申请人： Kazumasa Sunouchi , Hiroshi Takato , Tohru Ozaki , Naoko Okabe , Katsuhiko Hieda , Fumio Horiguchi , Akihiro Nitayama , Takashi Yamada , Kouji Hasimoto , Satosi Inoue
发明人： Kazumasa Sunouchi , Hiroshi Takato , Tohru Ozaki , Naoko Okabe , Katsuhiko Hieda , Fumio Horiguchi , Akihiro Nitayama , Takashi Yamada , Kouji Hasimoto , Satosi Inoue
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/78 , H01L27/02 , H01L29/68 , H01L29/92
CPC分类号： H01L27/10829
摘要： In a DRAM having a structure in which a storage node electrode is formed via an insulator film in a trench formed in a memory cell region to thereby form a capacitor, and in which the storage node electrode is connected in the source/drain regions of a MOSFET through a storage node contact formed in a part of the insulator film, the trench is disposed so as to deviate widthwise in a channel region of the MOSFET, so that the distance between adjacent element regions is reduced without causing misalignment of masks used in the formation of the storage node contact, thereby to provide a miniaturized high-reliability DRAM. In addition, the storage node contact and the trench can be formed in large size.
摘要翻译：在具有通过形成在存储单元区域中的沟槽中的绝缘膜形成存储节点电极从而形成电容器的结构的DRAM中，并且其中存储节点电极连接在源极/漏极区域 MOSFET通过形成在绝缘膜的一部分中的存储节点接触，沟槽设置成在MOSFET的沟道区域中宽度偏离，使得相邻元件区域之间的距离减小，而不会导致在形成存储节点接触，从而提供小型化的高可靠性DRAM。此外，存储节点接触和沟槽可以形成为大尺寸。

65. 发明授权

US5358808A Exposure mask, method of manufacturing the same, and exposure method using the same 失效
标题翻译：曝光掩模，其制造方法和使用其的曝光方法
公开(公告)号：US5358808A
公开(公告)日：1994-10-25
申请号：US94442
申请日：1993-07-21
申请人： Akihiro Nitayama , Makoto Nakase , Kouji Hishimoto , Hirotsugu Wada
发明人： Akihiro Nitayama , Makoto Nakase , Kouji Hishimoto , Hirotsugu Wada
IPC分类号： G03F1/00 , G03F9/00
CPC分类号： G03F1/29
摘要： An exposure mask for lithography, a method of manufacturing the same, and an exposure method using the same are disclosed. A light-transmitting opening of the exposure mask has a main light-transmitting region located in the middle of the opening and having a first optical path length, and phase shift regions adjacent to a light-shielding layer and having a second optical path length, different from the first optical path length. Light transmitted through each phase shift region interferes with light transmitted through the main light-transmitting region at the edges of the light-transmitting opening, thus enabling a sharp photo-intensity distribution of total transmitted light to be obtained. As a result, the resolution of the exposure mask is improved.
摘要翻译：公开了一种用于光刻的曝光掩模，其制造方法和使用其的曝光方法。曝光掩模的透光开口具有位于开口中间并具有第一光程长度的主透光区域和与遮光层相邻并且具有第二光程长度的相移区域，不同于第一光路长度。透过各相移区域的光干涉透过透光开口边缘的主透光区域的光，从而能够得到总透光的尖锐的光强度分布。结果，改善了曝光掩模的分辨率。

66. 发明授权

US5311050A Semiconductor vertical MOSFET inverter circuit 失效
标题翻译：半导体垂直MOSFET逆变电路
公开(公告)号：US5311050A
公开(公告)日：1994-05-10
申请号：US796602
申请日：1991-11-22
申请人： Akihiro Nitayama , Koji Sakui
发明人： Akihiro Nitayama , Koji Sakui
IPC分类号： H01L21/8238 , H01L27/092 , H01L29/423 , H01L29/78
CPC分类号： H01L27/092 , H01L29/4236
摘要： A semiconductor device including a semiconductor substrate 1 and at least one first column-shaped semiconductor layer 10 of a first channel type formed on semiconductor substrate 1 in order of first, second and third regions, and having a side surface. At least one second column-shaped semiconductor layer 11 of a second channel type is selectively laminated on first semiconductor layer 10 in order of first, second and third regions, and having a side surface. A gate insulation film 8 is formed on the side surfaces of first semiconductor layer 10 and second semiconductor layer 11. A gate electrode 9 is formed on the insulation film 8 extending to an external portion of first semiconductor layer 10. A first source layer 2 and first drain layer 4 are respectively formed in the first and third regions of first semiconductor layer 10. A second source layer 7 and second drain layer 5 are respectively formed in the first and third regions of semiconductor layer 11. An input terminal 14 is connected to gate electrode 9 to lead out to the exterior of first semiconductor layer 10. An output terminal 15 is connected to second drain layer 5 formed on and in low-resistance contact with first drain layer. A first power source terminal 16 is connected to first source layer 2 of first semiconductor layer 10, and a second power source terminal 17 is connected to second source layer 7.
摘要翻译：一种半导体器件，包括半导体衬底1和形成在半导体衬底1上的第一沟道型的至少一个第一柱状半导体层10，其具有第一，第二和第三区域的顺序并且具有侧表面。第二沟道型的至少一个第二列状半导体层11按照第一，第二和第三区域的顺序选择性层压在第一半导体层10上，并具有侧面。在第一半导体层10和第二半导体层11的侧表面上形成栅极绝缘膜8.在延伸到第一半导体层10的外部的绝缘膜8上形成栅电极9.第一源极层2和第一漏极层4分别形成在第一半导体层10的第一和第三区域中。第二源极层7和第二漏极层5分别形成在半导体层11的第一和第三区域中。输入端子14连接到栅极电极9引出到第一半导体层10的外部。输出端子15连接到形成在第一漏极层上并与第一漏极层低电阻接触的第二漏极层5。第一电源端子16连接到第一半导体层10的第一源极层2，第二电源端子17连接到第二源极层7。

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