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61. 发明授权

US06593659B2 Dual damascene structure with carbon containing SiO2 dielectric layers 失效
标题翻译：具有含SiO 2介电层的双镶嵌结构
公开(公告)号：US06593659B2
公开(公告)日：2003-07-15
申请号：US09837683
申请日：2001-04-18
申请人： Takashi Yokoyama
发明人： Takashi Yokoyama
IPC分类号： H01L2348
CPC分类号： H01L21/76829 , H01L21/02126 , H01L21/02131 , H01L21/02134 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/02282 , H01L21/31633 , H01L21/76801 , H01L21/76807 , H01L21/7681 , H01L21/76834 , H01L2221/1036
摘要： A semiconductor device with dual damascene structure is provided, which suppresses propagation delay of signals without using complicated processes. The device comprises a semiconductor substrate having a lower wiring layer and electronic elements, a first dielectric layer on the substrate, a second dielectric layer on the first dielectric layer made of carbon-containing SiO2, a third dielectric layer on the second dielectric layer, a fourth dielectric layer on the third dielectric layer made of carbon containing SiO2, the first and second dielectric layers having a via hole, the third dielectric layer having a recess overlapping the via hole, the recess formed to communicate with the via hole, a metal plug formed in the via hole in contact with the lower wiring layer or the electronic elements in the substrate, a metal wiring layer formed in the recess, and a fourth dielectric layer to cover the metal wiring layer.
摘要翻译：提供了具有双镶嵌结构的半导体器件，其抑制信号的传播延迟而不使用复杂的工艺。该器件包括具有下布线层和电子元件的半导体衬底，衬底上的第一介电层，由含碳SiO 2制成的第一电介质层上的第二电介质层，第二电介质层上的第三介电层，所述第三电介质层由含有SiO 2的碳制成的第三电介质层，所述第一和第二电介质层具有通孔，所述第三电介质层具有与所述通孔重叠的凹部，所述凹部与所述通孔连通，金属插塞形成在与下布线层或基板中的电子元件接触的通孔中，形成在凹部中的金属布线层和覆盖金属布线层的第四介电层。

62. 发明授权

US06479407B2 Semiconductor device and process for producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06479407B2
公开(公告)日：2002-11-12
申请号：US09770114
申请日：2001-01-23
申请人： Takashi Yokoyama , Tatsuya Usami
发明人： Takashi Yokoyama , Tatsuya Usami
IPC分类号： H01L2131
CPC分类号： H01L21/76834 , H01L21/76801 , H01L21/76802 , H01L21/76814 , H01L21/76826 , H01L21/76828 , H01L21/76831 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interlayer insulation film containing a dielectric component represented by a chemical formula having a Si—E bond or a Si—CH3 bond is formed on a substrate. Next, a photoresist is formed on the interlayer insulation film. The photoresist is then formed into a form of a contact hole. Thereafter, dry-etching of the interlayer insulation film is conducted by use of the photoresist as a mask. Subsequently, the photoresist is removed, and the interlayer insulation film is exposed to nitrogen plasma and hydrogen plasma, for example.
摘要翻译：在基板上形成含有由具有Si-E键或Si-CH3键的化学式表示的电介质成分的层间绝缘膜。接着，在层间绝缘膜上形成光致抗蚀剂。然后将光致抗蚀剂形成为接触孔的形式。此后，通过使用光致抗蚀剂作为掩模进行层间绝缘膜的干法蚀刻。随后，除去光致抗蚀剂，并且例如将层间绝缘膜暴露于氮等离子体和氢等离子体。

63. 发明授权

US06303982B2 Semiconductor device 失效
公开(公告)号：US06303982B2
公开(公告)日：2001-10-16
申请号：US09771617
申请日：2001-01-30
申请人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjo , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsuro Matsumoto
发明人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjo , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsuro Matsumoto
IPC分类号： H01L23495
CPC分类号： H01L23/3107 , H01L23/4951 , H01L23/49555 , H01L23/49558 , H01L23/49568 , H01L23/49586 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/105 , H01L29/0657 , H01L2224/0401 , H01L2224/05554 , H01L2224/05599 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4554 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48599 , H01L2224/48699 , H01L2224/48799 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2224/85205 , H01L2224/8592 , H01L2224/92147 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L2225/1088 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01039 , H01L2924/01043 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01092 , H01L2924/0132 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/15738 , H01L2924/15747 , H01L2924/1576 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/3511 , H05K1/144 , H05K1/181 , H05K3/3421 , H01L2924/00012 , H01L2924/00 , H01L2924/01026 , H01L2924/3512 , H01L2924/0695 , H01L2224/85399
摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the “Lead-On-Chip” or “Chip-On-Lead” structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

64. 发明授权

US06284661B1 Method and apparatus for producing a wafer 失效
标题翻译：用于制造晶片的方法和装置
公开(公告)号：US06284661B1
公开(公告)日：2001-09-04
申请号：US08833125
申请日：1997-04-04
申请人： Takashi Yokoyama , Kazuma Yamamoto , Masato Yamamoto , Takahiro Mishima , Go Matsuda , Shigeki Itou
发明人： Takashi Yokoyama , Kazuma Yamamoto , Masato Yamamoto , Takahiro Mishima , Go Matsuda , Shigeki Itou
IPC分类号： B28D500
CPC分类号： C30B33/00 , Y10T83/2109
摘要： A method and an apparatus for cutting a wafer from a crystalline ingot, by directing a stream or streams of etching gas at the crystalline ingot in a vacuum. Waste in cutting can be greatly minimized and the work environment can also be kept clean. Further, excellent surface smoothness can be realized on the cut wafers.
摘要翻译：一种用于通过在真空中将结晶锭的流或蚀刻气体流引导而从晶体晶片切割晶片的方法和装置。切割废料可以大大减少，工作环境也可以保持清洁。此外，可以在切割的晶片上实现优异的表面平滑度。

65. 发明授权

US06245665B1 Semiconductor device and method of fabricating the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06245665B1
公开(公告)日：2001-06-12
申请号：US09458243
申请日：1999-12-09
申请人： Takashi Yokoyama
发明人： Takashi Yokoyama
IPC分类号： H01L214763
CPC分类号： H01L21/76829 , H01L21/02126 , H01L21/02131 , H01L21/02134 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/02282 , H01L21/31633 , H01L21/76801 , H01L21/76807 , H01L21/7681 , H01L21/76834 , H01L2221/1036
摘要： A semiconductor device equipped with the dual damascene structure that is provided, which suppresses the propagation delay of signals effectively without using any complicated processes. The device is comprised of (i) a semiconductor substrate having a lower wiring layer and electronic elements; (ii) a first interlayer dielectric layer formed on the substrate; (iii) a second interlayer dielectric layer formed on the first interlayer dielectric layer, the second interlayer dielectric layer being made of carbon-containing SiO2; (iv) a third interlayer dielectric layer formed on the second interlayer dielectric layer; (v) a fourth interlayer dielectric layer formed on the third interlayer dielectric layer, the fourth interlayer dielectric layer being made of carbon-containing SiO2; (vi) the first and second interlayer dielectric layers having a via hole penetrating therethrough; (vii) the third interlayer dielectric layer having a recess overlapping with the via hole, the recess being formed to communicate with the via hole; (viii) a metal plug formed in the via hole to be contacted with the lower wiring layer or the electronic elements in the substrate; (ix) a metal wiring layer formed in the recess; and (x) a fourth interlayer dielectric layer formed on the third interlayer dielectric layer to cover the metal wiring layer.
摘要翻译：配备有提供的双镶嵌结构的半导体器件，其有效地抑制信号的传播延迟，而不使用任何复杂的过程。该器件包括（i）具有下布线层和电子元件的半导体衬底; （ii）形成在所述基板上的第一层间电介质层; （iii）形成在所述第一层间电介质层上的第二层间电介质层，所述第二层间电介质层由含碳SiO 2制成; （iv）形成在所述第二层间电介质层上的第三层间电介质层; （v）形成在所述第三层间电介质层上的第四层间介电层，所述第四层间介电层由含碳SiO 2构成; （vi）所述第一和第二层间电介质层具有贯穿其中的通孔; （vii）具有与所述通孔重叠的凹部的所述第三层间电介质层，所述凹部形成为与所述通孔连通; （viii）形成在所述通孔中以与所述下布线层或所述基板中的所述电子元件接触的金属插塞; （ix）形成在所述凹部中的金属布线层; 和（x）形成在第三层间电介质层上以覆盖金属布线层的第四层间介电层。

66. 发明授权

US06225196B1 High electron mobility transistor and method of fabricating the same 失效
标题翻译：高电子迁移率晶体管及其制造方法
公开(公告)号：US06225196B1
公开(公告)日：2001-05-01
申请号：US09521781
申请日：2000-03-09
申请人： Takashi Yokoyama
发明人： Takashi Yokoyama
IPC分类号： H01L2120
CPC分类号： H01L29/66431 , H01L29/1604 , H01L29/7786
摘要： There is provided a field effect transistor including (a) an amorphous semiconductor layer made of amorphous silicon hydride containing impurities doped therein, (b) a semiconductor layer made of single crystal silicon having electron affinity greater than that of the amorphous silicon hydride, formed on the amorphous semiconductor layer, (c) a gate insulating film formed on the semiconductor layer, and (d) a gate electrode formed on the gate insulating film. The amorphous semiconductor layer and the semiconductor layer cooperate with each other to thereby form a potential well at a junction therebetween. The above mentioned field effect transistor utilizes a difference in electron affinity between the amorphous semiconductor layer and the semiconductor layer to thereby make it possible to operate at a higher speed because carriers are not influenced by scattering of doped ions. In addition, a structure of a single crystal silicon layer formed on an amorphous silicon layer, which would be difficult to fabricate by epitaxial growth, can be accomplished by means of ion implantation, and can be operated in accordance with the operation principle of an ordinary MOS transistor.
摘要翻译：提供了一种场效应晶体管，其包括（a）由非晶硅氢化物制成的非晶半导体层，其中掺杂有杂质，（b）由单晶硅制成的半导体层，其电子亲和力大于非晶硅氢化物的电子亲和力，形成在所述非晶半导体层，（c）形成在所述半导体层上的栅极绝缘膜，以及（d）形成在所述栅极绝缘膜上的栅电极。非晶半导体层和半导体层彼此配合，从而在它们之间的接合处形成势阱。上述场效应晶体管利用了非晶半导体层与半导体层之间的电子亲和力差，从而使得可以以更高的速度工作，因为载流子不受掺杂离子的散射的影响。此外，通过离子注入可以实现通过外延生长难以制造的在非晶硅层上形成的单晶硅层的结构，并且可以根据普通的操作原理来操作 MOS晶体管。

67. 发明授权

US6100580A Semiconductor device having all outer leads extending from one side of a resin member 失效
标题翻译：具有从树脂构件的一侧延伸的所有外部引线的半导体装置
公开(公告)号：US6100580A
公开(公告)日：2000-08-08
申请号：US167736
申请日：1998-10-07
申请人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjo , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsuro Matsumoto
发明人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjo , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsuro Matsumoto
IPC分类号： H01L21/44 , H01L21/48 , H01L21/50 , H01L23/31 , H01L23/495 , H01L25/10 , H01L29/06 , H05K1/14 , H05K1/18 , H05K3/34
CPC分类号： H01L24/32 , H01L23/3107 , H01L23/4951 , H01L23/49555 , H01L23/49558 , H01L23/49568 , H01L23/49586 , H01L24/05 , H01L24/06 , H01L25/105 , H01L29/0657 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/05599 , H01L2224/05624 , H01L2224/06136 , H01L2224/16 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/48724 , H01L2224/48799 , H01L2224/73215 , H01L2224/85205 , H01L2224/8592 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01043 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01092 , H01L2924/0132 , H01L2924/014 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/15738 , H01L2924/15747 , H01L2924/1576 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/3511 , H05K1/144 , H05K1/181 , H05K3/3421 , Y10T29/49121
摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.
摘要翻译：由于半导体芯片尺寸大，高集成度和加速度，所以难以将半导体芯片与包装中的引线组合在一起。鉴于这种困难，已经采用称为半导体和引线堆叠和封装的称为“片上引线”或“引线芯片”结构的封装结构。在该结构的封装中，根据本发明，内引线和半导体芯片的前端部之间的间隙比除引导端部和半导体芯片之外的内引线部分之间的间隙宽，从而减小杂散容量，提高信号传输速率和减少电气噪声。

68. 发明授权

US5988602A Variable venturi carburetor 失效
标题翻译：可变文丘里化油器
公开(公告)号：US5988602A
公开(公告)日：1999-11-23
申请号：US992531
申请日：1997-12-17
申请人： Takashi Yokoyama , Takashi Udono
发明人： Takashi Yokoyama , Takashi Udono
IPC分类号： F02M7/17 , F02M17/04 , F02M9/06
CPC分类号： F02M17/04 , Y10S261/56 , Y10S261/68
摘要： A variable venturi carburetor, which is part of an intake system of an internal combustion engine, includes structural features which allow an air intake path of the carburetor to be shortened, and which allow the size of air chambers of the carburetor to be reduced. A piston valve is composed of a plate-shaped valve and a tubular portion. The plate-shaped valve is guided by a pair of grooves provide in sidewalls of the intake path. The tubular portion is attached to one side of the plate-shaped valve near a center of the side of the plate-shaped valve. The tubular portion has a rectangular or square cross-section. Each side of the rectangular cross section is shorter than the internal diameter of the intake path. A flange is attached to an upper end of the piston valve. The flange is of a reduced diameter and facilitates connection of the piston valve to a diaphragm. Since the diameter of the flange is also less than the diameter of the intake path, a vacuum chamber and an atmosphere chamber of the carburetor can be reduced in size.
摘要翻译：作为内燃机的进气系统的一部分的可变文丘里化油器包括允许化油器的进气路径缩短的结构特征，并且允许化油器的空气室的尺寸减小。活塞阀由板状阀和管状部构成。板形阀由在进气通道的侧壁中提供的一对槽引导。管状部分附接在板状阀的靠近板状阀侧的中心的一侧。管状部分具有矩形或正方形的横截面。矩形横截面的每一侧比进气道的内径短。法兰连接到活塞阀的上端。该法兰具有减小的直径，并且便于将活塞阀连接到隔膜。由于凸缘的直径也小于进气通道的直径，所以可以减小化油器的真空室和气氛室的尺寸。

69. 发明授权

US5981315A Semiconductor device 失效
公开(公告)号：US5981315A
公开(公告)日：1999-11-09
申请号：US166532
申请日：1998-10-06
申请人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjoh , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsurou Matsumoto
发明人： Gen Murakami , Kunihiro Tsubosaki , Masahiro Ichitani , Kunihiko Nishi , Ichiro Anjoh , Asao Nishimura , Makoto Kitano , Akihiro Yaguchi , Sueo Kawai , Masatsugu Ogata , Syuuji Eguchi , Hiroyoshi Kokaku , Masanori Segawa , Hiroshi Hozoji , Takashi Yokoyama , Noriyuki Kinjo , Aizo Kaneda , Junichi Saeki , Shozo Nakamura , Akio Hasebe , Hiroshi Kikuchi , Isamu Yoshida , Takashi Yamazaki , Kazuyoshi Oshima , Tetsurou Matsumoto
IPC分类号： H01L21/52 , H01L23/31 , H01L23/495 , H01L23/50 , H01L25/10 , H01L29/06 , H05K1/14 , H05K1/18 , H05K3/34 , H01L21/44
CPC分类号： H01L23/3107 , H01L23/4951 , H01L23/49555 , H01L23/49558 , H01L23/49568 , H01L23/49586 , H01L24/32 , H01L24/49 , H01L25/105 , H01L29/0657 , H01L2224/0401 , H01L2224/05554 , H01L2224/05599 , H01L2224/16245 , H01L2224/29111 , H01L2224/2919 , H01L2224/2929 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4554 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48599 , H01L2224/48699 , H01L2224/48799 , H01L2224/49171 , H01L2224/73215 , H01L2224/73265 , H01L2224/85205 , H01L2224/8592 , H01L2224/92147 , H01L2225/1005 , H01L2225/1029 , H01L2225/107 , H01L2225/1088 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01011 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01039 , H01L2924/01043 , H01L2924/01045 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01092 , H01L2924/0132 , H01L2924/014 , H01L2924/07802 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/15738 , H01L2924/15747 , H01L2924/1576 , H01L2924/181 , H01L2924/1815 , H01L2924/3025 , H01L2924/3511 , H05K1/144 , H05K1/181 , H05K3/3421
摘要： As the semiconductor chip is large-sized, highly integrated and speeded up, it becomes difficult to pack the semiconductor chip together with leads in a package. In view of this difficulty, there has been adopted the package structure called the "Lead-On-Chip" or "Chip-On-Lead" structure in which the semiconductor and the leads are stacked and packed. In the package of this structure, according to the present invention, the gap between the leading end portions of the inner leads and the semiconductor chip is made wider than that between the inner lead portions except the leading end portions and the semiconductor chip thereby to reduce the stray capacity, to improve the signal transmission rate and to reduce the electrical noises.

70. 发明授权

US5931676A Dental attachment 失效
标题翻译：牙齿贴附
公开(公告)号：US5931676A
公开(公告)日：1999-08-03
申请号：US702491
申请日：1996-08-27
申请人： Yoshinobu Honkura , Takashi Yokoyama , Hideki Fujii , Yoshinobu Tanaka
发明人： Yoshinobu Honkura , Takashi Yokoyama , Hideki Fujii , Yoshinobu Tanaka
IPC分类号： A61C8/00 , A61C13/235
CPC分类号： A61C8/0081 , A61C13/235
摘要： A dental magnetic attachment, which is embedded in the denture base so as to face a soft magnetic keeper 103 and attract the keeper by magnetic force, comprising at least three yokes which are plates and made of soft magnetic material, and at least two pieces of magnet which have the magnetization direction parallel to the thickness. In the example the attachment comprises a central yoke 10, the magnet 1, the magnet 2, the outer yoke 11, and the outer yoke 12. The invention is characterized by a magnet arrangement in which like poles of the magnet 1 and the magnet 2 faces each other. Because of it mutually independent two magnetic circuits are formed and they offer strong attractive force which is two times larger than that of existing ones in a compact volume required for dental attachment. Furthermore, corrosion resistance and wear resistance are improved by covering the attracting face of the magnet 1, 2 with spacers made of non-magnetic material and covering the whole attachment with the cap made of non-magnetic material except the attracting face of the attachment.
摘要翻译： PCT No.PCT / JP95 / 02685第 371日期1997年12月12日 102（e）日期1997年12月12日PCT 1995年12月26日PCT PCT。第WO96 / 19951号公报日期1996年7月4日牙科磁性附件嵌入义齿底座以面对软磁性保持器103并通过磁力吸引保持器，其包括至少三个由软磁性材料制成的磁轭，至少两片具有磁化方向平行于厚度的磁体。在该示例中，附件包括中心磁轭10，磁体1，磁体2，外磁轭11和外磁轭12.本发明的特征在于磁体装置，其中磁体1和磁体2的相同磁极面对面由于它相互独立，形成了两个磁路，并且它们具有强的吸引力，这是在牙齿附着所需的紧凑体积中比现有的两倍大的吸引力。此外，通过用由非磁性材料制成的间隔物覆盖磁体1,2的吸附面，并且除了附件的吸附面以外的非磁性材料制成的盖子覆盖整个附件，提高了耐腐蚀性和耐磨性。

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