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61. 发明授权

US5792706A Interlevel dielectric with air gaps to reduce permitivity 失效
标题翻译：具有气隙的层间电介质以降低介电常数
公开(公告)号：US5792706A
公开(公告)日：1998-08-11
申请号：US658457
申请日：1996-06-05
申请人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
IPC分类号： H01L21/768 , H01L23/522 , H01L21/31
CPC分类号： H01L21/7682 , H01L23/5222 , H01L2924/0002
摘要： A reduced permittivity interlevel dielectric is provided. The interlevel dielectric is formed between two levels of interconnect. The interlevel dielectric comprises a first dielectric layer formed from a TEOS source deposited on a first level interconnect. The first dielectric contains air gaps at spaced intervals across the first dielectric. A second dielectric, preferably from a silane source is deposited upon said first dielectric. A second interconnect level is then placed on the second dielectric.
摘要翻译：提供了一种降低介电常数的层间电介质。层间电介质形成在两层互连之间。层间电介质包括由沉积在第一层互连上的TEOS源形成的第一介质层。第一电介质以间隔开的间隔跨越第一电介质。第二电介质，优选由硅烷源沉积在所述第一电介质上。然后将第二互连电平放置在第二电介质上。

62. 发明授权

US5767012A Method of forming a recessed interconnect structure 失效
标题翻译：形成凹陷互连结构的方法
公开(公告)号：US5767012A
公开(公告)日：1998-06-16
申请号：US660674
申请日：1996-06-05
申请人： H. Jim Fulford, Jr. , Basab Bandyopadhyay , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： H. Jim Fulford, Jr. , Basab Bandyopadhyay , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/316 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L23/52 , H01L23/522 , H01L27/04 , H01L21/283
CPC分类号： H01L23/5222 , H01L21/768 , H01L2924/0002
摘要： A method of forming a recessed interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween. The method of forming a recessed interconnect structure comprises forming a substantially coplanar set of the first conductors upon a semiconductor substrate, depositing a first dielectric layer on said first conductors, forming a trench in the first dielectric layer, depositing a conductive material in the trench, planarizing the conductive material an upper surface of the conductive material is substantially coplanar with an upper surface of the first dielectric, etching the conductive material until the upper surface of the conductive material is displaced below the upper surface of the first dielectric, forming a second dielectric on the conductive material and the first dielectric layer.
摘要翻译：提供一种形成凹陷互连结构的方法。互连结构包括多个级别的导体，其中一个层上的导体相对于另一层上的导体交错。在密集间隔的互连区域中，插入的导体被拉至不同的高度级以减小互连之间的电容耦合。通过交错密集图案化区域中的每隔一个互连线，互连能够承载更大量的电流并且在其间具有最小的电容耦合。形成凹陷互连结构的方法包括在半导体衬底上形成基本共面的第一导体组，在第一导体上沉积第一电介质层，在第一电介质层中形成沟槽，在沟槽中沉积导电材料，对导电材料进行平面化，导电材料的上表面与第一电介质的上表面基本共面，蚀刻导电材料，直到导电材料的上表面位于第一电介质的上表面以下，形成第二电介质在导电材料和第一介电层上。

63. 发明授权

US5766803A Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization 失效
公开(公告)号：US5766803A
公开(公告)日：1998-06-16
申请号：US659165
申请日：1996-06-05
申请人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
IPC分类号： H01L21/033 , H01L21/3105 , H01L21/768 , G03F9/00
CPC分类号： H01L21/0334 , H01L21/31051 , H01L21/76819
摘要： A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.

64. 发明授权

US5733798A Mask generation technique for producing an integrated circuit with optimal polysilicon interconnect layout for achieving global planarization 失效
公开(公告)号：US5733798A
公开(公告)日：1998-03-31
申请号：US655247
申请日：1996-06-05
申请人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
IPC分类号： H01L21/3105 , H01L21/768 , H01L23/528 , H01L21/44 , H01L21/48
CPC分类号： H01L21/76819 , H01L21/31053 , H01L23/528 , H01L2924/0002
摘要： A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.

65. 发明授权

US5717242A Integrated circuit having local interconnect for reduing signal cross coupled noise 失效
公开(公告)号：US5717242A
公开(公告)日：1998-02-10
申请号：US633473
申请日：1996-04-17
申请人： Mark W. Michael , Robert Dawson , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L27/11 , H01L29/76 , H01L29/94
CPC分类号： H01L23/5222 , H01L21/76895 , H01L23/5286 , H01L27/11 , H01L2924/0002
摘要： An integrated circuit is provided having an improved interconnect structure. The interconnect structure includes a power-coupled local interconnect which is always retained at VDD or VSS (i.e., ground) level. The local interconnect resides a dielectric-spaced distance below critical runs of overlying interconnect. The powered local interconnect serves to sink noise transients from the critical conductors to ensure that circuits connected to the conductors do not inoperably function. Accordingly, the local interconnect extends along a substantial portion of the conductor length, and is either wider or narrower than the conductor under which it extends. The local interconnect can either be polysilicon, doped polysilicon, polycide, refractory metal silicide, or multi-level refractory metal.

66. 发明授权

US06326298B1 Substantially planar semiconductor topography using dielectrics and chemical mechanical polish 有权
标题翻译：使用电介质和化学机械抛光的基本平面的半导体形貌
公开(公告)号：US06326298B1
公开(公告)日：2001-12-04
申请号：US09513293
申请日：2000-02-25
申请人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
发明人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L214763
CPC分类号： H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a multilevel interconnect structure having a globally planarized upper surface. Dielectrics are deposited upon a semiconductor to minimize pre-existing disparities in topographical height and to create an upper surface topography having a polish rate greater than that of lower regions. Subsequent chemical mechanical polishing produces a substantially planar surface.
摘要翻译：一种用于形成具有全局平坦化的上表面的多层互连结构的方法。电介质沉积在半导体上以最小化形貌高度上的先前存在的差异并产生具有比下部区域更高的抛光速率的上表面形貌。随后的化学机械抛光产生基本平坦的表面。

67. 发明授权

US6153833A Integrated circuit having interconnect lines separated by a dielectric having a capping layer 有权
标题翻译：具有由具有封盖层的电介质隔开的互连线的集成电路
公开(公告)号：US6153833A
公开(公告)日：2000-11-28
申请号：US148098
申请日：1998-09-04
申请人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
发明人： Robert Dawson , Mark W. Michael , Basab Bandyopadhyay , H. Jim Fulford, Jr. , Fred N. Hause , William S. Brennan
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/312 , H01L21/3205 , H01L21/768 , H01L21/822 , H01L23/52 , H01L23/522 , H01L23/528 , H01L27/04 , H05K1/03
CPC分类号： H01L23/5222 , H01L23/5226 , H01L23/5283 , H01L2924/0002
摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. Accordingly, a space between conductors on one level is directly above or directly below a conductor within another level. The staggered interconnect lines are advantageously used in densely spaced regions to reduce the interlevel and intralevel capacitance. Furthermore, an interlevel and an intralevel dielectric structure includes optimally placed low K dielectrics which exist in critical spaced areas to minimize capacitive coupling and propagation delay problems. The low K dielectric, according to one embodiment, includes a capping dielectric which is used to prevent corrosion on adjacent metallic conductors, and serves as an etch stop when conductors are patterned. The capping dielectric further minimizes the overall intrinsic stress of the resulting intralevel and interlevel dielectric structure.
摘要翻译：提供了一种改进的多级互连结构。互连结构包括多个级别的导体，其中一个层上的导体相对于另一层上的导体交错。因此，在一个级别上的导体之间的空间位于另一层内的导体的正上方或正下方。交错的互连线有利地用于密集间隔的区域以减少层间和层间电容。此外，层间和层间介质结构包括存在于临界间隔区域中的最佳放置的低K电介质，以最小化电容耦合和传播延迟问题。根据一个实施例的低K电介质包括封盖电介质，其用于防止相邻金属导体上的腐蚀，并且当导体被图案化时用作蚀刻停止层。封盖电介质进一步最小化所得到的层间和层间电介质结构的整体固有应力。

68. 发明授权

US6150721A Integrated circuit which uses a damascene process for producing staggered interconnect lines 有权
标题翻译：集成电路，其使用镶嵌工艺来产生交错的互连线
公开(公告)号：US6150721A
公开(公告)日：2000-11-21
申请号：US132454
申请日：1998-08-11
申请人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
发明人： Basab Bandyopadhyay , H. Jim Fulford, Jr. , Robert Dawson , Fred N. Hause , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/768 , H01L23/522 , H01L23/48
CPC分类号： H01L21/76807 , H01L21/768 , H01L23/5222 , H01L2924/0002
摘要： An improved multilevel interconnect structure is provided. The interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. In densely spaced interconnect areas, interposed conductors are drawn to dissimilar elevational levels to lessen the capacitive coupling between the interconnects. By staggering every other interconnect line in the densely patterned areas, the interconnects are capable of carrying a larger amount of current with minimal capacitive coupling therebetween.
摘要翻译：提供了一种改进的多级互连结构。互连结构包括多个级别的导体，其中一个层上的导体相对于另一层上的导体交错。在密集间隔的互连区域中，插入的导体被拉至不同的高度级以减小互连之间的电容耦合。通过交错密集图案化区域中的每隔一个互连线，互连能够承载更大量的电流并且在其间具有最小的电容耦合。

69. 发明授权

US6091149A Dissolvable dielectric method and structure 有权
标题翻译：溶解介电法和结构
公开(公告)号：US6091149A
公开(公告)日：2000-07-18
申请号：US251059
申请日：1999-02-18
申请人： Fred N. Hause , Basab Bandyopadhyay , Robert Dawson , H. Jim Fulford, Jr. , Mark W. Michael , William S. Brennan
发明人： Fred N. Hause , Basab Bandyopadhyay , Robert Dawson , H. Jim Fulford, Jr. , Mark W. Michael , William S. Brennan
IPC分类号： H01L21/768 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/7682
摘要： A fabrication process is provided that produces an air gap dielectric in which a multi-level interconnect structure is formed upon a temporary supporting material. The temporary material is subsequently dissolved away leaving behind an intralevel and an interlevel dielectric comprised of air. In one embodiment of the invention, a first interconnect level is formed on a barrier layer. A temporary support material is then formed over the first interconnect level and a second level of interconnect is formed on the temporary support material. Prior to formation of the second interconnect level, a plurality of pillar openings are formed in the temporary material and filled with a conductive material. In addition to providing a contact between the first and second level of interconnects, the pillars provide mechanical support for the second interconnect level. The temporary material is dissolved in a solution that attacks the temporary material but leaves the interconnect material and pillar material intact. In one embodiment of the invention, a passivation layer is formed on the second interconnect level prior to dissolving the temporary material. The air gap dielectric can be used with more than two levels of interconnect, if desired.
摘要翻译：提供一种制造工艺，其产生气隙电介质，其中在临时支撑材料上形成多层互连结构。随后将临时材料溶解掉，留下由空气组成的层间和层间电介质。在本发明的一个实施例中，在阻挡层上形成第一互连电平。然后在第一互连层上形成临时支撑材料，并在临时支撑材料上形成第二层互连。在形成第二互连级别之前，在临时材料中形成多个柱状开口并填充有导电材料。除了在第一和第二级互连之间提供接触之外，支柱为第二互连电平提供机械支撑。临时材料溶解在攻击临时材料的溶液中，但使互连材料和支柱材料完好无损。在本发明的一个实施例中，在溶解临时材料之前，在第二互连层上形成钝化层。如果需要，气隙电介质可以与多于两个级别的互连一起使用。

70. 发明授权

US6049134A Mask generation technique for producing an integrated circuit with optimal metal interconnect layout for achieving global planarization 失效
标题翻译：用于制造具有最佳金属互连布局以实现全局平坦化的集成电路的掩模生成技术
公开(公告)号：US6049134A
公开(公告)日：2000-04-11
申请号：US15821
申请日：1998-01-29
申请人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
发明人： Mark W. Michael , Robert Dawson , Fred N. Hause , Basab Bandyopadhyay , H. Jim Fulford, Jr. , William S. Brennan
IPC分类号： H01L21/033 , H01L21/3105 , H01L21/768 , H01L29/72 , H01L21/283
CPC分类号： H01L21/0334 , H01L21/31051 , H01L21/76819
摘要： A photolithography mask derivation process is provided for improving the overall planarity of interlevel dielectric deposited upon conductors formed by the derived photolithography mask. The photolithography mask is derived such that non-operational conductors are spaced a minimum distance from each other and from operational conductors to present a regular spaced arrangement of conductors upon which a dielectric layer can be deposited and readily planarized using, for example, chemical-mechanical polishing techniques. The resulting interlevel dielectric upper surface is globally planarized to an even elevational level across the entire semiconductor topography. The operational conductors are dissimilar from non-operational conductors in that the operational conductors are connected within a circuit path of an operational integrated circuit. Non-operational conductors are not connected within the integrated circuit path and generally are floating or are connected to a power supply. The non-operational conductors thereby do not contribute to the integrated circuit functionality other than to provide structural planarity to the overlying interlevel dielectric. The mask derivation process is applicable to either a metal interconnect photolithography mask or a polysilicon interconnect photolithography mask.
摘要翻译：提供了一种光刻掩模衍生方法，用于改善沉积在由衍生的光刻掩模形成的导体上的层间电介质的整体平面性。衍生出光刻掩模，使得非操作导体彼此间隔开最小距离和与操作导体间隔开的规则间隔排列的导体，其上可使用例如化学机械的电介质层沉积并容易地平坦化抛光技术。所得的层间电介质上表面在整个半导体形貌上被全局平坦化到均匀的高度。操作导体与非操作导体不相似，因为操作导体连接在可操作的集成电路的电路中。非操作导体不在集成电路路径内连接，并且通常浮动或连接到电源。因此，非操作导体对集成电路功能没有贡献，而不是为覆盖的层间电介质提供结构平面性。掩模推导方法适用于金属互连光刻掩模或多晶硅互连光刻掩模。

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