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    • 63. 发明申请
    • Group III nitride semiconductor stacked structure and production method thereof
    • III族氮化物半导体层叠结构及其制造方法
    • US20070080369A1
    • 2007-04-12
    • US11543950
    • 2006-10-06
    • Hiromitsu Sakai
    • Hiromitsu Sakai
    • H01L33/00
    • H01L33/12H01L33/007H01L33/16
    • An object of the present invention is to provide a group III nitride semiconductor stacked structure having a high-quality A-plane group III nitride semiconductor layer on an R-plane sapphire substrate. The inventive group III nitride semiconductor stacked structure comprises a substrate composed of R-plane sapphire (α-Al2O3), a buffer layer composed of aluminum gallium nitride (AlxGa1−xN: 0≦X≦1) formed on said substrate and an underlying layer composed of an A-plane group III nitride semiconductor (AlxGayInzN1−aMa: 0≦X≦1, 0≦Y≦1, 0≦Z≦1, and X+Y+Z=1; wherein, M represents a group V element other than nitrogen (N), and 0≦a≦1) formed on said buffer layer, wherein the pit density of the surface of said underlying layer is 1×1010 cm−2 or less.
    • 本发明的目的是提供一种在R平面蓝宝石衬底上具有高质量A面III族氮化物半导体层的III族氮化物半导体层叠结构。 本发明的III族氮化物半导体层叠结构包括由R平面蓝宝石(α-Al 2 O 3 N 3)构成的衬底,由氮化镓铝(Al 形成在所述基板上的由下列层构成的基底层:由A面III族氮化物半导体构成的基底层(Al < 在&lt; z&gt; N&lt; 1&gt; 1&lt;&lt;&lt;&lt; <= 1,0 <= Y <= 1,0 <= Z <= 1,X + Y + Z = 1;其中,M表示氮(N)以外的V族元素,0 < = 1),其中所述下层的表面的凹坑密度为1×10 -2 cm -2以下。
    • 65. 发明授权
    • Gate driver for MOS control semiconductor devices
    • 用于MOS控制半导体器件的栅极驱动器
    • US06703874B2
    • 2004-03-09
    • US10436265
    • 2003-05-13
    • Shuji KatohShigeta UedaHiromitsu SakaiTakashi IkimiTomomichi Ito
    • Shuji KatohShigeta UedaHiromitsu SakaiTakashi IkimiTomomichi Ito
    • H03K300
    • H02M1/32H03K17/0828H03K17/107
    • A gate driver is provided for controlling a gate voltage of each of a plurality of MOS control semiconductor devices, such as IGBTs or metal oxide MOS transistors, of a semiconductor power converter in which said MOS control semiconductors are connected in series with each other, the gate driver includes a power supply line having a higher potential than a gate potential on each of said MOS control semiconductor devices when in steady ON state, and an arrangement for supplying a current from the power source line to the gate of each of said MOS control semiconductors to increase the gate voltage of the MOS control semiconductor devices when a potential difference between said power supply line and an emitter of each of said MOS control semiconductors is constant and when a collector voltage of the MOS control semiconductor device exceeds a predetermined value under ON state of the MOS control semiconductor device.
    • 提供一种栅极驱动器,用于控制半导体功率转换器中的多个MOS控制半导体器件(例如IGBT或金属氧化物MOS晶体管)中的每一个的栅极电压,其中所述MOS控制半导体彼此串联连接, 栅极驱动器包括在稳定导通状态时具有比每个所述MOS控制半导体器件上的栅极电位高的电位的电源线,以及用于将电流从电源线提供给每个所述MOS控制的栅极的装置 半导体,当所述电源线和所述MOS控制半导体的每一个的发射极之间的电位差恒定时,以及当所述MOS控制半导体器件的集电极电压在ON时超过预定值时,增加所述MOS控制半导体器件的栅极电压 MOS控制半导体器件的状态。
    • 66. 发明授权
    • Semiconductor power converting apparatus
    • 半导体电力转换装置
    • US06380796B2
    • 2002-04-30
    • US09838470
    • 2001-04-20
    • Hiromitsu SakaiHidetoshi AizawaShuji KatohRyuji IyotaniMasahiro Nagasu
    • Hiromitsu SakaiHidetoshi AizawaShuji KatohRyuji IyotaniMasahiro Nagasu
    • H03K17687
    • H02M1/08H03K4/00H03K17/166H03K17/168
    • A semiconductor power converting apparatus includes a semiconductor element for controlling a current flowing between a collector and an emitter in response to a gate condition, a driving device connected to the gate, for driving the gate in response to a drive signal entered thereinto, a voltage applying device for applying both a forward bias and a reverse bias to the gate so as to set the emitter of the semiconductor element to a neutral potential, and a voltage dividing device for dividing a voltage appearing between the collector and the emitter of the semiconductor element, in which the drive signal is under OFF state, a voltage produced based upon the divided voltage by the voltage dividing device is applied to the gate, and the gate voltage is controlled in response to the voltage appearing between the collector and the emitter of the semiconductor element, thereby reducing the snubbed loss.
    • 半导体功率转换装置包括:半导体元件,用于响应于栅极条件控制在集电极和发射极之间流动的电流;连接到栅极的驱动装置,用于响应输入的驱动信号驱动栅极;电压 施加装置,用于向栅极施加正向偏压和反向偏压,以将半导体元件的发射极设置为中性电位;以及分压装置,用于分割半导体元件的集电极和发射极之间的电压 ,其中驱动信号处于OFF状态,将通过分压装置分压的电压产生的电压施加到栅极,并且响应于集电极和发射极之间出现的电压来控制栅极电压 半导体元件,从而减少缓冲损耗。
    • 67. 发明授权
    • Semiconductor power converting apparatus
    • 半导体电力转换装置
    • US06242968B1
    • 2001-06-05
    • US09642816
    • 2000-08-22
    • Hiromitsu SakaiHidetoshi AizawaShuji KatohRyuji IyotaniMasahiro Nagasu
    • Hiromitsu SakaiHidetoshi AizawaShuji KatohRyuji IyotaniMasahiro Nagasu
    • H03K17687
    • H02M1/08H03K4/00H03K17/166H03K17/168
    • A semiconductor power converting apparatus includes a semiconductor element for controlling a current flowing between a collector and an emitter in response to a gate condition, a driving device connected to the gate, for driving the gate in response to a drive signal entered thereinto, a voltage applying device for applying both a forward bias and a reverse bias to the gate so as to set the emitter of the semiconductor element to a neutral potential, and a voltage dividing device for dividing a voltage appearing between the collector and the emitter of the semiconductor element, in which the drive signal is under OFF state, a voltage produced based upon the divided voltage by the voltage dividing device is applied to the gate, and the gate voltage is controlled in response to the voltage appearing between the collector and the emitter of the semiconductor element, thereby reducing the snubbed loss.
    • 半导体功率转换装置包括:半导体元件,用于响应于栅极条件控制在集电极和发射极之间流动的电流;连接到栅极的驱动装置,用于响应输入的驱动信号驱动栅极;电压 施加装置,用于向栅极施加正向偏压和反向偏压,以将半导体元件的发射极设置为中性电位;以及分压装置,用于分割半导体元件的集电极和发射极之间的电压 ,其中驱动信号处于OFF状态,将通过分压装置分压的电压产生的电压施加到栅极,并且响应于集电极和发射极之间出现的电压来控制栅极电压 半导体元件,从而减少缓冲损耗。
    • 68. 发明授权
    • Method for controlling electroless plating bath
    • 控制化学镀浴的方法
    • US4353933A
    • 1982-10-12
    • US204046
    • 1980-11-04
    • Ken ArakiHiromitsu SakaiYutaka Sugiura
    • Ken ArakiHiromitsu SakaiYutaka Sugiura
    • C23C18/16G05D21/02B05D1/18
    • G05D21/02C23C18/1617C23C18/1683C23C18/36C23C18/40
    • A method and an apparatus for controlling an electroless plating bath such as an electroless nickel plating bath such that the bath is useable for an extended period of time without remaking are disclosed. The method comprises the steps of:continuously or intermittently measuring the concentration of at least one consumable ingredient of the electroless plating bath, andautomatically adding to the plating bath a first replenishing composition essentially consisting of the consumable ingredient after detecting that the measured value has reached a predetermined concentration; whilecontinuously or intermittently measuring one physical property of the electroless plating bath to determine the degree of aging of the bath, andautomatically discharging a predetermined volume of the plating solution and automatically adding to the plating bath a second replenishing composition containing unconsumable ingredients in an amount essentially corresponding to the lost amount by the discharging after detecting that the measured value has reached a predetermined value of the physical property.
    • 公开了一种用于控制化学镀浴的方法和装置,例如化学镀镍浴,使得浴可长时间使用而不需要重新制造。 该方法包括以下步骤:连续或间歇地测量化学镀浴中至少一种可消耗成分的浓度,并且在检测到测量值已达到之后,自动向电镀槽中添加基本由消耗成分组成的第一补充组合物 预定浓度; 同时连续地或间歇地测量化学镀浴的一个物理性质以确定浴的老化程度,并自动排出预定体积的镀液,并自动地向镀液中添加含有不可消耗的成分的第二补充组合物 基本上对应于在检测到测量值达到物理特性的预定值之后通过放电的损失量。