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61. 发明申请

US20050127417A1 Field effect transistor with etched-back gate dielectric 有权
标题翻译：具有蚀刻背栅电介质的场效应晶体管
公开(公告)号：US20050127417A1
公开(公告)日：2005-06-16
申请号：US10730892
申请日：2003-12-10
申请人： Katherine Saenger , Rajarao Jammy , Vijay Narayanan
发明人： Katherine Saenger , Rajarao Jammy , Vijay Narayanan
IPC分类号： H01L21/28 , H01L21/283 , H01L21/311 , H01L21/314 , H01L21/336 , H01L21/8238 , H01L29/51 , H01L29/94
CPC分类号： H01L21/31111 , H01L21/28194 , H01L21/31105 , H01L21/31122 , H01L29/517
摘要： A method for making an ultrathin high-k gate dielectric for use in a field effect transistor is provided. The method involves depositing a high-k gate dielectric material on a substrate and forming an ultrathin high-k dielectric by performing a thinning process on the high-k gate dielectric material. The process used to thin the high-k dielectric material can include at least one of any number of processes including wet etching, dry etching (including gas cluster ion beam (GCIB) processing), and hybrid damage/wet etching. In addition to the above, the present invention relates to an ultrathin high-k gate dielectric made for use in a field-effect transistor made by the above method.
摘要翻译：提供一种用于制造用于场效应晶体管的超薄高k栅极电介质的方法。该方法包括在衬底上沉积高k栅极电介质材料，并通过对高k栅极电介质材料进行稀化处理来形成超薄高介电常数。用于稀薄高k介电材料的方法可以包括湿法蚀刻，干法蚀刻（包括气体簇离子束（GCIB）处理）和混合损伤/湿式蚀刻的任何数量的工艺中的至少一种。除了上述之外，本发明涉及一种用于通过上述方法制造的场效应晶体管的超薄高k栅极电介质。

62. 发明申请

US20050118757A1 Method for integration of silicide contacts and silicide gate metals 失效
标题翻译：硅化物触点和硅化物栅极金属的集成方法
公开(公告)号：US20050118757A1
公开(公告)日：2005-06-02
申请号：US10725851
申请日：2003-12-02
申请人： Cyril Cabral , Jakub Kedzierski , Victor Ku , Christian Lavoie , Vijay Narayanan , An Steegen
发明人： Cyril Cabral , Jakub Kedzierski , Victor Ku , Christian Lavoie , Vijay Narayanan , An Steegen
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L27/092 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/78
CPC分类号： H01L21/823835
摘要： A CMOS silicide metal integration scheme that allows for the incorporation of silicide contacts (S/D and gates) and metal silicide gates using a self-aligned process (salicide) as well as one or more lithography steps is provided. The integration scheme of the present invention minimizes the complexity and cost associated in fabricating a CMOS structure containing silicide contacts and silicide gate metals.
摘要翻译：提供了允许使用自对准工艺（自对准硅化物）以及一个或多个光刻步骤并入硅化物触点（S / D和栅极）和金属硅化物栅极的CMOS硅化物金属集成方案。本发明的集成方案最小化了制造包含硅化物触点和硅化物栅极金属的CMOS结构所涉及的复杂性和成本。

63. 发明授权

US09236314B2 High-K/metal gate stack using capping layer methods, IC and related transistors 有权
标题翻译：高K /金属栅极堆叠采用封盖层法，IC及相关晶体管
公开(公告)号：US09236314B2
公开(公告)日：2016-01-12
申请号：US13433659
申请日：2012-03-29
申请人： Michael P. Chudzik , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
发明人： Michael P. Chudzik , Naim Moumen , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri
IPC分类号： H01L21/8238 , H01L29/49 , H01L29/51
CPC分类号： H01L21/823857 , H01L21/823842 , H01L29/4966 , H01L29/4975 , H01L29/517
摘要： Methods, IC and related transistors using capping layer with high-k/metal gate stacks are disclosed. In one embodiment, the IC includes a first type transistor having a gate electrode including a first metal, a second metal and a first dielectric layer, the first dielectric layer including oxygen; a second type transistor separated from the first type transistor by an isolation region, the second type transistor having a gate electrode including the second metal having a work function appropriate for the second type transistor and the first dielectric layer; and wherein the gate electrode of the first type transistor includes a rare earth metal between the first metal and the second metal and the gate electrode of the second type transistor includes a second dielectric layer made of an oxide of the rare earth metal.
摘要翻译：公开了使用具有高k /金属栅极叠层的封盖层的IC和相关晶体管。在一个实施例中，IC包括具有包括第一金属，第二金属和第一介电层的栅电极的第一类型晶体管，第一介电层包括氧; 通过隔离区与第一型晶体管分离的第二类型晶体管，第二类型晶体管具有包括具有适合于第二类型晶体管和第一介电层的功函数的第二金属的栅电极; 并且其中所述第一类型晶体管的栅极包括在所述第一金属和所述第二金属之间的稀土金属，并且所述第二类型晶体管的栅电极包括由所述稀土金属的氧化物制成的第二电介质层。

64. 发明授权

US09041082B2 Engineering multiple threshold voltages in an integrated circuit 有权
标题翻译：在集成电路中工程化多个阈值电压
公开(公告)号：US09041082B2
公开(公告)日：2015-05-26
申请号：US12899691
申请日：2010-10-07
申请人： Catherine Anne Dubourdieu , Martin Michael Frank , Vijay Narayanan
发明人： Catherine Anne Dubourdieu , Martin Michael Frank , Vijay Narayanan
IPC分类号： H01L21/02 , H01L21/28 , H01L21/8234 , H01L29/78
CPC分类号： H01L29/516 , H01L21/28291 , H01L21/823412 , H01L21/823462 , H01L27/088 , H01L29/78 , H01L29/7843
摘要： An integrated circuit and method for forming an integrated circuit. There are at least three field-effect transistors with at least two of the field-effect transistors having the same electrically insulating material which is ferroelectric when unstrained or is capable of being ferroelectric when strain is induced. It is optional for the third field-effect transistor to have an electrically insulating material which is ferroelectric when unstrained or is capable of being ferroelectric when strain is induced. The at least three field-effect transistors are strained to varying amounts so that each of the three field-effect transistors has a threshold voltage, Vt, which is different from the Vt of the two other field-effect transistors.
摘要翻译：一种用于形成集成电路的集成电路和方法。存在至少三个场效应晶体管，其中至少两个场效应晶体管具有相同的电绝缘材料，其在未应变时为铁电体，或者当诱发应变时能够为铁电体。对于第三场效应晶体管来说，具有电绝缘材料是可选的，其在未应变时为铁电体，或者当诱发应变时能够是铁电体。至少三个场效应晶体管被应变到不同的量，使得三个场效应晶体管中的每一个具有不同于另外两个场效应晶体管的Vt的阈值电压Vt。

65. 发明授权

US08786030B2 Gate-last fabrication of quarter-gap MGHK FET 失效
标题翻译：最后制造四分之一MGHK FET
公开(公告)号：US08786030B2
公开(公告)日：2014-07-22
申请号：US13570388
申请日：2012-08-09
申请人： Takashi Ando , Kisik Choi , Vijay Narayanan , Tenko Yamashita , Junli Wang
发明人： Takashi Ando , Kisik Choi , Vijay Narayanan , Tenko Yamashita , Junli Wang
IPC分类号： H01L21/02
CPC分类号： H01L29/517 , H01L21/28079 , H01L21/28088 , H01L29/4958 , H01L29/4966 , H01L29/66545
摘要： A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack.
摘要翻译：通过栅极最终制造形成的四分之一间隙p型场效应晶体管（PFET）包括形成在硅衬底上的栅极堆叠，所述栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于高k电介质层上方的栅极金属层，所述栅极金属层包括氮化钛并且具有约20埃的厚度; 以及形成在栅极堆叠上的金属接触。通过栅极最后制造形成的四分之一间隙n型场效应晶体管（NFET）包括形成在硅衬底上的栅极堆叠，该栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于所述高k电介质层上方的第一栅极金属层，所述第一栅极金属层包括氮化钛; 以及形成在栅极堆叠上的金属接触。

66. 发明授权

US08735243B2 FET device with stabilized threshold modifying material 有权
标题翻译：具有稳定阈值修饰材料的FET器件
公开(公告)号：US08735243B2
公开(公告)日：2014-05-27
申请号：US11834641
申请日：2007-08-06
申请人： Matthew W. Copel , Bruce B. Doris , Vijay Narayanan , Yun-Yu Wang
发明人： Matthew W. Copel , Bruce B. Doris , Vijay Narayanan , Yun-Yu Wang
IPC分类号： H01L21/8238 , H01L21/335 , H01L21/336 , H01L21/8234 , H01L29/51 , H01L21/28
CPC分类号： H01L29/513 , H01L21/28026 , H01L21/28229 , H01L21/823857 , H01L29/517 , H01L29/665 , H01L29/6653 , H01L29/7833
摘要： A method for fabricating an FET device is disclosed. The FET device has a gate insulator with a high-k dielectric portion, and a threshold modifying material. The method introduces a stabilizing material into the gate insulator in order to hinder one or more metals from the threshold modifying material to penetrate across the high-k portion of the gate insulator. The introduction of the stabilizing material may involve disposing a stabilizing agent over a layer which contains an oxide of the one or more metals. A stabilizing material may also be incorporated into the high-k dielectric. Application of the method may lead to FET devices with unique gate insulator structures.
摘要翻译：公开了一种用于制造FET器件的方法。 FET器件具有具有高k电介质部分的栅极绝缘体和阈值修饰材料。该方法将稳定材料引入栅极绝缘体中，以便阻止来自阈值修饰材料的一种或多种金属穿过栅极绝缘体的高k部分。稳定材料的引入可以包括在包含一种或多种金属的氧化物的层上设置稳定剂。稳定材料也可以并入高k电介质中。该方法的应用可能导致具有独特栅极绝缘体结构的FET器件。

67. 发明授权

US08722548B2 Structures and techniques for atomic layer deposition 有权
标题翻译：原子层沉积的结构和技术
公开(公告)号：US08722548B2
公开(公告)日：2014-05-13
申请号：US12890051
申请日：2010-09-24
申请人： Shintaro Aoyama , Robert D. Clark , Steven P. Consiglio , Marinus Hopstaken , Hemanth Jagannathan , Paul Charles Jamison , Gert Leusink , Barry Paul Linder , Vijay Narayanan , Cory Wajda
发明人： Shintaro Aoyama , Robert D. Clark , Steven P. Consiglio , Marinus Hopstaken , Hemanth Jagannathan , Paul Charles Jamison , Gert Leusink , Barry Paul Linder , Vijay Narayanan , Cory Wajda
IPC分类号： H01L21/469
CPC分类号： H01L21/02181 , B32B15/04 , B32B2457/14 , C23C16/40 , C23C16/401 , C23C16/405 , C23C16/45527 , C23C16/45531 , C23C16/56 , H01L21/022 , H01L21/0228 , H01L21/02318 , H01L21/28194 , H01L29/517
摘要： In one exemplary embodiment, a method includes: forming at least one first monolayer of first material on a surface of a substrate by performing a first plurality of cycles of atomic layer deposition; thereafter, annealing the formed at least one first monolayer of first material under a first inert atmosphere at a first temperature between about 650° C. and about 900° C.; thereafter, forming at least one second monolayer of second material by performing a second plurality of cycles of atomic layer deposition, where the formed at least one second monolayer of second material at least partially overlies the annealed at least one first monolayer of first material; and thereafter, annealing the formed at least one second monolayer of second material under a second inert atmosphere at a second temperature between about 650° C. and about 900° C.
摘要翻译：在一个示例性实施例中，一种方法包括：通过执行原子层沉积的第一多个循环，在衬底的表面上形成至少一个第一材料的第一单层; 之后，在第一惰性气氛下，在约650℃至约900℃的第一温度下退火所形成的至少一个第一材料的第一单层; 此后，通过执行第二多个原子层沉积循环形成第二材料的至少一个第二单层，其中所形成的至少一个第二单层的第二材料至少部分地覆盖所述退火的至少一个第一单层第一材料; 然后在第二惰性气氛下，在约650℃和约900℃之间的第二温度下对所形成的至少一个第二单层第二材料进行退火。

68. 发明授权

US08420473B2 Replacement gate devices with barrier metal for simultaneous processing 失效
标题翻译：具有隔离金属的替换门装置用于同时处理
公开(公告)号：US08420473B2
公开(公告)日：2013-04-16
申请号：US12960586
申请日：2010-12-06
申请人： Takashi Ando , Michael P. Chudzik , Siddarth A. Krishnan , Unoh Kwon , Vijay Narayanan
发明人： Takashi Ando , Michael P. Chudzik , Siddarth A. Krishnan , Unoh Kwon , Vijay Narayanan
IPC分类号： H01L21/8238 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823842 , H01L29/165 , H01L29/4966 , H01L29/51 , H01L29/66545 , H01L29/66606 , H01L29/7848
摘要： A method of simultaneously fabricating n-type and p type field effect transistors can include forming a first replacement gate having a first gate metal layer adjacent a gate dielectric layer in a first opening in a dielectric region overlying a first active semiconductor region. A second replacement gate including a second gate metal layer can be formed adjacent a gate dielectric layer in a second opening in a dielectric region overlying a second active semiconductor region. At least portions of the first and second gate metal layers can be stacked in a direction of their thicknesses and separated from each other by at least a barrier metal layer. The NFET resulting from the method can include the first active semiconductor region, the source/drain regions therein and the first replacement gate, and the PFET resulting from the method can include the second active semiconductor region, source/drain regions therein and the second replacement gate.
摘要翻译：同时制造n型和p型场效应晶体管的方法可以包括在覆盖第一有源半导体区域的电介质区域中的第一开口中形成具有与栅极电介质层相邻的第一栅极金属层的第一替代栅极。包括第二栅极金属层的第二替代栅极可以在覆盖在第二有源半导体区域上的电介质区域中的第二开口中邻近栅极电介质层形成。第一和第二栅极金属层的至少一部分可以沿其厚度的方向堆叠并且通过至少阻挡金属层彼此分离。由该方法产生的NFET可以包括第一有源半导体区域，其中的源极/漏极区域和第一替换栅极，并且由该方法产生的PFET可以包括第二有源半导体区域，其中的源/漏区域和第二替换门。

69. 发明申请

US20120299123A1 Gate-Last Fabrication of Quarter-Gap MGHK FET 失效
标题翻译：最近制造四分之一间隙MGHK FET
公开(公告)号：US20120299123A1
公开(公告)日：2012-11-29
申请号：US13570388
申请日：2012-08-09
申请人： Takashi Ando , Kisik Choi , Vijay Narayanan , Tenko Yamashita , Junli Wang
发明人： Takashi Ando , Kisik Choi , Vijay Narayanan , Tenko Yamashita , Junli Wang
IPC分类号： H01L29/78
CPC分类号： H01L29/517 , H01L21/28079 , H01L21/28088 , H01L29/4958 , H01L29/4966 , H01L29/66545
摘要： A quarter-gap p-type field effect transistor (PFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a gate metal layer located over the high-k dielectric layer, the gate metal layer including titanium nitride and having a thickness of about 20 angstroms; and a metal contact formed over the gate stack. A quarter-gap n-type field effect transistor (NFET) formed by gate-last fabrication includes a gate stack formed on a silicon substrate, the gate stack including: a high-k dielectric layer located on the silicon substrate; and a first gate metal layer located over the high-k dielectric layer, the first gate metal layer including titanium nitride; and a metal contact formed over the gate stack.
摘要翻译：通过栅极最终制造形成的四分之一间隙p型场效应晶体管（PFET）包括形成在硅衬底上的栅极堆叠，所述栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于高k电介质层上方的栅极金属层，所述栅极金属层包括氮化钛并且具有约20埃的厚度; 以及形成在栅极堆叠上的金属接触。通过栅极最后制造形成的四分之一间隙n型场效应晶体管（NFET）包括形成在硅衬底上的栅极堆叠，该栅极堆叠包括：位于硅衬底上的高k电介质层; 以及位于所述高k电介质层上方的第一栅极金属层，所述第一栅极金属层包括氮化钛; 以及形成在栅极堆叠上的金属接触。

70. 发明申请

US20120292677A1 FERROELECTRIC SEMICONDUCTOR TRANSISTOR DEVICES HAVING GATE MODULATED CONDUCTIVE LAYER 有权
标题翻译：具有门控调制导电层的电磁半导体晶体管器件
公开(公告)号：US20120292677A1
公开(公告)日：2012-11-22
申请号：US13108340
申请日：2011-05-16
申请人： Catherine A. Dubourdieu , David J. Frank , Martin M. Frank , Vijay Narayanan , Paul M. Solomon , Thomas N. Theis
发明人： Catherine A. Dubourdieu , David J. Frank , Martin M. Frank , Vijay Narayanan , Paul M. Solomon , Thomas N. Theis
IPC分类号： H01L29/772
CPC分类号： H01L29/4232 , H01L29/42316 , H01L29/812
摘要： Ferroelectric semiconductor switching devices are provided, including field effect transistor (FET) devices having gate stack structures formed with a ferroelectric layer disposed between a gate contact and a thin conductive layer (“quantum conductive layer”) . The gate contact and ferroelectric layer serve to modulate an effective work function of the thin conductive layer. The thin conductive layer with the modulated work function is coupled to a semiconductor channel layer to modulate current flow through the semiconductor and achieve a steep sub-threshold slope.
摘要翻译：提供了铁电半导体开关器件，包括具有栅极叠层结构的场效应晶体管（FET）器件，栅极堆叠结构形成有设置在栅极接触和薄导电层（量子导电层）之间的铁电层。栅极接触和铁电层用于调制薄导电层的有效功函数。具有调制功函数的薄导电层耦合到半导体沟道层，以调制通过半导体的电流，并实现陡峭的子阈值斜率。

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