专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US08643409B2 Wide-range clock multiplier 有权
标题翻译：宽范围时钟倍频器
公开(公告)号：US08643409B2
公开(公告)日：2014-02-04
申请号：US13535690
申请日：2012-06-28
申请人： Yue Lu , Jared L. Zerbe
发明人： Yue Lu , Jared L. Zerbe
IPC分类号： H03B19/00
CPC分类号： H03K5/00006 , H03J2200/10 , H03L7/0802 , H03L7/083 , H03L7/085 , H03L7/099 , H03L7/0995 , H03L7/16 , H03L7/24 , H04L7/033
摘要： A variable-frequency input clock signal and a reference clock signal are compared during a frequency-compare interval to generate a value that indicates a ratio of their frequencies. The frequency-ratio value is then applied to configure a wide-range frequency-locking oscillator for operation with a narrowed input frequency range. Because the narrowed input frequency range is targeted to the input clock frequency, the wide-range oscillator is able to rapidly lock to a frequency multiple of the input clock frequency. Because the frequency-compare interval is also brief, an extremely fast-locking, clock-multiplying operation may be effected over a relatively wide range of input clock frequencies.
摘要翻译：在频率比较间隔期间比较可变频率输入时钟信号和参考时钟信号，以产生指示其频率比率的值。然后应用频率比值来配置宽范围的锁频振荡器，以便在输入频率范围变窄的情况下工作。由于变窄的输入频率范围针对输入时钟频率，因此宽频振荡器能够快速锁定到输入时钟频率的倍数。因为频率比较间隔也是短暂的，所以在相对宽的输入时钟频率范围内可以实现非常快速锁定的时钟相乘操作。

62. 发明授权

US08634452B2 Multiphase receiver with equalization circuitry 有权
标题翻译：具有均衡电路的多相接收器
公开(公告)号：US08634452B2
公开(公告)日：2014-01-21
申请号：US13491508
申请日：2012-06-07
申请人： Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
发明人： Jared L. Zerbe , Bruno W. Garlepp , Pak S. Chau , Kevin S. Donnelly , Mark A. Horowitz , Stefanos Sidiropoulos , Billy W. Garrett, Jr. , Carl W. Werner
IPC分类号： H04B17/00
CPC分类号： H04L25/4917 , G06F13/1678 , G06F13/4068 , G11C7/10 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1072 , G11C7/1078 , G11C7/1084 , G11C7/1087 , G11C7/22 , G11C8/10 , G11C11/56 , G11C27/02 , G11C2207/108 , H04L7/0331 , H04L7/0332 , H04L25/0272 , H04L25/0282 , H04L25/0296 , H04L25/0298 , H04L25/03006 , H04L25/03057 , H04L25/08 , H04L25/4902
摘要： An integrated circuit device includes a first circuit to receive bits associated with a first data cycle of an electrical input signal, operable to produce a decision regarding logic state of the bits associated with the first data cycle, and a second circuit to receive bits associated with a second cycle of the electrical input signal, to produce a decision regarding logic state of the bits associated with the second data cycle. An equalizing circuit compensates for intersymbol interference affecting the second circuit dependent on an output of the first circuit and compensates for intersymbol interference affecting the first circuit dependent on an output of a circuit other than the first circuit operable to produce a decision regarding logic state of bits of the electrical input signal.
摘要翻译：集成电路装置包括：第一电路，用于接收与电输入信号的第一数据周期相关联的位，可操作以产生关于与第一数据周期相关联的位的逻辑状态的判定;以及第二电路，用于接收与第电输入信号的第二周期，以产生关于与第二数据周期相关联的位的逻辑状态的判定。均衡电路根据第一电路的输出补偿影响第二电路的符号间干扰，并根据第一电路以外的电路的输出补偿影响第一电路的符号间干扰，该电路可操作以产生关于位的逻辑状态的判定的电气输入信号。

63. 发明申请

US20130128944A1 Selectable-tap Equalizer 有权
公开(公告)号：US20130128944A1
公开(公告)日：2013-05-23
申请号：US13729510
申请日：2012-12-28
申请人： Jared L. Zerbe , Vladimir M. Stojanovic , Fred F. Chen
发明人： Jared L. Zerbe , Vladimir M. Stojanovic , Fred F. Chen
IPC分类号： H04L25/03
CPC分类号： H04L25/03019 , H04B1/1081 , H04L7/0058 , H04L7/0087 , H04L7/0331 , H04L25/03025 , H04L25/03038 , H04L25/03057 , H04L25/03343 , H04L25/03885
摘要： A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

64. 发明申请

US20130002318A1 WIDE-RANGE CLOCK MULTIPLIER 有权
标题翻译：宽范围时钟累加器
公开(公告)号：US20130002318A1
公开(公告)日：2013-01-03
申请号：US13535690
申请日：2012-06-28
申请人： Yue Lu , Jared L. Zerbe
发明人： Yue Lu , Jared L. Zerbe
IPC分类号： H03L7/06
CPC分类号： H03K5/00006 , H03J2200/10 , H03L7/0802 , H03L7/083 , H03L7/085 , H03L7/099 , H03L7/0995 , H03L7/16 , H03L7/24 , H04L7/033
摘要： A variable-frequency input clock signal and a reference clock signal are compared during a frequency-compare interval to generate a value that indicates a ratio of their frequencies. The frequency-ratio value is then applied to configure a wide-range frequency-locking oscillator for operation with a narrowed input frequency range. Because the narrowed input frequency range is targeted to the input clock frequency, the wide-range oscillator is able to rapidly lock to a frequency multiple of the input clock frequency. Because the frequency-compare interval is also brief, an extremely fast-locking, clock-multiplying operation may be effected over a relatively wide range of input clock frequencies
摘要翻译：在频率比较间隔期间比较可变频率输入时钟信号和参考时钟信号，以产生指示其频率比率的值。然后应用频率比值来配置宽范围的锁频振荡器，以便在输入频率范围变窄的情况下工作。由于变窄的输入频率范围针对输入时钟频率，因此宽频振荡器能够快速锁定到输入时钟频率的倍数。由于频率比较间隔也很短，因此可以在相对宽的输入时钟频率范围内实现极快锁定的时钟相乘操作

65. 发明授权

US08311145B2 Bit-error rate in fixed line-rate systems 失效
标题翻译：固定线路速率系统中的误码率
公开(公告)号：US08311145B2
公开(公告)日：2012-11-13
申请号：US12437530
申请日：2009-05-07
申请人： Jared L. Zerbe , Vladimir M. Stojanovic
发明人： Jared L. Zerbe , Vladimir M. Stojanovic
IPC分类号： H04L27/00
CPC分类号： H04B17/373 , H04B17/21 , H04B17/26 , H04B17/309
摘要： A method of reducing bit-error rate is described. The method includes transmitting a data stream of data words at a line rate that is adjustable and equal to a positive delta value added to an established data rate. The method includes accumulating available time slots in the transmitted data stream, and selectively retransmitting a subset of the data words such that the retransmitted data words occupy no more than the accumulated available time slots.
摘要翻译：描述了一种降低误码率的方法。该方法包括以可调整且等于添加到建立的数据速率的正增量值的线速度传输数据字的数据流。该方法包括：在所发送的数据流中累积可用的时隙，并且选择性地重传数据字的子集，使得重传的数据字占用不超过累积的可用时隙。

66. 发明授权

US08305871B2 Crosstalk minimization in serial link systems 有权
标题翻译：串行链路系统中的串扰最小化
公开(公告)号：US08305871B2
公开(公告)日：2012-11-06
申请号：US12344086
申请日：2008-12-24
申请人： Jared L. Zerbe
发明人： Jared L. Zerbe
IPC分类号： H04J1/12
CPC分类号： H04L25/14
摘要： Described are methods and circuits for reducing the error-inducing effects of crosstalk. Communication circuits in accordance with some embodiments adjust the phase of transmitted “aggressor” data to misalign transmitted signals from the perspective of “victim” channels. This misalignment moves the noise artifacts cross coupled to the victim channel away from sensitive sample times in the victim data, and consequently reduces the net effects of aggressor crosstalk on neighboring victim channels. Some embodiments reduce the effects of crosstalk by introducing static timing offsets to one or a plurality of aggressor transmitters, one or a plurality of victim transmitters, or some combination of aggressor and victim transmitters. Other embodiments dynamically alter the relative timing of aggressor and victim transmitters.
摘要翻译：描述了用于减少串扰的误差诱导效应的方法和电路。根据一些实施例的通信电路调整发射的攻击者数据的相位，以从受害者信道的角度对准发送的信号。这种未对准使得与受害者信道交叉耦合的噪声伪影远离受害者数据中的敏感采样时间，并且因此降低了侵入者串扰对相邻受害信道的净影响。一些实施例通过向一个或多个侵略者发射机，一个或多个受害者发射机或侵略者和受害者发射机的某些组合引入静态定时偏移来减少串扰的影响。其他实施例动态地改变攻击者和受害者发射机的相对定时。

67. 发明授权

US08139675B2 Multi-tone system with oversampled precoders 失效
标题翻译：具有过采样预编码器的多音系统
公开(公告)号：US08139675B2
公开(公告)日：2012-03-20
申请号：US12907937
申请日：2010-10-19
申请人： Vladimir M. Stojanovic , Amir Amirkhany , Jared L. Zerbe
发明人： Vladimir M. Stojanovic , Amir Amirkhany , Jared L. Zerbe
IPC分类号： H04L27/00
CPC分类号： H04L25/03343 , H04L27/2637
摘要： A multi-tone system includes a data transmission circuit with an interface for receiving a data stream for transmission, a data steam splitter that splits the data stream to produce multiple substreams and a plurality of parallel data preparation circuits. Each data preparation circuit prepares a respective substream for transmission and generates a respective sub-channel signal. At least a first data preparation circuit of the plurality of parallel data preparation circuits includes a first analog filter for filtering a first substream. The first analog filter operates at a sample rate greater than the respective symbol rate of the first substream. The first analog filter provides pre-emphasis of the respective sub-channel signal and attenuation of signals outside of a respective band of frequencies corresponding to the respective sub-channel signal. The data transmission circuit also includes a combiner for combining respective sub-channel signals to generate a data transmission signal.
摘要翻译：多音系统包括具有用于接收用于传输的数据流的接口的数据传输电路，分割数据流以产生多个子流的数据蒸汽分配器和多个并行数据准备电路。每个数据准备电路准备相应的子流进行传输，并产生相应的子信道信号。多个并行数据准备电路的至少第一数据准备电路包括用于对第一子流进行滤波的第一模拟滤波器。第一模拟滤波器以大于第一子流的相应符号率的采样率操作。第一模拟滤波器提供相应子信道信号的预加重和对应于相应子信道信号的相应频带之外的信号的衰减。数据传输电路还包括用于组合各个子信道信号以产生数据传输信号的组合器。

68. 发明申请

US20110150051A1 Multi-Tone System with Oversampled Precoders 失效
标题翻译：带过采样预编码器的多音系统
公开(公告)号：US20110150051A1
公开(公告)日：2011-06-23
申请号：US12907937
申请日：2010-10-19
申请人： Vladimir M. Stojanovic , Amir Amirkhany , Jared L. Zerbe
发明人： Vladimir M. Stojanovic , Amir Amirkhany , Jared L. Zerbe
IPC分类号： H04B1/38
CPC分类号： H04L25/03343 , H04L27/2637
摘要： A multi-tone system includes a data transmission circuit with an interface for receiving a data stream for transmission, a data steam splitter that splits the data stream to produce multiple substreams and a plurality of parallel data preparation circuits. Each data preparation circuit prepares a respective substream for transmission and generates a respective sub-channel signal. At least a first data preparation circuit of the plurality of parallel data preparation circuits includes a first analog filter for filtering a first substream. The first analog filter operates at a sample rate greater than the respective symbol rate of the first substream. The first analog filter provides pre-emphasis of the respective sub-channel signal and attenuation of signals outside of a respective band of frequencies corresponding to the respective sub-channel signal. The data transmission circuit also includes a combiner for combining respective sub-channel signals to generate a data transmission signal.
摘要翻译：多音系统包括具有用于接收用于传输的数据流的接口的数据传输电路，分割数据流以产生多个子流的数据蒸汽分配器和多个并行数据准备电路。每个数据准备电路准备相应的子流进行传输，并产生相应的子信道信号。多个并行数据准备电路的至少第一数据准备电路包括用于对第一子流进行滤波的第一模拟滤波器。第一模拟滤波器以大于第一子流的相应符号率的采样率操作。第一模拟滤波器提供相应子信道信号的预加重和对应于相应子信道信号的相应频带之外的信号的衰减。数据传输电路还包括用于组合各个子信道信号以产生数据传输信号的组合器。

69. 发明申请

US20100271092A1 LOW-POWER SOURCE-SYNCHRONOUS SIGNALING 有权
标题翻译：低功率源同步信号
公开(公告)号：US20100271092A1
公开(公告)日：2010-10-28
申请号：US12738610
申请日：2008-07-03
申请人： Jared L. Zerbe , Frederick A. Ware
发明人： Jared L. Zerbe , Frederick A. Ware
IPC分类号： H03L7/00
CPC分类号： G11C11/4076 , G06F1/04 , G06F13/4243 , G11C7/04 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C29/022 , G11C29/023 , G11C29/028 , G11C2207/2254 , H04L7/0008 , Y02D10/14 , Y02D10/151
摘要： Within a system of integrated circuit devices, first and second signals are transmitted intermittently from a first integrated circuit device to a second integrated circuit device. The second integrated circuit device generates a timing signal based on transitions of the second signal and generates samples of the first signal in response to transitions of the timing signal. The second integrated circuit device further generates timing error information based on the samples of the first signal, the timing error information to enable adjustment of the relative phases of the timing signal and the first signal.
摘要翻译：在集成电路器件的系统中，第一和第二信号从第一集成电路器件间歇地传输到第二集成电路器件。第二集成电路装置基于第二信号的转换产生定时信号，并且响应于定时信号的转换而产生第一信号的采样。第二集成电路装置还基于第一信号的采样，定时误差信息产生定时误差信息，以使得能够调整定时信号和第一信号的相对相位。

70. 发明授权

US07715509B2 Partial response receiver 有权
公开(公告)号：US07715509B2
公开(公告)日：2010-05-11
申请号：US12403340
申请日：2009-03-12
申请人： Vladimir M. Stojanovic , Mark A. Horowitz , Jared L. Zerbe , Anthony Bessios , Andrew C. C. Ho , Jason C. Wei , Grace Tsang , Bruno W. Garlepp
发明人： Vladimir M. Stojanovic , Mark A. Horowitz , Jared L. Zerbe , Anthony Bessios , Andrew C. C. Ho , Jason C. Wei , Grace Tsang , Bruno W. Garlepp
IPC分类号： H04L7/00
CPC分类号： H04L25/03057 , H04L7/0276 , H04L25/063 , H04L25/497 , H04L2025/03369 , H04L2025/03503
摘要： A receive circuit for receiving a signal transmitted via an electric signal conductor. A first sampling circuit generates a first sample value that indicates whether the signal exceeds a first threshold level, and a second sampling circuit generates a second sample value that indicates whether the signal exceeds a second threshold level. A first select circuit receives the first and second sample values from the first and second sampling circuits and selects, according to a previously generated sample value, either the first sample value or the second sample value to be output as a selected sample value.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式