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61. 发明授权

US5623628A Computer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queue 失效
标题翻译：用于维持流水线，非阻塞缓存总线请求队列中的内存一致性的计算机系统和方法
公开(公告)号：US5623628A
公开(公告)日：1997-04-22
申请号：US205040
申请日：1994-03-02
申请人： James M. Brayton , Michael W. Rhodehamel , Nitin V. Sarangdhar , Glenn J. Hinton
发明人： James M. Brayton , Michael W. Rhodehamel , Nitin V. Sarangdhar , Glenn J. Hinton
IPC分类号： G06F9/38 , G06F12/08 , G06F13/18 , G06F12/00
CPC分类号： G06F12/0831 , G06F13/18 , G06F9/3017 , G06F9/3824 , G06F9/3828 , G06F9/3834
摘要： A computer system, and a method performed by it, having a mechanism for ensuring consistency of data among various level(s) of caching in a multi-level hierarchical memory system. The cache consistency mechanism includes an external bus request queue which and associated mechanism, which cooperate to monitor and control the issuance of data requests, such as read requests and write requests, onto an external bus. The computer system includes one or more CPUs each having this consistency mechanism.
摘要翻译：一种计算机系统及其执行的方法，具有用于确保在多级分层存储器系统中的各种级别的高速缓存之间的数据的一致性的机制。高速缓存一致性机制包括一个外部总线请求队列及其相关联的机制，它们协调监视和控制诸如读请求和写请求之类的数据请求的发布到外部总线上。计算机系统包括一个或多个具有这一一致性机制的CPU。

62. 发明授权

US5586278A Method and apparatus for state recovery following branch misprediction in an out-of-order microprocessor 失效
标题翻译：在无序微处理器中的分支错误预测之后状态恢复的方法和装置
公开(公告)号：US5586278A
公开(公告)日：1996-12-17
申请号：US639244
申请日：1996-04-22
申请人： David B. Papworth , Glenn J. Hinton
发明人： David B. Papworth , Glenn J. Hinton
IPC分类号： G06F9/38
CPC分类号： G06F9/3863
摘要： A method of state recovery following a branch misprediction or an undetected branch instruction. If, during execution of a branch instruction in an out-of-order unit, it is determined that the branch has been mispredicted, or if a taken branch has not been detected, then a JEClear signal is asserted to flush the instruction fetch unit and decoder section, and to change the instruction pointer to the actual target address. Within the out-of-order section, the instructions preceding the branch instruction are allowed to continue execution and proceed to in-order retirement. Simultaneously, instructions fetched at the actual target address are decoded, but not allowed to issue therefrom until the branch instruction has been retired from the out-of-order section, after which all instructions within the out-of-order section are flushed, and then decoded instructions are allowed to issue from the decoder. The state recovery method advantageously provides efficient utilization of processor time.
摘要翻译：分支错误预测或未检测到的分支指令之后的状态恢复方法。如果在执行无序单元中的分支指令时，确定分支已经被错误预测，或者如果未被检测到被采取的分支，则断言JEClear信号以刷新指令获取单元，并且解码器部分，并将指令指针更改为实际目标地址。在无序部分中，分支指令之前的指令被允许继续执行，并进行到订单退休。同时，在实际目标地址处获取的指令被解码，但是在分支指令已经从无序部分退出之前不允许发出指令，之后清除无序部分内的所有指令，以及则解码指令被允许从解码器发出。状态恢复方法有利地提供了处理器时间的有效利用。

63. 发明授权

US5574871A Method and apparatus for implementing a set-associative branch target buffer 失效
公开(公告)号：US5574871A
公开(公告)日：1996-11-12
申请号：US177155
申请日：1994-01-04
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani K. Gupta , Michael A. Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani K. Gupta , Michael A. Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/30054
摘要： A Branch Target Buffer Circuit in a computer processor that predicts branch instructions with a stream of computer instructions is disclosed. The Branch Target Buffer Circuit uses a Branch Target Buffer Cache that stores branch information about previously executed branch instructions. The branch information stored in the Branch Target Buffer Cache is addressed by the last byte of each branch instruction. When an Instruction Fetch Unit in the computer processor fetches a block of instructions it sends the Branch Target Buffer Circuit an instruction pointer. Based on the instruction pointer, the Branch Target Buffer Circuit looks in the Branch Target Buffer Cache to see if any of the instructions in the block being fetched is a branch instruction. When the Branch Target Buffer Circuit finds an upcoming branch instruction in the Branch Target Buffer Cache, the Branch Target Buffer Circuit informs an Instruction Fetch Unit about the upcoming branch instruction.

64. 发明授权

US08407489B2 Method and apparatus for quick resumption 有权
公开(公告)号：US08407489B2
公开(公告)日：2013-03-26
申请号：US12384673
申请日：2009-04-07
申请人： Michael A. Rothman , Glenn J. Hinton , Mark S. Doran , Vincent J. Zimmer , Michael D. Kinney
发明人： Michael A. Rothman , Glenn J. Hinton , Mark S. Doran , Vincent J. Zimmer , Michael D. Kinney
IPC分类号： G06F9/24 , G06F15/177
CPC分类号： G06F1/3234 , G06F9/4418
摘要： When transitioning from sleep mode to active mode, a processing system loads first stage resume content and second stage resume content into a volatile memory of the processing system. The first stage resume content may contain contextual data for a first program that was in use before the processing system transitioned to sleep mode. The second stage resume content may contain contextual data for another program that was in use before the processing system transitioned to sleep mode. The processing system may provide a user interface for the first program before all of the second stage resume content has been loaded into the volatile memory. Other embodiments are described and claimed.

65. 发明申请

US20120166891A1 TWO-LEVEL SYSTEM MAIN MEMORY 有权
标题翻译：两级系统主要内存
公开(公告)号：US20120166891A1
公开(公告)日：2012-06-28
申请号：US12976545
申请日：2010-12-22
申请人： Eric J. Dahlen , Glenn J. Hinton , Raj K. Ramanujan
发明人： Eric J. Dahlen , Glenn J. Hinton , Raj K. Ramanujan
IPC分类号： G06F11/16 , G06F12/00
CPC分类号： G06F3/0611 , G06F3/0647 , G06F3/0685 , G06F11/0766 , G06F12/0246 , G06F12/0638 , G06F12/0868 , G06F12/0893 , G06F2212/1024 , G06F2212/313 , G06F2212/7203 , G06F2212/7208 , G06F2212/7209 , G06F2212/7211 , G11C14/009
摘要： Embodiments of the invention describe a system main memory comprising two levels of memory that include cached subsets of system disk level storage. This main memory includes “near memory” comprising memory made of volatile memory, and “far memory” comprising volatile or nonvolatile memory storage that is larger and slower than the near memory.The far memory is presented as “main memory” to the host OS while the near memory is a cache for the far memory that is transparent to the OS, thus appearing to the OS the same as prior art main memory solutions. The management of the two-level memory may be done by a combination of logic and modules executed via the host CPU. Near memory may be coupled to the host system CPU via high bandwidth, low latency means for efficient processing. Far memory may be coupled to the CPU via low bandwidth, high latency means.
摘要翻译：本发明的实施例描述了包括两级存储器的系统主存储器，其包括系统盘级存储器的缓存子集。该主存储器包括包括由易失性存储器构成的存储器的“近存储器”，以及包括比近存储器更大和更慢的易失性或非易失性存储器存储器的“远存储器”。远端存储器被呈现为主机OS的“主存储器”，而近端存储器是对于对OS是透明的远存储器的高速缓存，因此与OS显示与现有技术主存储器解决方案相同的高速缓存。两级存储器的管理可以通过经由主机CPU执行的逻辑和模块的组合来完成。靠近存储器可以通过高带宽，低延迟的方式耦合到主机系统CPU，用于有效处理。远存储器可以经由低带宽，高延迟装置耦合到CPU。

66. 发明授权

US08171219B2 Method and system to perform caching based on file-level heuristics 有权
标题翻译：基于文件级启发式方法和系统执行缓存
公开(公告)号：US08171219B2
公开(公告)日：2012-05-01
申请号：US12415595
申请日：2009-03-31
申请人： Sanjeev N. Trika , Amber D. Huffman , James A. Boyd , Frank T. Hady , Glenn J. Hinton , Dale J. Juenemann , Oscar P. Pinto , Scott R. Tetrick , Thomas J. Barnes , Scott E. Burridge
发明人： Sanjeev N. Trika , Amber D. Huffman , James A. Boyd , Frank T. Hady , Glenn J. Hinton , Dale J. Juenemann , Oscar P. Pinto , Scott R. Tetrick , Thomas J. Barnes , Scott E. Burridge
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0866 , G06F12/0888 , G06F12/121 , G06F2212/222 , G06F2212/6028
摘要： A method and system to perform caching based at least on one or more file-level heuristics. The caching of a storage medium in a caching device is performed by a cache policy engine. The cache policy engine receives file-level information of input/output access of data of the storage medium and caches or evicts the data of the storage medium in the caching device based on the received file-level information. By utilizing information about the files and file operations associated with the disk sectors or logical block addresses of the storage medium, the cache policy engine can make a better decision on the data selection of the storage medium to be cached in or evicted from the caching device in one embodiment of the invention. Higher cache hit rates can be achieved and the performance of the system utilizing the cache policy engine is improved.
摘要翻译：至少基于一个或多个文件级启发式方法和系统执行缓存。缓存设备中的存储介质的缓存由高速缓存策略引擎执行。高速缓存策略引擎接收存储介质的数据的输入/输出访问的文件级信息，并基于接收到的文件级信息来高速缓存或者将高速缓存设备中的存储介质的数据移出。通过利用关于与存储介质的磁盘扇区或逻辑块地址相关联的文件和文件操作的信息，高速缓存策略引擎可以更好地决定要缓存到缓存设备或从高速缓存设备移出的存储介质的数据选择在本发明的一个实施例中。可以实现更高的缓存命中率，并提高利用缓存策略引擎的系统的性能。

67. 发明申请

US20090271641A1 Method and apparatus for quick resumption 有权
公开(公告)号：US20090271641A1
公开(公告)日：2009-10-29
申请号：US12384673
申请日：2009-04-07
申请人： Michael A. Rothman , Glenn J. Hinton , Mark S. Doran , Vincent J. Zimmer , Michael D. Kinney
发明人： Michael A. Rothman , Glenn J. Hinton , Mark S. Doran , Vincent J. Zimmer , Michael D. Kinney
IPC分类号： G06F1/00
CPC分类号： G06F1/3234 , G06F9/4418
摘要： When transitioning from sleep mode to active mode, a processing system loads first stage resume content and second stage resume content into a volatile memory of the processing system. The first stage resume content may contain contextual data for a first program that was in use before the processing system transitioned to sleep mode. The second stage resume content may contain contextual data for another program that was in use before the processing system transitioned to sleep mode. The processing system may provide a user interface for the first program before all of the second stage resume content has been loaded into the volatile memory. Other embodiments are described and claimed.

68. 发明授权

US06487675B2 Processor having execution core sections operating at different clock rates 有权
标题翻译：具有执行核心部分以不同时钟速率工作的处理器
公开(公告)号：US06487675B2
公开(公告)日：2002-11-26
申请号：US09775383
申请日：2001-02-02
申请人： David J. Sager , Thomas D. Fletcher , Glenn J. Hinton , Michael D. Upton
发明人： David J. Sager , Thomas D. Fletcher , Glenn J. Hinton , Michael D. Upton
IPC分类号： G06F104
CPC分类号： G06F1/02 , G06F1/06 , G06F1/08 , G06F9/30145 , G06F9/383 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3869 , G06F15/7832
摘要： A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.
摘要翻译：一种处理器，包括以第一时钟频率执行执行操作的第一执行核心部分和第二执行核心部分，其被计时以在与第一时钟频率不同的第二时钟频率执行执行操作。第二个执行核心部分运行速度更快，包括数据高速缓存和关键的ALU功能，而第一个执行核心部分包括延迟容忍功能，如指令提取和解码单元以及非关键ALU功能。处理器还可以包括可能仍然比第一执行核心部分慢的I / O环。可选地，第一执行核心部分可以包括其时钟速率在第一执行核心部分和第二执行核心部分之间的第三执行核心部分。可以在各部分之间使用时钟乘法器/分频器，以从单个源（例如I / O时钟）导出其时钟。

69. 发明授权

US5842036A Circuit and method for scheduling instructions by predicting future availability of resources required for execution 失效
公开(公告)号：US5842036A
公开(公告)日：1998-11-24
申请号：US954444
申请日：1997-10-20
申请人： Glenn J. Hinton , Robert W. Martell , Michael A. Fetterman , David B. Papworth , James L. Schwartz
发明人： Glenn J. Hinton , Robert W. Martell , Michael A. Fetterman , David B. Papworth , James L. Schwartz
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/384 , G06F9/30145 , G06F9/30167 , G06F9/3824 , G06F9/3836 , G06F9/3857 , G06F9/3875 , G06F9/3885 , G06F9/3889 , G06F9/3891
摘要： An out-of-order execution processor comprising an execution unit, a storage unit and a scheduler is disclosed. The storage unit stores instructions awaiting availability of resources required for execution. The scheduler periodically determines whether resources required for executing each instruction are available, and if so, dispatches that instruction to the execution unit. The execution unit indicates future availability of hardware resources such as functional units and write back ports a number of clock cycles before actual availability of the hardware resources. The scheduler determines availability of resources required for execution of an instruction based on the indication of future availability of the hardware resources, and dispatched the instruction for execution. The out-of-order execution processor also includes means to determine future completion of execution of source instructions a number of clock cycles before actual completion of execution. The scheduler dispatches for execution a data-dependent instruction that requires an execution result of one of such source instructions for an operand. Once the execution result of the source instruction is available, a bypass multiplexor bypasses the execution result into the dispatched data-dependent instruction. The bypass multiplexor sends the data dependent instruction with fully assembled operands to the execution unit for execution.

70. 发明授权

US5812839A Dual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unit 失效
标题翻译：双预测分支系统具有分支恢复过程的两个步骤，仅在错误预测分支是无序单元中最旧的指令时激活
公开(公告)号：US5812839A
公开(公告)日：1998-09-22
申请号：US851141
申请日：1997-05-05
申请人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
发明人： Bradley D. Hoyt , Glenn J. Hinton , David B. Papworth , Ashwani Kumar Gupta , Michael Alan Fetterman , Subramanian Natarajan , Sunil Shenoy , Reynold V. D'Sa
IPC分类号： G06F9/38
CPC分类号： G06F9/3806 , G06F9/322 , G06F9/3844 , G06F9/3863 , G06F9/3885
摘要： A four stage branch instruction resolution system for a pipelined processor is disclosed. A first stage of the branch instruction resolution system predicts the existence and outcome of branch instructions within an instruction stream such that an instruction fetch unit can continually fetch instructions. A second stage decodes all the instructions fetched. If the decode stage determines that a branch instruction predicted by the first stage is not a branch instruction, the decode stage flushes the pipeline and restarts the processor at a corrected address. The decode stage verifies all branch predictions made by the branch prediction stage. Finally, the decode stage makes branch predictions for branches not predicted by the branch prediction stage. A third stage executes all the branch instructions to determine a final branch outcome and a final branch target address. The branch execution stage compares the final branch outcome and final branch target address with the predicted branch outcome and predicted branch target address to determine if the processor must flush the front-end of the microprocessor pipeline and restart at a corrected address. A final branch resolution stage retires all branch instructions. The retirement stage ensures that any instructions fetched after a mispredicted branch are not committed into permanent state.
摘要翻译：公开了一种用于流水线处理器的四级分支指令解析系统。分支指令解析系统的第一阶段预测指令流内分支指令的存在和结果，使得指令获取单元可以连续地获取指令。第二阶段解码所有提取的指令。如果解码级确定由第一级预测的分支指令不是分支指令，则解码级别刷新流水线并以校正的地址重新启动处理器。解码阶段验证分支预测阶段所做的所有分支预测。最后，解码阶段对分支预测阶段未预测的分支进行分支预测。第三阶段执行所有分支指令以确定最终分支结果和最终分支目标地址。分支执行阶段将最终分支结果和最终分支目标地址与预测的分支结果和预测分支目标地址进行比较，以确定处理器是否必须冲洗微处理器流水线的前端并以修正的地址重新启动。最终的分支解决阶段退出所有分支指令。退休阶段确保在错误预测的分支之后提取的任何指令不会被永久保留。

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