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61. 发明申请

US20130061199A1 Navigating Analytical Tools Using Layout Software 有权
标题翻译：使用布局软件导航分析工具
公开(公告)号：US20130061199A1
公开(公告)日：2013-03-07
申请号：US13611776
申请日：2012-09-12
申请人： Franco Stellari , Peilin Song
发明人： Franco Stellari , Peilin Song
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5022 , G06F17/5036
摘要： A background process installs a system hook for message interception of integrated circuit chip layout display software. A call message is intercepted through the system hook, and current layout coordinates are read from the integrated circuit chip layout display software. A representation of the current layout coordinates is entered into tool control software configured to control a physical tool for analyzing integrated circuits, and the physical tool is controlled with the tool control software. In an “inverse” approach, a background process is used to install at least one system hook for message interception of tool control software configured to control a physical tool for analyzing integrated circuits, and a call message is intercepted through the system hook. Current coordinates are read from the tool control software. A representation of the current coordinates is entered into integrated circuit chip layout display software, and at least a portion of an integrated circuit layout is displayed.
摘要翻译：背景过程安装了用于消息拦截集成电路芯片布局显示软件的系统挂钩。通过系统挂钩截取通话消息，从集成电路芯片布局显示软件中读取当前布局坐标。将当前布局坐标的表示输入到被配置为控制用于分析集成电路的物理工具的工具控制软件中，并且物理工具由工具控制软件控制。在逆向方法中，使用后台处理来安装至少一个用于消息拦截的系统钩子，用于控制用于分析集成电路的物理工具的工具控制软件，并且通过系统钩子拦截呼叫消息。从刀具控制软件读取当前坐标。将当前坐标的表示输入到集成电路芯片布局显示软件中，并且显示集成电路布局的至少一部分。

62. 发明授权

US08312413B2 Navigating analytical tools using layout software 有权
标题翻译：使用布局软件浏览分析工具
公开(公告)号：US08312413B2
公开(公告)日：2012-11-13
申请号：US12692198
申请日：2010-01-22
申请人： Franco Stellari , Peilin Song
发明人： Franco Stellari , Peilin Song
IPC分类号： G06F17/50 , G06F9/44
CPC分类号： G06F17/5081 , G06F17/5022 , G06F17/5036
摘要： A background process is used to install at least one system hook for message interception of integrated circuit chip layout display software. A call message is intercepted through the system hook, and, responsive to the call message, current layout coordinates are read from the integrated circuit chip layout display software. A representation of the current layout coordinates is entered into tool control software configured to control a physical tool for analyzing integrated circuits, and the physical tool is controlled with the tool control software, based on the representation of the current layout coordinates. In an “inverse” approach, a background process is used to install at least one system hook for message interception of tool control software configured to control a physical tool for analyzing integrated circuits, and a call message is intercepted through the system hook. Responsive to the call message, current coordinates are read from the tool control software. A representation of the current coordinates is entered into integrated circuit chip layout display software, and at least a portion of an integrated circuit layout, corresponding to the representation of the current coordinates from the tool control software, is displayed.
摘要翻译：后台进程用于安装至少一个系统挂钩，用于消息拦截集成电路芯片布局显示软件。通过系统挂钩拦截呼叫消息，并响应于呼叫消息，从集成电路芯片布局显示软件读取当前布局坐标。将当前布局坐标的表示输入到被配置为控制用于分析集成电路的物理工具的工具控制软件中，并且基于当前布局坐标的表示，通过工具控制软件来控制物理工具。在逆向方法中，使用后台处理来安装至少一个用于消息拦截的系统钩子，用于控制用于分析集成电路的物理工具的工具控制软件，并且通过系统钩子拦截呼叫消息。响应于通话消息，从工具控制软件读取当前坐标。将当前坐标的表示输入到集成电路芯片布局显示软件中，并且显示对应于来自刀具控制软件的当前坐标的表示的集成电路布局的至少一部分。

63. 发明授权

US08131056B2 Constructing variability maps by correlating off-state leakage emission images to layout information 失效
标题翻译：通过将非状态泄漏图像与布局信息相关联来构建变异性图
公开(公告)号：US08131056B2
公开(公告)日：2012-03-06
申请号：US12241926
申请日：2008-09-30
申请人： Stanislav Polonsky , Peilin Song , Franco Stellari , Alan J. Weger
发明人： Stanislav Polonsky , Peilin Song , Franco Stellari , Alan J. Weger
IPC分类号： G06K9/00
CPC分类号： G06T7/001 , G06T2207/30148
摘要： Improved techniques are disclosed for monitoring or sensing process variations in integrated circuit designs. Such techniques provide such improvements by constructing variability maps correlating leakage emission images to layout information. By way of example, a method for monitoring one or more manufacturing process variations associated with a device under test (e.g., integrated circuit) comprises the following steps. An emission image representing an energy emission associated with a leakage current of the device under test is obtained. The emission image is correlated with a layout of the device under test to form a cross emission image. Common structures on the cross emission image are selected and identified as regions of interest. One or more variability measures (e.g., figures of merit) are calculated based on the energy emissions associated with the regions of interest. A variability map is created based on the calculated variability measures, wherein the variability map is useable to monitor the one or more manufacturing process variations associated with the device under test.
摘要翻译：公开了用于监测或感测集成电路设计中的工艺变化的改进的技术。这样的技术通过构建将泄漏发射图像与布局信息相关联的可变性图来提供这样的改进。作为示例，用于监测与被测器件（例如，集成电路）相关联的一个或多个制造工艺变化的方法包括以下步骤。获得表示与被测设备的泄漏电流相关联的能量发射的发射图像。发射图像与待测器件的布局相关，以形成交叉发射图像。选择交叉发射图像上的共同结构并将其识别为感兴趣的区域。基于与感兴趣区域相关联的能量排放来计算一个或多个可变性度量（例如，品质因素）。基于所计算的变异性度量创建变异性图，其中可变性图可用于监测与被测设备相关联的一个或多个制造过程变化。

64. 发明申请

US20110296266A1 Self-Adjusting Critical Path Timing of Multi-Core VLSI Chip 有权
标题翻译：多核VLSI芯片的自调节关键路径时序
公开(公告)号：US20110296266A1
公开(公告)日：2011-12-01
申请号：US12788987
申请日：2010-05-27
申请人： Peilin Song , Franco Stellari
发明人： Peilin Song , Franco Stellari
IPC分类号： G06F1/12 , G06F11/25 , G01R31/3177
CPC分类号： G01R31/31726 , G01R31/3187 , G06F1/10 , G06F11/2242
摘要： A method for adjusting timing of multiple cores within an integrated circuit includes selecting a reference core and a target core from among a plurality of cores of an integrated circuit. Self-test circuitry of the integrated circuit is used to generate a response signature for each of the reference core and the target core. The response signature of the reference core is compared with the response signature of the target core. A local clock buffer of the target core is adjusted until the response signature of the target core matches the response signature of the reference core.
摘要翻译：一种用于调整集成电路内的多个核心的定时的方法包括从集成电路的多个核心中选择参考核心和目标核心。集成电路的自检电路用于为每个参考核心和目标核心产生响应特征。将参考核心的响应签名与目标核心的响应签名进行比较。调整目标核心的本地时钟缓冲器，直到目标核心的响应签名与参考核心的响应签名相匹配。

65. 发明申请

US20110280468A1 METHOD AND SYSTEM FOR QUICKLY IDENTIFYING CIRCUIT COMPONENTS IN AN EMISSION IMAGE 有权
标题翻译：在排放图像中快速识别电路组件的方法和系统
公开(公告)号：US20110280468A1
公开(公告)日：2011-11-17
申请号：US12778544
申请日：2010-05-12
申请人： Peilin Song , Franco Stellari
发明人： Peilin Song , Franco Stellari
IPC分类号： G06T7/00 , G01R31/303
CPC分类号： G01R31/311 , G01R31/2853 , G06T7/001 , G06T7/11 , G06T2207/10056 , G06T2207/30148
摘要： A system and method for localization and resolvability of an integrated circuit includes selecting one or more electrical stimuli to be applied to a device under test such that the electrical stimuli are chosen to provide a baseline image and a distinguishing image effect as a result of the chosen stimuli when applied to the device under test. The one or more electrical stimuli are applied to the device under test. Emissions from the device under test are measured to provide a measurement data set from the one or more electrical stimuli using one or more measurement tools for collecting the baseline image and the distinguishing image effect. The measurement data set is analyzed to localize and evaluate circuit structures by comparing the baseline image and the distinguishing image effect.
摘要翻译：用于集成电路的定位和可解析性的系统和方法包括选择要施加到被测器件的一个或多个电刺激，使得选择电刺激以提供基线图像和作为所选择的结果的结果的区别图像效果当被施加到被测设备时刺激。一个或多个电刺激被施加到被测设备。测量来自被测器件的发射，以使用一个或多个测量工具从一个或多个电刺激提供测量数据集，用于收集基线图像和区分图像效果。分析测量数据集，通过比较基线图像和区分图像效果来定位和评估电路结构。

66. 发明授权

US07927898B2 Apparatus and methods for packaging electronic devices for optical testing 失效
标题翻译：用于包装电子设备进行光学测试的装置和方法
公开(公告)号：US07927898B2
公开(公告)日：2011-04-19
申请号：US12534556
申请日：2009-08-03
申请人： Alberto Tosi , Franco Stellari , Peilin Song
发明人： Alberto Tosi , Franco Stellari , Peilin Song
IPC分类号： H01L21/00
CPC分类号： G01R31/311 , G01R1/0408 , H01L25/16 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/00011 , H01L2924/00014 , H01L2924/3011 , H01L2224/0401
摘要： Apparatus and methods are provided for packaging IC (integrated circuit) chips to enable both optical access to the back side of an IC chip and electrical access to the front side of the IC chip.
摘要翻译：提供了用于封装IC（集成电路）芯片的装置和方法，以使得能够对IC芯片的背侧进行光学接入和对IC芯片的前侧的电接入。

67. 发明申请

US20110026806A1 Detecting Chip Alterations with Light Emission 有权
标题翻译：用光发射检测芯片变化
公开(公告)号：US20110026806A1
公开(公告)日：2011-02-03
申请号：US12512168
申请日：2009-07-30
申请人： Kerry Bernstein , James Culp , David F. Heidel , Dirk Pfeiffer , Anthony D. Polson , Peilin Song , Franco Stellari , Robert L. Wisnieff
发明人： Kerry Bernstein , James Culp , David F. Heidel , Dirk Pfeiffer , Anthony D. Polson , Peilin Song , Franco Stellari , Robert L. Wisnieff
IPC分类号： G03F9/00 , G06F19/00
CPC分类号： G01R31/311
摘要： An emission map of a circuit to be tested for alterations is obtained by measuring the physical circuit to be tested. An emission map of a reference circuit is obtained by measuring a physical reference circuit or by simulating the emissions expected from the reference circuit. The emission map of the circuit to be tested is compared with the emission map of the reference circuit, to determine presence of alterations in the circuit to be tested, as compared to the reference circuit.
摘要翻译：通过测量要测试的物理电路来获得待测试电路的发射图。通过测量物理参考电路或通过模拟从参考电路预期的发射来获得参考电路的发射图。与参考电路相比，要测试的电路的发射图与参考电路的发射图进行比较，以确定待测电路中的变化的存在。

68. 发明申请

US20100329586A1 CREATING EMISSION IMAGES OF INTEGRATED CIRCUITS 失效
标题翻译：创建集成电路的排放图像
公开(公告)号：US20100329586A1
公开(公告)日：2010-12-30
申请号：US12493686
申请日：2009-06-29
申请人： Franco Stellari , Peilin Song
发明人： Franco Stellari , Peilin Song
IPC分类号： G06K9/36
CPC分类号： H04N5/33 , G01R31/303 , G06T7/32 , G06T2200/32 , G06T2207/10056 , G06T2207/30148 , H04N5/2259 , H04N5/2621 , H04N5/2625 , H04N5/2628 , H04N5/332
摘要： A method, system and computer program product are disclosed for creating an image from a device. In one embodiment, the method comprises acquiring first and second images from the device, said first and second images having overlapping portions, and estimating said overlapping portions to obtain an approximate shift amount to align approximately said first and second images. This method further comprises analyzing the overlapping portions, using a defined cross-correlation algorithm, to calculate a precise shift amount to align the first and second images; and using said precise shift amount to join the first and second images together. In one embodiment, an optical system is used to acquire the images, a stage is used to move either the device or the optical system to acquire the first and second images, and the estimating includes using movement of the stage to estimate the overlapping areas.
摘要翻译：公开了用于从设备创建图像的方法，系统和计算机程序产品。在一个实施例中，该方法包括从设备获取第一和第二图像，所述第一和第二图像具有重叠部分，并且估计所述重叠部分以获得近似偏移量以对准所述第一和第二图像。该方法还包括使用定义的互相关算法来分析重叠部分以计算精确偏移量以对齐第一和第二图像; 并且使用所述精确位移量将第一和第二图像连接在一起。在一个实施例中，使用光学系统来获取图像，阶段用于移动设备或光学系统以获取第一和第二图像，并且估计包括使用平台的运动来估计重叠区域。

69. 发明授权

US07826045B2 Angular spectrum tailoring in solid immersion microscopy for circuit analysis 失效
标题翻译：用于电路分析的固体浸液显微镜中的角度光谱裁剪
公开(公告)号：US07826045B2
公开(公告)日：2010-11-02
申请号：US12020157
申请日：2008-01-25
申请人： Stephen Bradley Ippolito , Darrell L. Miles , Peilin Song , John D. Sylvestri
发明人： Stephen Bradley Ippolito , Darrell L. Miles , Peilin Song , John D. Sylvestri
IPC分类号： G01N21/00
CPC分类号： G01R31/311
摘要： A method and structure for locating a fault in a semiconductor chip. The chip includes a substrate on a dielectric interconnect. A first electrical response image of the chip, which includes a spot representing the fault, is overlayed on a first reflection image for monochromatic light in an optical path from an optical microscope through a SIL/NAIL and into the chip. The index of refraction of the substrate exceeds that of the dielectric interconnect and is equal to that of the SIL/NAIL. A second electrical response image of the chip is overlayed on a second reflection image for the monochromatic light in an optical path in which an optical stop prevents all subcritical angular components of the monochromatic light from being incident on the SIL/NAIL. If the second electrical response image includes or does not include the spot, then the fault is in the substrate or the dielectric interconnect, respectively.
摘要翻译：一种用于定位半导体芯片中的故障的方法和结构。芯片包括电介质互连上的衬底。包括代表故障的点的芯片的第一电响应图像重叠在从光学显微镜通过SIL / NAIL并进入芯片的光路中的单色光的第一反射图像上。衬底的折射率超过电介质互连的折射率，等于SIL / NAIL的折射率。芯片的第二电响应图像覆盖在光路中的单色光的第二反射图像上，其中光学停止器防止单色光的所有亚临界角分量入射到SIL / NAIL上。如果第二电响应图像包括或不包括点，则故障分别在基板或电介质互连中。

70. 发明授权

US07788058B2 Method and apparatus for diagnosing broken scan chain based on leakage light emission 失效
标题翻译：基于泄漏光发射诊断断层扫描链的方法和装置
公开(公告)号：US07788058B2
公开(公告)日：2010-08-31
申请号：US12115768
申请日：2008-05-06
申请人： Peilin Song , Tian Xia , Alan J. Weger , Franco Stellari , Stanislav V. Polonsky
发明人： Peilin Song , Tian Xia , Alan J. Weger , Franco Stellari , Stanislav V. Polonsky
IPC分类号： G06F19/00
CPC分类号： G01R31/318538 , G01R31/311
摘要： A mechanism for diagnosing broken scan chains based on leakage light emission is provided. An image capture mechanism detects light emission from leakage current in complementary metal oxide semiconductor (CMOS) devices. The diagnosis mechanism identifies devices with unexpected light emission. An unexpected amount of light emission may indicate that a transistor is turned off when it should be turned on or vice versa. All possible inputs may be tested to determine whether a problem exists with transistors in latches or with transistors in clock buffers. Broken points in the scan chain may then be determined based on the locations of unexpected light emission.
摘要翻译：提供了一种基于泄漏光发射来诊断断层扫描链的机构。图像捕获机构检测互补金属氧化物半导体（CMOS）器件中的泄漏电流的发光。诊断机制识别具有意外发光的设备。意外的发光量可能表明当它应该被打开时晶体管被关闭，反之亦然。可以测试所有可能的输入以确定锁存器中的晶体管或时钟缓冲器中的晶体管是否存在问题。然后可以基于意外光发射的位置来确定扫描链中的断点。

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