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61. 发明授权

US5881272A Synchronized MIMD multi-processing system and method inhibiting instruction fetch at other processors on write to program counter of one processor 失效
标题翻译：同步MIMD多处理系统和方法禁止在其他处理器上的指令读取到一个处理器的程序计数器
公开(公告)号：US5881272A
公开(公告)日：1999-03-09
申请号：US922152
申请日：1997-09-02
申请人： Keith Balmer
发明人： Keith Balmer
IPC分类号： G06F9/30 , G06F9/312 , G06F9/315 , G06F9/318 , G06F9/355 , G06F9/38 , G06F15/16
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/30036 , G06F9/30087 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/30192 , G06F9/321 , G06F9/325 , G06F9/355 , G06F9/3832 , G06F9/3885
摘要： A multi-processor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories. The individual processors can, on a cycle by cycle basis, be grouped in any configuration to run in synchronism (but from different instruction streams) with the other processors in that group. More than one such synchronized group can be formed concurrently. A crossbar switch serves to establish the processor memory links and the entire image processor, including the individual processors, the crossbar switch and the memories are contained on a single silicon chip.
摘要翻译：在一个实施例中，多处理器系统被布置为图像和图形处理器。处理器的结构与几个单独的处理器都具有到几个存储器的通信链接。各个处理器可以逐周期地分组在任何配置中，与该组中的其他处理器同步（但是来自不同的指令流）运行。可以同时形成多个这样的同步组。交叉开关用于建立处理器存储器链路，并且整个图像处理器，包括各个处理器，交叉开关和存储器都包含在单个硅芯片上。

62. 发明授权

US5606677A Packed word pair multiply operation forming output including most significant bits of product and other bits of one input 失效
标题翻译：封装字对乘法运算形成输出，包括产品的最高有效位和一个输入的其他位
公开(公告)号：US5606677A
公开(公告)日：1997-02-25
申请号：US472828
申请日：1995-06-07
申请人： Keith Balmer , Christopher J. Read
发明人： Keith Balmer , Christopher J. Read
IPC分类号： G06F7/52 , G06F9/302 , G06F7/44
CPC分类号： G06F7/5324 , G06F7/5336 , G06F9/30014 , G06F9/30036 , G06F2207/382 , G06F2207/3828 , G06F7/49963
摘要： This invention is a method and apparatus for multiplication which enables two factors to be packed into the same size data word as the product. The invention partitions two N bit buses (210, 202) into a first set of M bits and a second set of L bits. In the preferred embodiment the first set of M bits is N/2 most significant bits and the second set of L bits in N/2 least significant bits. Thus N=M+L and M=L. A multiplier (220) multiplies the second sets of L bits of each of the N bit numbers. This results in a product having up to 2L bits. The invention forms an output word having a first set of L bits being the most significant L bits of the product and a second set of M bits being the first set of M bits of the first N bit data word. In the preferred embodiment, a multiplexer (221) selects between the full product of 2L bits and the packed word output. The product may be scaled prior to partitioning via a left shifter (224) which shifts the product a selected number of bit positions. The invention preferably also includes rounding the most significant half of the product using an adder (226). This invention enables multiplication of respective first and second sets of bits of a first number by respective second and third numbers, resulting in a single packed word resultant. This process includes two passes through the multiplier (220). The final resultant has a first set of bits corresponding to the most significant half of the second product and a second set of bits corresponding to the first set product from the intermediate resultant. In the preferred embodiment of this invention, the multiplier (220) is embodied in at least one digital image/graphics processor (71, 72, 73, 74) as a part of a multiprocessor (100) formed in a single integrated circuit used in image processing.
摘要翻译：本发明是一种用于乘法的方法和装置，其使两个因素能够被打包成与产品相同大小的数据字。本发明将两个N位总线（210,202）分成第一组M位和第二组L位。在优选实施例中，第一组M位是N / 2个最高有效位，并且N / 2个最低有效位中的第二组L位。因此N = M + L和M = L。乘法器（220）将N位数中的每一个的第二组L位相乘。这导致产品具有高达2L的位。本发明形成具有产品的最高有效L位的第一组L位和第一N位数据字M位的第一组M位的输出字。在优选实施例中，多路复用器（221）在2L位的全乘积和打包字输出之间进行选择。产品可以在经由左移位器（224）进行分割之前进行缩放，左移位器将产品移动到选定数量的位位置。本发明还优选地还包括使用加法器（226）对产品的最重要的一半舍入。本发明使得能够通过相应的第二和第三数字来乘以第一数字的相应的第一和第二组位，导致单个打包字的结果。该过程包括通过乘法器（220）的两次通过。最终结果具有对应于第二乘积的最高有效半部分的第一组位，以及对应于来自中间结果的第一集合乘积的第二组位。在本发明的优选实施例中，乘法器（220）被实现在至少一个数字图像/图形处理器（71,72,73,74）中，作为形成在单个集成电路中使用的多处理器（100）的一部分，图像处理。

63. 发明授权

US07047284B1 Transfer request bus node for transfer controller with hub and ports 有权
标题翻译：用于具有集线器和端口的传输控制器的传输请求总线节点
公开(公告)号：US07047284B1
公开(公告)日：2006-05-16
申请号：US09713440
申请日：2000-11-15
申请人： Sanjive Agarwala , David A. Comisky , Charles L. Fuoco , Iain Robertson , David Hoyle , John Keay , Keith Balmer , Amarjit S. Bhandal , Christopher L. Mobley
发明人： Sanjive Agarwala , David A. Comisky , Charles L. Fuoco , Iain Robertson , David Hoyle , John Keay , Keith Balmer , Amarjit S. Bhandal , Christopher L. Mobley
IPC分类号： G06F15/177
CPC分类号： G06F13/37
摘要： A transfer request bus and transfer request bus node is described which is suitable for use in a data transfer controller processing multiple concurrent transfer requests despite the attendant collisions which result when conflicting transfer requests occur. Transfer requests are passed from an upstream transfer request node to downstream transfer request node and then to a transfer request controller with queue. At each node a local transfer request can also be inserted to be passed on to the transfer controller queue. Collisions at each transfer request node are resolved using a token passing scheme wherein a transfer request node possessing the token allows a local request to be inserted in preference to the upstream request.
摘要翻译：描述了转移请求总线和传送请求总线节点，其适用于处理多个并发转移请求的数据传输控制器，尽管在发生冲突的转移请求时产生了伴随的冲突。传输请求从上游传输请求节点传递到下游传输请求节点，然后传送到具有队列的传输请求控制器。在每个节点处，也可以插入本地传输请求以传递到传输控制器队列。使用令牌传递方案来解决每个传送请求节点处的冲突，其中拥有令牌的传送请求节点允许优先于上游请求插入本地请求。

64. 发明授权

US06757775B2 Batch method for accessing IDE device task registers 有权
标题翻译：访问IDE设备任务寄存器的批量方法
公开(公告)号：US06757775B2
公开(公告)日：2004-06-29
申请号：US09964924
申请日：2001-09-26
申请人： Keith Balmer
发明人： Keith Balmer
IPC分类号： G06F1312
CPC分类号： G06F13/126
摘要： The method maps at least one intermediate data register of a first data width into the address space of the computer bus. The computer bus writes data to an intermediate data registers with write strobes corresponding to data subsets of a second smaller data width equal to the data width of the device registers. The IDE controller then transfers data from the intermediate data register to the device registers in subsets of the device register data width in a fixed order of device registers. Similarly, for reads of the device register, the computer bus writes data to a read selection data field of an intermediate data register. Each bit of the read selection data field corresponding to one device register. The IDE controller transfers data from the device registers corresponding to bits of the read selection data field having a predetermined first digital state to an intermediate data register in a fixed read order of device registers.
摘要翻译：该方法将至少一个第一数据宽度的中间数据寄存器映射到计算机总线的地址空间中。计算机总线将数据写入中间数据寄存器，其中写入选通对应于等于设备寄存器的数据宽度的第二较小数据宽度的数据子集。然后，IDE控制器以设备寄存器的固定顺序将数据从中间数据寄存器传送到设备寄存器数据宽度子集中。类似地，对于设备寄存器的读取，计算机总线将数据写入中间数据寄存器的读取选择数据字段。读取选择数据字段的每一位对应于一个设备寄存器。 IDE控制器将来自具有预定的第一数字状态的读取选择数据字段的位的设备寄存器的数据以设备寄存器的固定读取顺序传送到中间数据寄存器。

65. 发明授权

US5758195A Register to memory data transfers with field extraction and zero/sign extension based upon size and mode data corresponding to employed address register 失效
标题翻译：根据对应于所采用的地址寄存器的大小和模式数据，对场提取和零/符号扩展进行存储器数据传输
公开(公告)号：US5758195A
公开(公告)日：1998-05-26
申请号：US487201
申请日：1995-06-07
申请人： Keith Balmer
发明人： Keith Balmer
IPC分类号： G06F9/30 , G06F9/312 , G06F9/315 , G06F9/318 , G06F9/355 , G06F9/38 , G06F12/04
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/30036 , G06F9/30087 , G06F9/30112 , G06F9/3013 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/30192 , G06F9/321 , G06F9/325 , G06F9/355 , G06F9/3832 , G06F9/3885
摘要： A data processing system including a data-memory storing data words having a first data size, and a data processor having an address generator generating addresses pointing to data of a second data size smaller than the first data size. The data processing system enables a data transfer by supplying an address to the data memory with zeros substituted for a predetermined number of least significant bits. The data processor receives a data word of the first data size corresponding to the altered address. The data processor stores data of a selected processor data size into a selected data register. If the processor data size is smaller than the first data size, then the date register stores a selected a subset of bits of the data word dependent upon the processor data size and the predetermined number of least significant address bits of said address. The selected processor data size is stored in a qualifier register which may be one of a plurality of qualifier registers corresponding to an address register used to generate the address. The data memory includes a plurality of write strobe inputs. The data processor repeats data recalled from a selected data registers of the selected processor data size a number of times to fill a data word of the first data size. The data processor enables selected write strobes dependent upon the processor data size and the predetermined number of least significant bits of the address.
摘要翻译：一种数据处理系统，包括存储具有第一数据大小的数据字的数据存储器和具有地址生成器的数据处理器，该地址生成器产生指向小于第一数据大小的第二数据大小的数据的地址。数据处理系统通过用代替预定数量的最低有效位的零来向数据存储器提供地址来实现数据传输。数据处理器接收与改变的地址对应的第一数据大小的数据字。数据处理器将所选择的处理器数据大小的数据存储到所选择的数据寄存器中。如果处理器数据大小小于第一数据大小，则日期寄存器根据处理器数据大小和所述地址的预定数目的最低有效地址位来存储选定的数据字的位的子集。所选择的处理器数据大小存储在限定符寄存器中，限定符寄存器可以是与用于生成地址的地址寄存器相对应的多个限定符寄存器之一。数据存储器包括多个写选通输入。数据处理器重复从所选择的处理器数据大小的所选择的数据寄存器中召回的数据，以填充第一数据大小的数据字。数据处理器使得所选择的写入选通取决于处理器数据大小和地址的预定数量的最低有效位。

66. 发明授权

US5398233A Method of resetting coupled modules and system using the method 失效
标题翻译：使用该方法复位耦合模块和系统的方法
公开(公告)号：US5398233A
公开(公告)日：1995-03-14
申请号：US83801
申请日：1993-06-28
申请人： Keith Balmer , Iain C. Robertson
发明人： Keith Balmer , Iain C. Robertson
IPC分类号： G06F13/00 , G06F1/24 , G06F11/07 , H04L29/08 , H04J3/14
CPC分类号： G06F11/0709 , G06F1/24 , G06F11/0793
摘要： A method of resetting coupled modules and a system using the method are disclosed. The method comprises applying a reset instruction signal to a selected module, the selected module generating a reset permission request signal, one or more other modules (other than the selected module) receiving the reset permission request signal and taking necessary action to avoid system malfunction after the selected module is reset, the one or more other modules sending a permission granted signal, and resetting the selected module once it is determined that the one or more modules have sent a permission granted signal. Other methods and systems are disclosed.
摘要翻译：公开了一种复位耦合模块的方法和使用该方法的系统。该方法包括向所选择的模块应用复位指令信号，所选择的模块产生复位许可请求信号，接收复位许可请求信号的一个或多个其他模块（所选择的模块除外），并采取必要的动作以避免系统故障所选择的模块被复位，一个或多个其他模块发送许可授权信号，并且一旦确定一个或多个模块已经发送了许可授权信号，则复位所选择的模块。公开了其它方法和系统。

67. 发明申请

US20080077771A1 Long Instruction Word Controlling Plural Independent Processor Operations 审中-公开
公开(公告)号：US20080077771A1
公开(公告)日：2008-03-27
申请号：US11930652
申请日：2007-10-31
申请人： Karl Guttag , Christopher Read , Keith Balmer
发明人： Karl Guttag , Christopher Read , Keith Balmer
IPC分类号： G06F9/30
CPC分类号： G06F7/53 , G06F7/57 , G06F9/30014 , G06F9/30032 , G06F9/30036 , G06F9/30145 , G06F9/30167 , G06F9/3851 , G06F9/3853 , G06F9/3867 , G06F9/3885 , G06F2207/382
摘要： This invention is a data processing apparatus which operates on instruction controlling plural processor actions. Each instruction includes a data unit section and a data transfer section. These instruction sections are independent and may include differing options. In the preferred embodiment, each instruction is 64 bits. The data unit section includes a data operation field that indicates the type of arithmetic logic unit operation and six operand fields. The six operand fields include four source data register fields and two destination register fields. The data unit (110) includes a multiplication unit (220) and an arithmetic logic unit (230). The data unit (110) may include a barrel rotator (235) for one input of the arithmetic logic unit (230). The rotated data may be stored in the first destination register instead of the multiply result. The address unit (120) operations according to the data transfer operation field. This could be a load, a store or a register to register move. Operations may be conditional based upon conditions stored in a status register (210). The status register (210) is set by a prior output of the arithmetic logic unit (230) and the instruction may specify some of the status bits protect from change. The address unit (120) preferably includes a plurality of base address registers (611), a full adder (615) and a left shifter (614). The full adder (615) may add an index as scaled by the left shifter to the base address or subtract the scaled index from the base address. The full adder (615) output may update the base address register (611), either before supply of the address or following supply of the address. The index may be recalled from an index register (612) or an immediate value. In the preferred embodiment of this invention, the data unit (110) including the data registers (200), the multiplication unit (220) and the arithmetic logic unit (230), the address unit (120) and the instruction decode logic (250, 660) are embodied in at least one digital image/graphics processor (71, 72, 73, 74) as a part of a multiprocessor (100) formed in a single integrated circuit used in image processing.

68. 发明授权

US06839831B2 Data processing apparatus with register file bypass 有权
标题翻译：具有寄存器文件旁路的数据处理设备
公开(公告)号：US06839831B2
公开(公告)日：2005-01-04
申请号：US09733597
申请日：2000-12-08
申请人： Keith Balmer , Richard D. Simpson , Iain Robertson , John Keay
发明人： Keith Balmer , Richard D. Simpson , Iain Robertson , John Keay
IPC分类号： G06F9/30 , G06F9/302 , G06F9/355 , G06F9/38 , G06F9/28
CPC分类号： G06F9/3885 , G06F9/3001 , G06F9/3012 , G06F9/355 , G06F9/3824 , G06F9/3828 , G06F9/3891
摘要： A data processing apparatus includes first (78) and second (80) functional unit groups, each includes a plurality of functional units and a register file (76) comprising a plurality of registers. A comparator (181) receives the operand register number of a current instruction for a functional unit in the first functional unit group, and the destination register number of an immediately preceding instruction for the second functional unit group. A register file bypass multiplexer (174) selects the data from the register corresponding to the operand number of the current instruction on no match and selects the output of the second functional unit group (hotpath 172) if the comparator indicates a match. The first functional unit utilizes the output of the second functional unit group without waiting for the result to be stored in the register file.
摘要翻译：数据处理装置包括第一（78）和第二（80）个功能单元组，每个功能单元组包括多个功能单元和包括多个寄存器的寄存器文件（76）。比较器（181）接收第一功能单元组中的功能单元的当前指令的操作数寄存器号和第二功能单元组的紧接在前的指令的目的地寄存器号。寄存器文件旁路多路复用器（174）在不匹配的情况下从当前指令的操作数编号对应的寄存器中选择数据，如果比较器指示匹配，则选择第二功能单元组（热路径172）的输出。第一功能单元利用第二功能单元组的输出，而不等待结果存储在寄存器文件中。

69. 发明授权

US06745319B1 Microprocessor with instructions for shuffling and dealing data 有权
标题翻译：具有混洗和交易数据指令的微处理器
公开(公告)号：US06745319B1
公开(公告)日：2004-06-01
申请号：US09702452
申请日：2000-10-31
申请人： Keith Balmer , David Hoyle , Lewis Nardini
发明人： Keith Balmer , David Hoyle , Lewis Nardini
IPC分类号： G06F9305
CPC分类号： G06F9/3891 , G06F9/30025 , G06F9/30032 , G06F9/30036 , G06F9/30072 , G06F9/30109 , G06F9/30112 , G06F9/3012 , G06F9/3828 , G06F9/3885
摘要： A data processing system is provided with a digital signal processor (DSP) which has a shuffle instruction for shuffling a source operand (600) and storing the shuffled result in a selected destination register (610). A shuffled result is formed by interleaving bits from a first source operand portion with bits from a second operand portion. A de-interleave and pack (DEAL) instruction is provided for de-interleaving a source operand. The shuffle instruction and the DEAL instruction have an exactly inverse effect. The DSP includes swizzle circuitry that performs interleaving or de-interleaving in a single execution phase.
摘要翻译：数据处理系统具有数字信号处理器（DSP），数字信号处理器（DSP）具有用于混洗源操作数（600）并将洗牌结果存储在所选目的地寄存器（610）中的混洗指令。通过从来自第二操作数部分的位与第一源操作数部分交织比特来形成混洗结果。提供去交错和包（DEAL）指令用于解交织源操作数。随机播放指令和DEAL指令具有完全相反的效果。 DSP包括在单个执行阶段执行交织或解交织的交换电路。

70. 发明授权

US06654834B1 Method and apparatus for data transfer employing closed loop of memory nodes 有权
标题翻译：采用闭环存储器节点进行数据传输的方法和装置
公开(公告)号：US06654834B1
公开(公告)日：2003-11-25
申请号：US09615645
申请日：2000-07-13
申请人： Iain Robertson , John Keay , Amarjit S. Bhandal , Keith Balmer
发明人： Iain Robertson , John Keay , Amarjit S. Bhandal , Keith Balmer
IPC分类号： G06F100
CPC分类号： G06F15/173
摘要： Data transfer between a master node (300) and plural memory nodes (301-308) follows a synchronous fixed latency loop bus (255). Each memory node includes bus interface (311-318) which passes command, write data, address and read data to a next memory node in the loop. Each memory node performs a read from its memory at the specified address if a read command is directed to it. Each memory node performs a write to its memory at the specified address if a write command is directed to it. This configuration provides a fixed latency between the issue of a read command and the return of the read data no matter which memory node is accessed. This configuration prevents collision of returning read data. This configuration retains the issued read and write order preserving proper function for read/write and write/read command pairs. This configuration provides fixed loading to each stage regardless of the number of memory nodes. Thus the design of large systems operating at high speeds is simplified.
摘要翻译：主节点（300）和多个存储节点（301-308）之间的数据传输遵循同步固定等待时间环路总线（255）。每个存储器节点包括总线接口（311-318），其将命令，写入数据，地址和读取数据传递给循环中的下一个存储器节点。如果读取命令被指向，则每个存储器节点在指定的地址处从其存储器执行读取。如果写入命令被指向，则每个存储器节点对指定地址的存储器执行写操作。无论访问哪个存储器节点，此配置都会在发出读命令和读取数据的返回之间提供固定的等待时间。该配置可以防止返回的读取数据发生冲突。该配置保留发出的读写顺序保持读/写和写/读命令对的正确功能。该配置为每个阶段提供固定加载，而不管存储器节点的数量。因此，简化了以高速运行的大型系统的设计。

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