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61. 发明申请

US20060123299A1 Semiconductor integrated circuit and a method of testing the same 有权
公开(公告)号：US20060123299A1
公开(公告)日：2006-06-08
申请号：US11329229
申请日：2006-01-11
申请人： Toshihiro Tanaka , Yutaka Shinagawa , Masahiko Kimura , Isao Nakamura
发明人： Toshihiro Tanaka , Yutaka Shinagawa , Masahiko Kimura , Isao Nakamura
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G11C29/021 , G01R31/30 , G01R31/31703 , G01R31/31725 , G01R31/3187 , G06F11/24 , G11C16/04 , G11C29/02 , G11C29/028 , G11C29/50012 , G11C2029/5004
摘要： A semiconductor integrated circuit (LSI) in which control information for determining a voltage or a width of a pulse produced itself can easily be set in parallel with other LSIs, and set information can be corrected easily. From an external evaluation device, a voltage of an expected value is supplied in overlapping manner to a plurality of LSIs each having a CPU and a flash memory. Each LSI incorporates a comparison circuit comparing an expected voltage value and a boosted voltage generated in itself. The CPU refers to a comparison result and optimizes control data in a data register for changing a boosted voltage. The CPU controls the comparison circuit and the data register and performs trimming in a self-completion manner, thereby making, trimming on a plurality of LSIs easily in a parallel manner and a total test time reduced.

62. 发明申请

US20060028868A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060028868A1
公开(公告)日：2006-02-09
申请号：US11198191
申请日：2005-08-08
申请人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
发明人： Tsutomu Okazaki , Daisuke Okada , Kyoya Nitta , Toshihiro Tanaka , Akira Kato , Toshikazu Matsui , Yasushi Ishii , Digh Hisamoto , Kan Yasui
IPC分类号： G11C11/34 , G11C5/06
CPC分类号： H01L27/1157 , G11C16/0425 , H01L21/28282 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11568 , H01L29/0649 , H01L29/4234 , H01L29/42344 , H01L29/518 , H01L29/66833 , H01L29/792
摘要： Memory cells are disposed in plural array form. Select gate electrodes of the memory cells arranged in an X direction are connected to one another by select gate lines respectively. Memory gate electrodes are connected by memory gate lines respectively. The memory gate lines respectively connected to the memory gate electrodes of the memory cells adjacent to one another through source regions interposed therebetween are not electrically connected to one another. Each of the select gate lines has a first portion that extends in the X direction, and a second portion 9b of which one end is connected to the first portion and extends in a Y direction. The memory gate line is formed on its corresponding sidewall of the select gate line with an insulating film interposed therebetween. The memory gate line has a contact section that extends in the X direction from over a second portion of the select gate line to over an element isolation region, and is connected to its corresponding wiring through a plug that buries a contact hole formed over the contact section.
摘要翻译：存储单元以多个阵列形式布置。选择沿X方向布置的存储单元的选择栅电极分别通过选择栅极线彼此连接。存储器栅极电极分别由存储器栅极线连接。分别连接到彼此相邻的存储单元的存储器栅极的存储栅极线通过其间的源极区域彼此不电连接。每个选择栅极线具有在X方向上延伸的第一部分和其一端连接到第一部分并沿Y方向延伸的第二部分9b。存储栅极线在其选择栅线的相应侧壁上形成有介于其间的绝缘膜。存储栅极线具有接触部分，该接触部分在选择栅极线的第二部分上方在X方向上延伸到元件隔离区域上方，并且通过塞子连接到其对应的布线，所述插头埋设形成在触点上的接触孔部分。

63. 发明申请

US20050285181A1 Non-volatil semiconductor memory device and writing method thereof 有权
标题翻译：非挥发性半导体存储器件及其写入方法
公开(公告)号：US20050285181A1
公开(公告)日：2005-12-29
申请号：US11147243
申请日：2005-06-08
申请人： Kan Yasui , Digh Hisamoto , Toshihiro Tanaka , Takashi Yamaki
发明人： Kan Yasui , Digh Hisamoto , Toshihiro Tanaka , Takashi Yamaki
IPC分类号： G11C16/02 , G11C16/04 , G11C16/34 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792
CPC分类号： G11C16/3418 , G11C16/0466 , G11C16/3427 , H01L27/115 , H01L29/4232 , H01L29/792
摘要： In a non-volatile semiconductor memory device using a charge storage film, it is intended to prevent a sequence disturb such as an erroneous write or erase of another memory cell on one and same word line which occurs depending on a bias transition path in stand-by state and write state. In connection with rise and fall of a word line bias, the present invention adopts a procedure such that a diffusion region voltage Vs on a memory transistor side is changed, and after the voltage Vs passes a certain intermediate value Vsx, a gate voltage Vmg of the memory transistor is changed. Alternatively, there is adopted a procedure such that the gate voltage Vmg of the memory transistor is changed, and after the voltage Vmg passes a certain intermediate value Vmgx, the diffusion layer voltage Vs on the memory transistor side is changed. The values of Vsx and Vmgx are determined from the magnitude of the electric field in a gate insulating film not causing FN tunneling electron injection that causes a change in threshold voltage and the magnitude of a potential barrier against holes not causing BTBT hot hole injection.
摘要翻译：在使用电荷存储膜的非易失性半导体存储器件中，旨在防止在根据独立的偏置过渡路径发生的同一字线上的另一个存储单元的错误写入或擦除的序列干扰，按状态和写状态。关于字线偏差的上升和下降，本发明采用使存储晶体管侧的扩散区电压Vs变化的过程，在电压Vs经过一定的中间值Vsx之后，栅极电压Vmg为存储晶体管被改变。或者，采用使存储晶体管的栅极电压Vmg改变的过程，并且在电压Vmg经过一定的中间值Vmgx之后，存储晶体管侧的扩散层电压Vs被改变。 Vsx和Vmgx的值由栅极绝缘膜中不引起FN隧穿电子注入的电场的大小确定，导致阈值电压的变化以及针对未引起BTBT热空穴注入的孔的势垒的大小。

64. 发明申请

US20050129830A1 Oil or fat composition 有权
标题翻译：油脂组成
公开(公告)号：US20050129830A1
公开(公告)日：2005-06-16
申请号：US11049975
申请日：2005-02-04
申请人： Shin Koike , Takatoshi Murase , Takanori Nii , Toshihiro Tanaka
发明人： Shin Koike , Takatoshi Murase , Takanori Nii , Toshihiro Tanaka
IPC分类号： A23D7/01 , A23D9/013 , A23K1/16 , A23L1/30 , A23L1/325 , A61K31/19 , A61K31/215 , A61K31/23 , A61K31/565 , A23D7/00
CPC分类号： A61K31/215 , A23D7/013 , A23D9/013 , A23K20/158 , A23L17/70 , A23L33/12 , A23V2002/00 , A61K31/19 , A61K31/23 , A61K31/565 , A61K2300/00 , A23V2250/1868 , A23V2250/712 , A23V2250/21 , A23V2250/2116 , A23V2250/187 , A23V2250/192 , A23V2250/182 , A23V2250/2136
摘要： The present invention relates to an oil or fat composition containing the following components (A) and (B): (A) from 80 to 99.9 wt. % of a monoglyceride containing 20 to 75 wt. % of docosahexaenoic acid (DHA) and 0.1 to 25 wt. % of icosapentaenoic acid (IPA), as the constituent fatty acids thereof, wherein the weight ratio of DHA/IPA being 2 or more; and (B) from 0.1 to 20 wt. % of a diglyceride.
摘要翻译：本发明涉及含有以下组分（A）和（B）的油或脂肪组合物：（A）80-99.9重量％％的单酸甘油酯含有20〜75wt。二十二碳六烯酸（DHA）的百分比和0.1至25wt。％的二十碳五烯酸（IPA）作为其构成脂肪酸，其中DHA / IPA的重量比为2以上; 和（B）0.1至20wt。％的甘油二酯。

65. 发明授权

US06869299B2 Power supply unit for electronic devices 失效
标题翻译：电子设备电源单元
公开(公告)号：US06869299B2
公开(公告)日：2005-03-22
申请号：US10700742
申请日：2003-11-04
申请人： Toshihiro Tanaka , Katsumi Myochin
发明人： Toshihiro Tanaka , Katsumi Myochin
IPC分类号： H01R13/71 , H01M2/10 , H01R13/05 , H01R13/24 , H01R13/26 , H01R29/00
CPC分类号： H01R13/26 , H01R13/05 , H01R13/24
摘要： A power supply unit for electronic devices has an insulating battery pack holder with a hollow portion to accommodate a battery pack detachably; a plurality of connector contacts and a switch contact formed of conductive metal and disposed inside the battery pack holder, part of each connector contact protruding toward the hollow portion, the switch contact capable of detaching from or attaching to a predetermined one of the connector contacts with a moving contact portion. When the battery pack is accommodated in the hollow portion, its electrode terminals elastically touch corresponding connector contacts to be conductively connected to a driver circuit. In removal of the battery pack from the hollow portion, when the predetermined connector contact protrudes into the hollow portion by a predetermined distance according to a reduction in urging force of the electrode terminal, the predetermined connector contact touches the switch contact to output a detection signal.
摘要翻译：一种用于电子设备的电源单元具有绝缘电池组保持器，其具有中空部分以可拆卸地容纳电池组; 多个连接器触点和由导电金属形成并设置在电池组保持器内部的开关触点，每个连接器触头的朝向中空部分突出的部分，开关触点能够与预定的一个连接器触点分离或附接到连接器触点中，移动接触部分。当电池组被容纳在中空部分中时，其电极端子弹性地接触相应的连接器触头以与驱动电路导电连接。在从中空部分移除电池组时，当预定的连接器触点根据电极端子的推动力的减小而突出到中空部分预定距离时，预定的连接器触头触摸开关触点以输出检测信号。

66. 发明授权

US06738310B2 Nonvolatile semiconductor memory 失效
公开(公告)号：US06738310B2
公开(公告)日：2004-05-18
申请号：US10351524
申请日：2003-01-27
申请人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
发明人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
IPC分类号： G11C700
CPC分类号： G11C16/0416 , G11C8/08 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/34 , G11C16/3418 , G11C16/3427 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

67. 发明授权

US06713771B2 Method and apparatus for electromagnetic irradiation of liquid 失效
标题翻译：将电磁波施加到液体的装置和方法
公开(公告)号：US06713771B2
公开(公告)日：2004-03-30
申请号：US10204599
申请日：2002-11-26
申请人： Sota Nakagawa , Toshihiro Tanaka , Yasushi Kosaka , Mitsuru Imai
发明人： Sota Nakagawa , Toshihiro Tanaka , Yasushi Kosaka , Mitsuru Imai
IPC分类号： H01J3706
CPC分类号： B01J19/123 , B01J19/125 , B01J19/127 , B01J19/128 , B01J19/129 , B01J19/247 , C02F1/325 , C02F1/38 , C02F1/722 , C02F1/725 , C02F1/78 , C02F2101/36 , C02F2103/06 , C02F2201/3223
摘要： An electromagnetic wave applying apparatus having an electromagnetic wave source (13) such as an ultraviolet lamp or the like, a cylinder (15) surrounding the electromagnetic wave source, a liquid retention tank (16) disposed around the cylinder, and an inlet portion (17) for introducing a liquid overflow from the liquid retention tank as a thin film flowing down an inner wall surface of the cylinder, which is irradiated with an electromagnetic wave from the ultraviolet lamp (11). The electromagnetic wave applying apparatus also has swirling flow forming means for causing the liquid introduced from the inlet portion (17) onto the inner wall surface of the cylinder to flow as a swirling flow down the inner wall surface. The electromagnetic wave applying apparatus allows a large amount of liquid to be stably treated by the application of an electromagnetic wave without causing the electromagnetic wave source such as an ultraviolet lamp or the like to be contaminated.
摘要翻译：具有紫外线灯等电磁波源（13）的电磁波施加装置，围绕电磁波源的圆筒（15），设置在圆筒上的液体保持箱（16）和入口部（ 17），其用于从液体保持槽引入液体溢出，作为从所述紫外灯（11）照射了电磁波的从所述气缸的内壁面向下流动的薄膜。电磁波施加装置还具有旋转流形成装置，用于使从入口部分（17）引入到圆筒的内壁表面上的液体沿着内壁表面沿着旋流流动。电磁波施加装置允许通过施加电磁波来稳定地处理大量的液体，而不会使诸如紫外线灯等的电磁波源被污染。

68. 发明授权

US06711061B2 Non-volatile semiconductor memory device for selectively re-checking word lines 有权
标题翻译：用于选择性地重新检查字线的非易失性半导体存储器件
公开(公告)号：US06711061B2
公开(公告)日：2004-03-23
申请号：US10223488
申请日：2002-08-20
申请人： Nozomu Matsuzaki , Kazuyoshi Shiba , Yasuhiro Taniguchi , Toshihiro Tanaka , Yutaka Shinagawa
发明人： Nozomu Matsuzaki , Kazuyoshi Shiba , Yasuhiro Taniguchi , Toshihiro Tanaka , Yutaka Shinagawa
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C8/08 , G11C16/12 , G11C16/3404
摘要： A method for settling threshold voltages of word lines on a predetermined level in an erasing processing of a non-volatile semiconductor memory device so as to speed up the erasing processing. A word latch circuit is provided for each word line and the threshold voltage of each memory cell is managed for each word line in a selected memory block. Each word latch circuit is shared by a plurality of word lines so as to reduce the required chip area. A rewriting voltage is set for each finished non-volatile memory and the voltage information is stored in the boot area of the non-volatile memory, so that the voltage is recognized by the system each time the system is powered.
摘要翻译：一种用于在非易失性半导体存储器件的擦除处理中在预定电平上建立字线的阈值电压的方法，以加速擦除处理。为每个字线提供字锁存电路，并且在所选择的存储器块中为每个字线管理每个存储器单元的阈值电压。每个字锁存电路由多个字线共享，以便减少所需的芯片面积。为每个完成的非易失性存储器设置重写电压，并且电压信息被存储在非易失性存储器的引导区域中，使得每当系统供电时，系统识别电压。

69. 发明授权

US06643193B2 Semiconductor device, microcomputer and flash memory 有权
公开(公告)号：US06643193B2
公开(公告)日：2003-11-04
申请号：US10247301
申请日：2002-09-20
申请人： Takashi Yamaki , Kan Takeuchi , Mitsuru Hirakii , Toshihiro Tanaka , Yutaka Shinagawa , Masamichi Fujito
发明人： Takashi Yamaki , Kan Takeuchi , Mitsuru Hirakii , Toshihiro Tanaka , Yutaka Shinagawa , Masamichi Fujito
IPC分类号： G11C700
CPC分类号： G11C29/50008 , G11C11/5628 , G11C11/5642 , G11C16/04 , G11C16/28 , G11C16/30 , G11C29/02 , G11C29/021 , G11C29/028
摘要： A semiconductor device whose characteristics are highly reliably regulated for circuits whose desired characteristics need to be realized without being affect by unevenness in device characteristics is to be provided. A replica MOS transistor for amperage measurement connected to an external measuring terminal is provided. A delay circuit and other circuits whose desired characteristics are to be realized have a constant current source MOS transistor formed in the same process as the replica MOS transistor, and a trimming voltage vtri is commonly applied to the respective gates of the constant current source MOS transistor and the replica MOS transistor. Trimming data determined on the basis of an amperage measured from the external measuring terminal are stored into a memory means such as an electrically rewritable non-volatile memory or the like. The trimming data determine the trimming voltage vtri.

70. 发明授权

US06519184B2 Non-volatile memory device with plurality of threshold voltage distributions 失效
公开(公告)号：US06519184B2
公开(公告)日：2003-02-11
申请号：US10082335
申请日：2002-02-26
申请人： Toshihiro Tanaka , Hiroyuki Tanikawa , Masayoshi Nakano , Norio Oza , Koki Watanabe , Yutaka Shinagawa
发明人： Toshihiro Tanaka , Hiroyuki Tanikawa , Masayoshi Nakano , Norio Oza , Koki Watanabe , Yutaka Shinagawa
IPC分类号： G11C1606
CPC分类号： G11C16/344 , G11C16/3468
摘要： In a verify operation after a write or erase to check whether a memory cell threshold voltage is contained in a predetermined threshold voltage distribution, verify voltage is changed in three stages or more in a direction to mitigate the decision condition. This prevents non-convergence of write and erase operation and can complete the write or erase in a short time.

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