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61. 发明申请

US20100284210A1 One-time programmable memory cell 审中-公开
标题翻译：一次性可编程存储单元
公开(公告)号：US20100284210A1
公开(公告)日：2010-11-11
申请号：US12387573
申请日：2009-05-05
申请人： Henry Kuo-Shun Chen , Xiangdong Chen , Wei Xia
发明人： Henry Kuo-Shun Chen , Xiangdong Chen , Wei Xia
IPC分类号： G11C17/00
CPC分类号： G11C17/16
摘要： According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a cell transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The cell transistor has a source, a gate, and a body shorted together. A programming operation causes a punchthrough to occur between the source and a drain of the cell transistor in response to a programming voltage on the bitline and the wordline. A channel length of the cell transistor is substantially less than a channel length of the access transistor. In one embodiment, the access transistor is an NFET while the cell transistor is a PFET. In another embodiment, the access transistor is an NFET and the cell transistor is also an NFET. Various embodiments result in a reduction of the required programming voltage.
摘要翻译：根据一个示例性实施例，一次性可编程存储器单元包括耦合到位线和地之间的单元晶体管的存取晶体管，其中存取晶体管具有耦合到字线的栅极。单元晶体管具有源极，栅极和与之短接在一起的主体。响应于位线和字线上的编程电压，编程操作导致在单元晶体管的源极和漏极之间发生穿透。单元晶体管的沟道长度基本上小于存取晶体管的沟道长度。在一个实施例中，存取晶体管是NFET，而单元晶体管是PFET。在另一个实施例中，存取晶体管是NFET，单元晶体管也是NFET。各种实施例导致所需编程电压的降低。

62. 发明申请

US20090289280A1 Method for Making Transistors and the Device Thereof 审中-公开
标题翻译：制造晶体管及其器件的方法
公开(公告)号：US20090289280A1
公开(公告)日：2009-11-26
申请号：US12125853
申请日：2008-05-22
申请人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
发明人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
IPC分类号： H01L27/092 , H01L21/336 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/1054 , H01L29/165 , H01L29/66636 , H01L29/7843 , H01L29/7848
摘要： A semiconductor process and apparatus includes forming channel orientation PMOS transistors (34) with enhanced hole mobility in the channel region of a transistor by epitaxially growing a bi-axially stressed silicon germanium channel region layer (22), alone or in combination with an underlying silicon carbide layer (86), prior to forming a PMOS gate structure (36) overlying the channel region layer, and then depositing a neutral (53) or compressive (55) contact etch stop layer over the PMOS gate structure. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.
摘要翻译：半导体工艺和装置包括通过外延生长双轴向应力的硅锗沟道区域层（22）来形成具有增强的晶体管沟道区中的空穴迁移率的<100>沟道取向PMOS晶体管（34），单独或与在形成覆盖在沟道区域层上的PMOS栅极结构（36）之前，然后在PMOS栅极结构上沉积中性（53）或压缩（55）接触蚀刻停止层之后的底层碳化硅层（86）。也可以在PMOS栅极结构（70）附近形成嵌入硅锗源极/漏极区（84），以向双轴向应力沟道区提供额外的单轴应力。

63. 发明申请

US20090146263A1 STRUCTURE AND METHOD TO INCREASE EFFECTIVE MOSFET WIDTH 有权
标题翻译：增加有效MOSFET宽度的结构和方法
公开(公告)号：US20090146263A1
公开(公告)日：2009-06-11
申请号：US11953445
申请日：2007-12-10
申请人： Xiangdong Chen , Kenneth J. Stein , Thomas A. Wallner
发明人： Xiangdong Chen , Kenneth J. Stein , Thomas A. Wallner
IPC分类号： H01L29/04 , H01L21/336
CPC分类号： H01L21/76232 , H01L29/66651
摘要： An epitaxial layer of silicon (Si) or silicon-germanium (SiGe) extends over the edge of silicon trench isolation (STI), thereby increasing the effective width of an active silicon region (RX) bordered by the STI. The RX region may have a crystal orientation. An effective width of an FET device formed in the RX region may be increased, therefore performance may be improved with same density. Isolation may not be degraded since RX-to-RX distance is same at bottom. Junction capacitance may be reduced since part of the RX is on STI.
摘要翻译：硅（Si）或硅锗（SiGe）的外延层在硅沟槽隔离（STI）的边缘上延伸，从而增加由STI界定的有源硅区域（RX）的有效宽度。 RX区域可以具有<100>晶体取向。可以增加在RX区域中形成的FET器件的有效宽度，因此可以以相同的密度提高性能。隔离可能不会降低，因为RX至RX距离在底部相同。由于RX的一部分在STI上，结电容可能会降低。

64. 发明授权

US07521308B2 Dual layer stress liner for MOSFETS 失效
标题翻译：用于MOSFET的双层应力衬垫
公开(公告)号：US07521308B2
公开(公告)日：2009-04-21
申请号：US11616147
申请日：2006-12-26
申请人： Deleep R. Nair , Christopher V. Baiocco , Xiangdong Chen , Junjung Kim , Jae-eun Park , Daewon Yang
发明人： Deleep R. Nair , Christopher V. Baiocco , Xiangdong Chen , Junjung Kim , Jae-eun Park , Daewon Yang
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/31604 , H01L29/66575
摘要： A method of producing a metal oxide semiconductor field effect transistor (MOSFET) creates a transistor by patterning a gate structure over a substrate, forming spacers on sides of the gate structure, and forming conductor regions within the substrate on alternate sides of the gate stack. The gate structure and the conductor regions make up the transistor. In order to reduce high power plasma induced damage, the method initially applies a first plasma having a first power level to the transistor to form a first stress layer over the transistor. After the first lower-power plasma is applied, the method then applies a second plasma having a second power level to the transistor to from a second stress layer over the first stress layer. The second power level is higher (e.g., at least 5 times higher) than the first power level.
摘要翻译：制造金属氧化物半导体场效应晶体管（MOSFET）的方法通过在衬底上图案化栅极结构来形成晶体管，在栅极结构的侧面上形成间隔物，以及在栅极堆叠的另一侧上在衬底内形成导体区域。栅极结构和导体区域构成晶体管。为了减少高功率等离子体引起的损伤，该方法首先将具有第一功率电平的第一等离子体施加到晶体管，以在晶体管上形成第一应力层。在施加第一低功率等离子体之后，该方法然后将第二等离子体具有第二功率电平施加到第一应力层上的第二应力层至晶体管。第二功率电平比第一功率电平高（例如，至少高5倍）。

65. 发明授权

US07442585B2 MOSFET with laterally graded channel region and method for manufacturing same 有权
标题翻译：具有横向渐变通道区域的MOSFET及其制造方法
公开(公告)号：US07442585B2
公开(公告)日：2008-10-28
申请号：US11162126
申请日：2005-08-30
申请人： Huilong Zhu , Xiangdong Chen
发明人： Huilong Zhu , Xiangdong Chen
IPC分类号： H01L21/00
CPC分类号： H01L21/26506 , H01L21/28132 , H01L29/1054 , H01L29/6656 , H01L29/66636 , H01L29/66659 , H01L29/66742 , H01L29/7834 , H01L29/78684 , H01L29/78696
摘要： The present invention relates generally to a semiconductor device having a channel region comprising a semiconductor alloy of a first semiconductor material and a second, different material, and wherein atomic distribution of the second material in the channel region is graded along a direction that is substantially parallel to a substrate surface in which the semiconductor device is located. Specifically, the semiconductor device comprises a field effect transistor (FET) that has a SiGe channel with a laterally graded germanium content.
摘要翻译：本发明一般涉及具有包括第一半导体材料和第二不同材料的半导体合金的沟道区的半导体器件，并且其中沟道区中的第二材料的原子分布沿着基本平行的方向分级到半导体器件所在的衬底表面。具体地，半导体器件包括具有横向渐变的锗含量的SiGe沟道的场效应晶体管（FET）。

66. 发明申请

US20080237733A1 STRUCTURE AND METHOD TO ENHANCE CHANNEL STRESS BY USING OPTIMIZED STI STRESS AND NITRIDE CAPPING LAYER STRESS 审中-公开
标题翻译：使用优化的STI应力和氮化物覆盖层应力来增强通道应力的结构和方法
公开(公告)号：US20080237733A1
公开(公告)日：2008-10-02
申请号：US11691699
申请日：2007-03-27
申请人： Xiangdong Chen , Zhijiong Luo , Huilong Zhu
发明人： Xiangdong Chen , Zhijiong Luo , Huilong Zhu
IPC分类号： H01L29/78 , H01L21/8232
CPC分类号： H01L21/823878 , H01L21/823807 , H01L29/665 , H01L29/7843 , H01L29/7846
摘要： The embodiments of the invention provide a structure and method to enhance channel stress by using optimized STI stress and nitride capping layer stress. More specifically, a transistor structure is provided comprising a substrate having a first transistor region and a second transistor region, different than the first transistor region. Moreover, first transistors are provided over the first transistor region and second transistors, different than the first transistors, are provided over the second transistors region. The first transistor comprises an NFET and the second transistor comprises a PFET. The structure further includes STI regions in the substrate adjacent sides of the first transistors and the second transistors, wherein the STI regions comprise stress producing regions. Recesses are within at least two of the STI regions, such that portions of at least one of said first stress liner and said second stress liner are positioned within said recesses.
摘要翻译：本发明的实施例提供了通过使用优化的STI应力和氮化物覆盖层应力来增强通道应力的结构和方法。更具体地，提供了晶体管结构，其包括具有不同于第一晶体管区域的第一晶体管区域和第二晶体管区域的衬底。此外，在第一晶体管区域上提供第一晶体管，并且在第二晶体管区域上提供与第一晶体管不同的第二晶体管。第一晶体管包括NFET，第二晶体管包括PFET。该结构还包括在第一晶体管和第二晶体管的相邻侧面的衬底中的STI区域，其中STI区域包括应力产生区域。凹陷部位在至少两个STI区域内，使得至少一个所述第一应力衬垫和所述第二应力衬垫的部分位于所述凹部内。

67. 发明申请

US20080142896A1 SELECTIVE STRESS ENGINEERING FOR SRAM STABILITY IMPROVEMENT 失效
标题翻译：用于SRAM稳定性改进的选择性应力工程
公开(公告)号：US20080142896A1
公开(公告)日：2008-06-19
申请号：US11612643
申请日：2006-12-19
申请人： Xiangdong Chen , Young G. Ko , Haining Yang
发明人： Xiangdong Chen , Young G. Ko , Haining Yang
IPC分类号： H01L27/11
CPC分类号： H01L27/11 , H01L29/7847 , Y10S257/903
摘要： An integrated circuit (IC) structure including a SRAM cell is provided in which the performance of the pass-gate transistors is degraded in order to increase the beta ratio of the transistors within the SRAM cell. In particular, the increased beta ratio is obtained in the present invention by intentionally improving only the performance of the pull-down transistors, while degrading the performance of the pass-gate transistors. This result is achieved in the present invention by implementing stress memorization technique on logic complementary metal oxide semiconductor (CMOS) nFETs and SRAM pull-down transistors to improve the nFET performance. The stress memorization technique is not performed at the pFET region to avoid performance degradation as well as at the SRAM pass-gate transistors to avoid the improvement. With performance improvement at the pull-down transistors and no performance improvement at the pass-gate transistors, the beta ratio of the SRAM transistors is improved.
摘要翻译：提供了包括SRAM单元的集成电路（IC）结构，其中栅极晶体管的性能降低，以便增加SRAM单元内的晶体管的β比。特别地，本发明中通过有意地仅改善下拉晶体管的性能，同时降低栅极晶体管的性能来获得增加的β比。通过在逻辑互补金属氧化物半导体（CMOS）nFET和SRAM下拉晶体管上实施应力记忆技术来提高nFET性能，在本发明中实现了该结果。在pFET区域不进行应力记忆技术，以避免性能下降以及在SRAM栅极晶体管中避免改进。随着下拉晶体管的性能改善，传递栅极晶体管的性能得不到改善，SRAM晶体管的β比率得到了改善。

68. 发明授权

US07388267B1 Selective stress engineering for SRAM stability improvement 失效
标题翻译： SRAM稳定性改进的选择性应力工程
公开(公告)号：US07388267B1
公开(公告)日：2008-06-17
申请号：US11612643
申请日：2006-12-19
申请人： Xiangdong Chen , Young G. Ko , Haining Yang
发明人： Xiangdong Chen , Young G. Ko , Haining Yang
IPC分类号： H01L29/78
CPC分类号： H01L27/11 , H01L29/7847 , Y10S257/903
摘要： An integrated circuit (IC) structure including a SRAM cell is provided in which the performance of the pass-gate transistors is degraded in order to increase the beta ratio of the transistors within the SRAM cell. In particular, the increased beta ratio is obtained in the present invention by intentionally improving only the performance of the pull-down transistors, while degrading the performance of the pass-gate transistors. This result is achieved in the present invention by implementing stress memorization technique on logic complementary metal oxide semiconductor (CMOS) nFETs and SRAM pull-down transistors to improve the nFET performance. The stress memorization technique is not performed at the pFET region to avoid performance degradation as well as at the SRAM pass-gate transistors to avoid the improvement. With performance improvement at the pull-down transistors and no performance improvement at the pass-gate transistors, the beta ratio of the SRAM transistors is improved.
摘要翻译：提供了包括SRAM单元的集成电路（IC）结构，其中栅极晶体管的性能降低，以便增加SRAM单元内的晶体管的β比。特别地，本发明中通过有意地仅改善下拉晶体管的性能，同时降低栅极晶体管的性能来获得增加的β比。通过在逻辑互补金属氧化物半导体（CMOS）nFET和SRAM下拉晶体管上实施应力记忆技术来提高nFET性能，在本发明中实现了该结果。在pFET区域不进行应力记忆技术，以避免性能下降以及在SRAM栅极晶体管中避免改进。随着下拉晶体管的性能改善，传递栅极晶体管的性能得不到改善，SRAM晶体管的β比率得到了改善。

69. 发明授权

US07354822B2 Method of forming a MOSFET with dual work function materials 有权
标题翻译：用双功能材料形成MOSFET的方法
公开(公告)号：US07354822B2
公开(公告)日：2008-04-08
申请号：US11553072
申请日：2006-10-26
申请人： Xiangdong Chen , Geng Wang , Yujun Li , Qiqing C. Ouyang
发明人： Xiangdong Chen , Geng Wang , Yujun Li , Qiqing C. Ouyang
IPC分类号： H01L21/8242
CPC分类号： H01L29/66181 , H01L27/10864
摘要： A vertical pass transistor used in a DRAM cell for maintaining a low total leakage current and providing adequate drive current is described together with a method of fabricating such a device. The transistor gate is engineered in lieu of the channel. The vertical pass transistor for the DRAM cell incorporates two gate materials having different work functions. The gate material near the storage node is n-type doped polysilicon. The gate material near the bit line diffusion is made of silicide or metal having a higher work function than the n-polysilicon. The novel device structure shows several advantages: the channel doping is reduced while maintaining a high Vt and a low sub-threshold leakage current; the carrier mobility improves with the reduced channel doping; the body effect of the device is reduced which improves the write back current; and the sub-threshold swing is reduced because of the low channel doping.
摘要翻译：在DRAM单元中使用的用于保持低总漏电流并提供足够的驱动电流的垂直传输晶体管与制造这种器件的方法一起被描述。晶体管栅极被设计代替通道。用于DRAM单元的垂直传输晶体管包括具有不同功函数的两个栅极材料。存储节点附近的栅极材料为n型掺杂多晶硅。位线扩散附近的栅极材料由具有比n-多晶硅更高的功函数的硅化物或金属制成。该新颖的器件结构显示出几个优点：沟道掺杂减少，同时保持高Vt和低的亚阈值漏电流; 载流子迁移率随着沟道掺杂的降低而提高; 减少了器件的体效，提高了回写电流; 并且由于低通道掺杂，子阈值摆幅减小。

70. 发明申请

US20080048269A1 METHOD OF FABRICATING STRUCTURE FOR INTEGRATED CIRCUIT INCORPORATING HYBRID ORIENTATION TECHNOLOGY AND TRENCH ISOLATION REGIONS 审中-公开
标题翻译：整合电路结合混合方向技术与热分解区域的方法
公开(公告)号：US20080048269A1
公开(公告)日：2008-02-28
申请号：US11467325
申请日：2006-08-25
申请人： Xiangdong Chen , Yong Meng Lee
发明人： Xiangdong Chen , Yong Meng Lee
IPC分类号： H01L29/94
CPC分类号： H01L21/823807 , H01L21/823878 , H01L27/0922
摘要： An embodiment of the present invention discloses a method of fabricating a structure for an integrated circuit incorporating hybrid orientation technology (HOT) and trench isolation regions. The structure of the integrated circuit comprising: a substrate with a first silicon layer of a first crystalline orientation and a second silicon layer, of a second crystalline orientation different from the first crystalline orientation, disposed on the first silicon layer; a dielectric layer on the substrate; a first silicon active trench region, having first crystalline orientation, extending to the first silicon layer; a second silicon active trench region, having the second crystalline orientation, extending to the second silicon layer, the first silicon active region electrically isolated from the second silicon active region by a portion of the dielectric layer; a first transistor on the first silicon active region; and a second transistor on the second silicon active region.
摘要翻译：本发明的实施例公开了一种制造用于集成混合取向技术（HOT）和沟槽隔离区域的集成电路的结构的方法。所述集成电路的结构包括：设置在所述第一硅层上的具有第一晶体取向的第一硅层和与所述第一晶体取向不同的第二晶体取向的第二硅层的衬底; 基底上的电介质层; 具有第一晶体取向的第一硅有源沟槽区，延伸到第一硅层; 具有第二晶体取向的第二硅有源沟槽区延伸到第二硅层，第一硅有源区通过介电层的一部分与第二硅有源区电隔离; 在第一硅有源区上的第一晶体管; 以及在第二硅有源区上的第二晶体管。

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