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61. 发明授权

US06867142B2 Method to prevent electrical shorts between tungsten interconnects 有权
标题翻译：防止钨互连之间电气短路的方法
公开(公告)号：US06867142B2
公开(公告)日：2005-03-15
申请号：US10247422
申请日：2002-09-18
申请人： Yi-Nan Chen , Shing-Yih Shih , Hsien-Wen Liu
发明人： Yi-Nan Chen , Shing-Yih Shih , Hsien-Wen Liu
IPC分类号： H01L21/321 , H01L21/3213 , H01L21/768 , H01L21/302 , C09K13/00
CPC分类号： H01L21/32134 , H01L21/3212 , H01L21/76877
摘要： A method to prevent electrical shorts between tungsten interconnects. First, a semiconductor substrate having an insulating layer thereon is provided. Then, the insulating layer is selectively etched to form a trench for interconnect. Then, a titanium nitride film is conformally deposited on the surface of the trench and the insulating layer. A tungsten layer is then deposited to fill the trench. Next, the tungsten layer above the titanium nitride film is removed by an ammonia hydrogen peroxide mixture (APM) solution. Next, the titanium nitride film above the insulating layer is removed by a sulfuric acid hydrogen peroxide mixture (SPM) solution to leave a tungsten interconnect within the trench.
摘要翻译：防止钨互连之间电短路的方法。首先，提供其上具有绝缘层的半导体衬底。然后，选择性地蚀刻绝缘层以形成用于互连的沟槽。然后，氮化钛膜被共形沉积在沟槽和绝缘层的表面上。然后沉积钨层以填充沟槽。接下来，通过氨过氧化氢混合物（APM）溶液除去氮化钛膜上方的钨层。接下来，通过硫酸过氧化氢混合物（SPM）溶液除去绝缘层上方的氮化钛膜，以在沟槽内留下钨互连。

62. 发明授权

US08723261B2 Recessed gate transistor with cylindrical fins 有权
标题翻译：带圆柱形鳍片的嵌入式晶体管
公开(公告)号：US08723261B2
公开(公告)日：2014-05-13
申请号：US13081499
申请日：2011-04-07
申请人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L27/12
CPC分类号： H01L27/10879 , H01L27/10826 , H01L29/4236 , H01L29/785
摘要： A recessed gate transistor with cylindrical fins is disclosed. The recessed gate transistor is disposed in an active region of a semiconductor substrate. Two isolation regions disposed in the semiconductor substrate to define an active region therebetween. The recessed gate transistor includes a gate structure, a source doping region and a drain doping region. The gate structure has at least three fins forms a concave and convex bottom of the gate structure. The front fin is disposed in one of the two isolation regions, the middle fin is disposed in the active region and a last fin disposed in the other one of the two isolation regions. The front fin and the last fin are both cylindrical. A lower part of the gate structure is M-shaped when view from the source doping region to the drain doping region direction.
摘要翻译：公开了一种具有圆柱形翅片的嵌入式栅极晶体管。凹陷栅极晶体管设置在半导体衬底的有源区中。设置在半导体衬底中以限定它们之间的有源区的两个隔离区。凹陷栅晶体管包括栅极结构，源极掺杂区和漏极掺杂区。栅极结构具有至少三个鳍形成栅极结构的凹凸底部。前鳍设置在两个隔离区域之一中，中间翅片设置在有源区域中，最后一个翅片设置在两个隔离区域中的另一个中。前鳍和最后的鳍都是圆柱形的。当从源极掺杂区域到漏极掺杂区域方向观察时，栅极结构的下部是M形的。

63. 发明授权

US08614467B2 Method of gate work function adjustment and metal gate transistor 有权
标题翻译：栅极功能调节方法和金属栅极晶体管
公开(公告)号：US08614467B2
公开(公告)日：2013-12-24
申请号：US13081505
申请日：2011-04-07
申请人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L29/66
CPC分类号： H01L29/4983 , H01L21/265 , H01L21/26586 , H01L21/28079 , H01L21/28105 , H01L29/495 , H01L29/66575 , H01L29/66795 , H01L29/78 , H01L29/7856
摘要： A method of gate work function adjustment includes the steps as follow. First, a substrate is provided, wherein a metal gate is disposed on the substrate, a source doping region and a drain doping region are disposed in the substrate at opposite sites of the metal gate, wherein the metal gate is divided into a source side adjacent to the source doping region, and a drain side adjacent to the drain doping region. Later, a mask layer is formed to cover the source doping region and the drain doping region. After that, an implantation process is performed to implant nitrogen into the metal gate so as to make a first nitrogen concentration of the source side higher than a second nitrogen concentration of the drain side. Finally, the mask layer is removed.
摘要翻译：门功功能调整方法包括以下步骤。首先，提供基板，其中金属栅极设置在基板上，源极掺杂区域和漏极掺杂区域设置在金属栅极的相对位置处的基板中，其中金属栅极被分成相邻的源极侧到源极掺杂区域和与漏极掺杂区域相邻的漏极侧。然后，形成掩模层以覆盖源极掺杂区域和漏极掺杂区域。之后，进行注入工艺以将氮注入到金属栅中，以使源极侧的第一氮浓度高于漏极侧的第二氮浓度。最后，去除掩模层。

64. 发明授权

US08536056B2 Method of forming conductive pattern 有权
标题翻译：形成导电图案的方法
公开(公告)号：US08536056B2
公开(公告)日：2013-09-17
申请号：US13214244
申请日：2011-08-22
申请人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
发明人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/28
CPC分类号： H01L21/321 , H01L21/76856 , H01L21/76861 , H01L21/76876 , H01L21/76885
摘要： A method of forming conductive pattern is provided. A seeding layer is formed on an underlayer. By using an energy ray, an irradiation treatment is performed on a portion of a surface of the seeding layer. The seeding layer thus includes a plurality of irradiated regions and a plurality of unirradiated regions. A conversion treatment is performed on the irradiated regions of the seeding layer. A selective growth process is performed, so as to form a conductive pattern on each unirradiated region of the seeding layer. The irradiated regions of the seeding layer are removed, so that the conductive patterns are insulated from each other.
摘要翻译：提供形成导电图案的方法。在底层上形成接种层。通过使用能量射线，对接种层的表面的一部分进行照射处理。因此，接种层包括多个照射区域和多个未照射区域。对接种层的照射区域进行转化处理。进行选择性生长处理，以在接种层的每个未照射区域上形成导电图案。去除接种层的照射区域，使得导电图案彼此绝缘。

65. 发明授权

US08530306B2 Method of forming a slit recess channel gate 有权
标题翻译：形成狭缝凹槽通道浇口的方法
公开(公告)号：US08530306B2
公开(公告)日：2013-09-10
申请号：US13117162
申请日：2011-05-27
申请人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/336 , H01L29/66
CPC分类号： H01L29/4236 , H01L21/28114 , H01L21/76224 , H01L29/42376 , H01L29/4966 , H01L29/66553
摘要： A slit recess channel gate is further provided. The slit recess channel gate includes a substrate, a gate dielectric layer, a first conductive layer and a second conductive layer. The substrate has a first trench. The gate dielectric layer is disposed on a surface of the first trench and the first conductive layer is embedded in the first trench. The second conductive layer is disposed on the first conductive layer and aligned with the first conductive layer above the main surface, wherein a bottom surface area of the second conductive layer is substantially smaller than a top surface area of the second conductive layer. The present invention also provides a method of forming the slit recess channel gate.
摘要翻译：还设置狭缝凹槽通道门。狭缝凹槽通道门包括衬底，栅介质层，第一导电层和第二导电层。衬底具有第一沟槽。栅介质层设置在第一沟槽的表面上，第一导电层嵌入第一沟槽中。第二导电层设置在第一导电层上并与主表面上的第一导电层对准，其中第二导电层的底表面积基本上小于第二导电层的顶表面积。本发明还提供了形成狭缝凹槽通道浇口的方法。

66. 发明授权

US08525262B2 Transistor with buried fins 有权
标题翻译：晶体管埋地鳍
公开(公告)号：US08525262B2
公开(公告)日：2013-09-03
申请号：US13081509
申请日：2011-04-07
申请人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tieh-Chiang Wu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L27/12
CPC分类号： H01L27/10879 , H01L27/10826 , H01L29/1037 , H01L29/4236 , H01L29/42376 , H01L29/78
摘要： The present invention disclosed a recessed gate transistor with buried fins. The recessed gate transistor with buried fins is disposed in an active region on a semiconductor substrate. Two isolation regions disposed in the semiconductor substrate, and sandwich the active region. A gate structure is disposed in the semiconductor substrate, wherein the gate structure includes: an upper part and a lower part. The upper part is disposed in the active region and a lower part having a front fin disposed in one of the two isolation regions, at least one middle fin disposed in the active region, and a last fin disposed in the other one of the two isolation regions, wherein the front fin are both elliptic cylindrical.
摘要翻译：本发明公开了一种具有埋地鳍片的凹陷式栅极晶体管。具有埋入散热片的嵌入式栅极晶体管设置在半导体衬底上的有源区中。两个隔离区域设置在半导体衬底中并夹持有源区。栅极结构设置在半导体衬底中，其中栅极结构包括：上部和下部。上部设置在有源区域中，下部具有设置在两个隔离区域之一中的前翅片，设置在有源区域中的至少一个中间翅片，以及设置在两个隔离物中的另一个中的最后一个翅片区域，其中前鳍都是椭圆柱形。

67. 发明授权

US08486834B2 Method for manufacturing memory device 有权
标题翻译：制造存储器件的方法
公开(公告)号：US08486834B2
公开(公告)日：2013-07-16
申请号：US13115039
申请日：2011-05-24
申请人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/768
CPC分类号： H01L27/10873 , H01L21/76834 , H01L21/7684 , H01L23/485 , H01L27/10888 , H01L2924/0002 , H01L2924/00
摘要： The disclosure provides a method for manufacturing a memory device, including: providing a plurality of gate structures formed on a substrate, wherein the gate structures comprise a cap layer disposed on the top of the gate structure, and each two adjacent gate structures are separated by a gap; blanketly forming a polysilicon layer on the substrate to fill the gap; performing a planarization process to the polysilicon layer, obtaining a polysilicon plug; and performing an oxidation process after the planarization process, converting a part of the polysilicon plug and a residual polysilicon layer over the gate structure to silicon oxide.
摘要翻译：本公开提供了一种用于制造存储器件的方法，包括：提供形成在衬底上的多个栅极结构，其中栅极结构包括设置在栅极结构的顶部上的覆盖层，并且每个两个相邻的栅极结构由一个沟; 在基底上覆盖地形成多晶硅层以填补间隙; 对多晶硅层进行平坦化处理，获得多晶硅插塞; 并且在平坦化处理之后进行氧化处理，将多晶硅插塞的一部分和栅极结构上的剩余多晶硅层转换成氧化硅。

68. 发明授权

US08470515B2 Method of forming an etch mask 有权
标题翻译：形成蚀刻掩模的方法
公开(公告)号：US08470515B2
公开(公告)日：2013-06-25
申请号：US13233039
申请日：2011-09-15
申请人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
发明人： Tse-Yao Huang , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： G03C5/00
CPC分类号： G03F7/094 , G03F7/095 , G03F7/32 , G03F7/38 , H01L21/0275 , H01L21/0277 , H01L21/32139
摘要： A method of forming an etch mask includes: providing a substrate having thereon a material layer to be etched; forming a hard mask layer consisting of a radiation-sensitive, single-layer resist material on the material layer; exposing the hard mask layer to actinic energy to change solvent solubility of exposed regions of the hard mask layer; and subjecting the hard mask layer to water treatment to remove the exposed regions of the hard mask layer, thereby forming a masking pattern consisting of unexposed regions of the hard mask layer.
摘要翻译：形成蚀刻掩模的方法包括：提供其上具有要蚀刻的材料层的基板; 在材料层上形成由辐射敏感的单层抗蚀剂材料组成的硬掩模层; 将硬掩模层暴露于光化能以改变硬掩模层的暴露区域的溶剂溶解度; 并对硬掩模层进行水处理以除去硬掩模层的暴露区域，从而形成由硬掩模层的未曝光区域构成的掩模图案。

69. 发明授权

US08410535B2 Capacitor and manufacturing method thereof 有权
标题翻译：电容器及其制造方法
公开(公告)号：US08410535B2
公开(公告)日：2013-04-02
申请号：US13093840
申请日：2011-04-25
申请人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
发明人： Kuo-Hui Su , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L27/108 , H01L29/76 , H01L21/8242
CPC分类号： H01L28/75
摘要： A capacitor and a manufacturing method thereof are provided. The capacitor includes a first electrode, a first metal layer, a dielectric layer and a second electrode. The first electrode is disposed on a substrate. The first metal layer is disposed on the first electrode. The dielectric layer is disposed on the first metal layer, wherein the material of the first metal layer does not react with the material of the dielectric layer. The second electrode is disposed on the dielectric layer.
摘要翻译：提供电容器及其制造方法。电容器包括第一电极，第一金属层，电介质层和第二电极。第一电极设置在基板上。第一金属层设置在第一电极上。电介质层设置在第一金属层上，其中第一金属层的材料不与电介质层的材料反应。第二电极设置在电介质层上。

70. 发明授权

US08399321B2 Method for manufacturing memory device 有权
标题翻译：制造存储器件的方法
公开(公告)号：US08399321B2
公开(公告)日：2013-03-19
申请号：US13111745
申请日：2011-05-19
申请人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
发明人： Ping Hsu , Yi-Nan Chen , Hsien-Wen Liu
IPC分类号： H01L21/8242 , H01L21/336 , H01L21/425
CPC分类号： H01L27/10867 , H01L21/26586 , H01L27/10873 , H01L29/1083 , H01L29/66659
摘要： The method for manufacturing a memory device is provided. The method includes: implanting a first impurity into the substrate adjacent to the gate conductor structure to form a source region on a first side of the gate conductor structure and a drain region on a second side of the gate conductor structure; implanting a second impurity into the substrate to form a halo implantation region disposed adjacent to the source region, wherein the halo implantation region has a doping concentration which does not degrade a data retention time of the memory device; and performing an annealing process to the drain region, forming a diffusion region under the drain region, wherein the process temperature of the annealing process is controlled to ensure that the diffusion region has a doping concentration substantially equal to a threshold concentration which maintains an electrical connection between the drain and the deep trench capacitor.
摘要翻译：提供了一种用于制造存储器件的方法。该方法包括：将第一杂质注入到与栅极导体结构相邻的衬底中，以在栅极导体结构的第一侧上形成源极区，在栅极导体结构的第二侧上形成漏极区; 将第二杂质注入到所述衬底中以形成邻近所述源极区设置的卤素注入区，其中所述晕圈注入区具有不降解所述存储器件的数据保留时间的掺杂浓度; 对所述漏极区进行退火处理，在所述漏极区域下方形成扩散区域，其中，控制所述退火处理的工艺温度，以确保所述扩散区域的掺杂浓度基本上等于保持电连接的阈值浓度在漏极和深沟槽电容器之间。

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