专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明申请

US20070250668A1 DATA PROCESSING SYSTEM, PROCESSOR AND METHOD OF DATA PROCESSING THAT SUPPORT MEMORY ACCESS ACCORDING TO DIVERSE MEMORY MODELS 失效
标题翻译：数据处理系统，处理器和数据处理方法，支持根据多个存储器模型的存储器访问
公开(公告)号：US20070250668A1
公开(公告)日：2007-10-25
申请号：US11380018
申请日：2006-04-25
申请人： Ravi Arimilli , Thomas Capasso , Guy Guthrie , Hugh Shen , William Starke
发明人： Ravi Arimilli , Thomas Capasso , Guy Guthrie , Hugh Shen , William Starke
IPC分类号： G06F13/00
CPC分类号： G06F13/1631 , G06F12/0811 , G06F12/0815 , G06F12/0846 , G06F12/0888
摘要： A data processing system includes a memory subsystem and an execution unit, coupled to the memory subsystem, which executes store instructions to determine target memory addresses of store operations to be performed by the memory subsystem. The data processing system further includes a mode field having a first setting indicating strong ordering between store operations and a second setting indicating weak ordering between store operations. Store operations accessing the memory subsystem are associated with either the first setting or the second setting. The data processing system also includes logic that, based upon settings of the mode field, inserts a synchronizing operation between a store operation associated with the first setting and a store operation associated with the second setting, such that all store operations preceding the synchronizing operation complete before store operations subsequent to the synchronizing operation.
摘要翻译：数据处理系统包括存储器子系统和执行单元，其耦合到存储器子系统，其执行存储指令以确定要由存储器子系统执行的存储操作的目标存储器地址。数据处理系统还包括具有指示存储操作之间的强顺序的第一设置的模式字段和指示存储操作之间的弱顺序的第二设置。访问内存子系统的存储操作与第一个设置或第二个设置相关联。数据处理系统还包括基于模式字段的设置的逻辑，在与第一设置相关联的存储操作与与第二设置相关联的存储操作之间插入同步操作，使得同步操作之前的所有存储操作完成在同步操作之后的存储操作之前。

62. 发明申请

US20070204110A1 Data processing system, cache system and method for reducing imprecise invalid coherency states 失效
标题翻译：数据处理系统，缓存系统和减少不精确无效一致性状态的方法
公开(公告)号：US20070204110A1
公开(公告)日：2007-08-30
申请号：US11364774
申请日：2006-02-28
申请人： Guy Guthrie , William Starke , Derek Williams
发明人： Guy Guthrie , William Starke , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains. In a first cache memory within the first coherency domain of the data processing system, a coherency state field associated with a storage location and an address tag is set to a first data-invalid coherency state that indicates that the address tag is valid and that the storage location does not contain valid data. In response to snooping a data-invalid state update request, the first cache memory updates the coherency state field from the first data-invalid coherency state to a second data-invalid coherency state that indicates that the address tag is valid, that the storage location does not contain valid data, and that a memory block associated with the address tag is likely cached within the first coherency domain.
摘要翻译：缓存相干数据处理系统至少包括第一和第二相干域。在数据处理系统的第一相关域内的第一高速缓冲存储器中，将与存储位置和地址标签相关联的一致性状态字段设置为指示地址标签有效的第一数据无效一致性状态，存储位置不包含有效数据。响应于窥探数据无效状态更新请求，第一缓存存储器将相关性状态字段从第一数据无效一致性状态更新为指示地址标签有效的第二数据无效一致性状态，存储位置不包含有效数据，并且与地址标签相关联的存储器块可能被缓存在第一个相干域内。

63. 发明申请

US20070180196A1 Data processing system, cache system and method for handling a flush operation in a data processing system having multiple coherency domains 失效
标题翻译：数据处理系统，缓存系统和用于处理具有多个相干域的数据处理系统中的刷新操作的方法
公开(公告)号：US20070180196A1
公开(公告)日：2007-08-02
申请号：US11342951
申请日：2006-01-30
申请人： Guy Guthrie , John Hollaway , William Starke , Derek Williams
发明人： Guy Guthrie , John Hollaway , William Starke , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0822 , G06F12/0804 , G06F12/0831
摘要： A cache coherent data processing system includes at least first and second coherency domains. The first coherency domain contains a memory controller, an associated system memory having a target memory block identified by a target address, and a domain indicator indicating whether the target memory block is cached outside the first coherency domain. During operation, the first coherency domain receives a flush operation broadcast to the first and second coherency domains, where the flush operation specifies the target address of the target memory block. The first coherency domain also receives a combined response for the flush operation representing a system-wide response to the flush operation. In response to receipt in the first coherency domain of the combined response, a determination is made if the combined response indicates that a cached copy of the target memory block may remain within the data processing system. In response to a determination that the combined response indicates that a cached copy of the target memory block may remain in the data processing system, the domain indicator is updated to indicate that the target memory block is cached outside of the first coherency domain.
摘要翻译：缓存相干数据处理系统至少包括第一和第二相干域。第一相干域包括存储器控制器，具有由目标地址标识的目标存储器块的相关系统存储器，以及指示目标存储器块是否被高速缓存在第一相干域之外的域指示符。在操作期间，第一相干域接收向第一和第二相干域广播的刷新操作，其中刷新操作指定目标存储器块的目标地址。第一个相干域还接收表示对刷新操作的系统范围响应的刷新操作的组合响应。响应于在组合响应的第一相关域中的接收，确定组合响应是否指示目标存储器块的高速缓存副本可能保留在数据处理系统内。响应于组合响应指示目标存储器块的高速缓存副本可能保留在数据处理系统中的确定，更新域指示符以指示目标存储器块被高速缓存在第一相干域之外。

64. 发明申请

US20060187958A1 Data processing system, method and interconnect fabric having a flow governor 有权
标题翻译：具有流量调节器的数据处理系统，方法和互连结构
公开(公告)号：US20060187958A1
公开(公告)日：2006-08-24
申请号：US11055399
申请日：2005-02-10
申请人： Leo Clark , Guy Guthrie , William Starke
发明人： Leo Clark , Guy Guthrie , William Starke
IPC分类号： H04J3/22 , H04J3/16
CPC分类号： H04L47/722 , H04L47/70 , H04L49/109
摘要： A data processing system includes a plurality of local hubs each coupled to a remote hub by a respective one a plurality of point-to-point communication links. Each of the plurality of local hubs queues requests for access to memory blocks for transmission on a respective one of the point-to-point communication links to a shared resource in the remote hub. Each of the plurality of local hubs transmits requests to the remote hub utilizing only a fractional portion of a bandwidth of its respective point-to-point communication link. The fractional portion that is utilized is determined by an allocation policy based at least in part upon a number of the plurality of local hubs and a number of processing units represented by each of the plurality of local hubs. The allocation policy prevents overruns of the shared resource.
摘要翻译：数据处理系统包括多个本地集线器，每个集线器通过相应的一个多个点对点通信链路耦合到远程集线器。多个本地集线器中的每一个排队对存储器块进行访问的请求，用于在到远程集线器中的共享资源的点对点通信链路中的相应一个上传输。多个本地集线器中的每一个仅利用其相应点对点通信链路的带宽的小数部分向远程集线器发送请求。所使用的分数部分由至少部分地基于多个本地集线器的数量和由多个本地集线器中的每一个表示的多个处理单元的分配策略确定。分配策略可以防止超出共享资源。

65. 发明申请

US20060179223A1 L2 cache array topology for large cache with different latency domains 有权
标题翻译：具有不同延迟域的大型缓存的L2缓存阵列拓扑
公开(公告)号：US20060179223A1
公开(公告)日：2006-08-10
申请号：US11054930
申请日：2005-02-10
申请人： Leo Clark , Guy Guthrie , Kirk Livingston , William Starke
发明人： Leo Clark , Guy Guthrie , Kirk Livingston , William Starke
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0822 , G06F12/0824
摘要： A cache memory logically associates a cache line with at least two cache sectors of a cache array wherein different sectors have different output latencies and, for a load hit, selectively enables the cache sectors based on their latency to output the cache line over successive clock cycles. Larger wires having a higher transmission speed are preferably used to output the cache line corresponding to the requested memory block. In the illustrative embodiment the cache is arranged with rows and columns of the cache sectors, and a given cache line is spread across sectors in different columns, with at least one portion of the given cache line being located in a first column having a first latency, and another portion of the given cache line being located in a second column having a second latency greater than the first latency. One set of wires oriented along a horizontal direction may be used to output the cache line, while another set of wires oriented along a vertical direction may be used for maintenance of the cache sectors. A given cache line is further preferably spread across sectors in different rows or cache ways. For example, a cache line can be 128 bytes and spread across four sectors in four different columns, each sector containing 32 bytes of the cache line, and the cache line is output over four successive clock cycles with one sector being transmitted during each of the four cycles.
摘要翻译：缓存存储器逻辑地将高速缓存行与高速缓存阵列的至少两个缓存扇区相关联，其中不同扇区具有不同的输出延迟，并且对于负载命中，基于它们的等待时间来选择性地启用高速缓存扇区以在连续的时钟周期上输出高速缓存行。优选使用具有较高传输速度的较大导线来输出与所请求的存储块相对应的高速缓存行。在说明性实施例中，高速缓存器配置有高速缓存扇区的行和列，并且给定的高速缓存行分布在不同列中的扇区之间，其中给定高速缓存行的至少一部分位于具有第一等待时间的第一列中并且所述给定高速缓存行的另一部分位于具有大于所述第一等待时间的第二等待时间的第二列中。可以使用沿水平方向定向的一组线来输出高速缓存线，而沿着垂直方向定向的另一组线可以用于高速缓存扇区的维护。给定的高速缓存行进一步优选地分布在不同行或高速缓存方式的扇区之间。例如，高速缓存行可以是128字节并且分布在四个不同列中的四个扇区上，每个扇区包含32个字节的高速缓存行，并且高速缓存行在四个连续的时钟周期内被输出，在每个四个周期。

66. 发明申请

US20060085605A1 Processor, data processing system and method for synchronzing access to data in shared memory 失效
标题翻译：处理器，数据处理系统和方法，用于同步共享存储器中数据的访问
公开(公告)号：US20060085605A1
公开(公告)日：2006-04-20
申请号：US10965151
申请日：2004-10-14
申请人： Guy Guthrie , Sheldon Levenstein , William Starke , Derek Williams
发明人： Guy Guthrie , Sheldon Levenstein , William Starke , Derek Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0875 , G06F9/3004 , G06F9/30072 , G06F9/30087 , G06F9/383 , G06F9/3834 , G06F9/3851
摘要： A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit. The instruction execution unit, responsive to receipt of a load-reserve instruction from the instruction sequencing unit, executes the load-reserve instruction to determine a load target address. The processor core, responsive to the execution of the load-reserve instruction, performs a corresponding load-reserve operation by accessing the store-through upper level cache utilizing the load target address to cause data associated with the load target address to be loaded from the store-through upper level cache into the data register and by establishing a reservation for a reservation granule including the load target address.
摘要翻译：一种用于多处理器数据处理系统的处理单元，包括：处理器核心，包括存储器上级缓存器，指令执行指令排序单元，数据寄存器和至少一个指令执行单元。指令执行单元响应于从指令排序单元接收到加载保留指令，执行加载保留指令以确定加载目标地址。处理器核心响应于负载预留指令的执行，通过使用负载目标地址访问存储上级高速缓存来执行相应的加载备份操作，以使与加载目标地址相关联的数据从通过上层缓存到数据寄存器中，并通过建立包括加载目标地址的预留颗粒的预留。

67. 发明授权

US5388223A 1-bit token ring arbitration architecture 失效
标题翻译： 1位令牌环仲裁架构
公开(公告)号：US5388223A
公开(公告)日：1995-02-07
申请号：US755474
申请日：1991-09-05
申请人： Guy Guthrie , Jeffery L. Swarts
发明人： Guy Guthrie , Jeffery L. Swarts
IPC分类号： G06F13/37 , H04L12/433 , G06F13/36
CPC分类号： G06F13/37 , H04L12/433
摘要： A 1-bit token ring arbitration architecture where a plurality of chips which require access to a shared bus are coupled together in a ring is described. Each chip receives an arbitration in signal from the preceding member of the ring which is used to receive the token. Each chip transmits an arbitration out signal to the following member of the ring to send the token to the following member. In the preferred embodiment, the token appears as a 1 cycle active low pulse. An error signal notifies all the bus participants that a ring error has been detected. Preferably, the number of cycles the error signal is held active, the more severe the error. A request of bus (ROB) signal notifies the chip holding the token that another bus member needs to use the bus. The ROB signal allows the current holder of the token to maintain control of the bus if it has further processing on the bus as long as no other bus member needs the bus. A Token Hold Timer may be included in a ring member which defines how long the member can hold on to the token after receiving notification on the ROB line that another bus participant wants the bus.
摘要翻译：描述了需要访问共享总线的多个芯片以环形耦合在一起的1位令牌环仲裁架构。每个芯片从用于接收令牌的环的前一成员的信号中接收仲裁。每个芯片向环的下一个成员发送仲裁输出信号，以将令牌发送到下一个成员。在优选实施例中，令牌显示为1个周期的有效低电平脉冲。错误信号通知所有总线参与者已检测到环路错误。优选地，误差信号保持有效的周期数，误差越严重。总线（ROB）信号的请求通知保存令牌的芯片，另一个总线成员需要使用总线。只要没有其他总线构件需要总线，ROB信号允许令牌的当前持有者在总线上进行进一步的处理来维持总线的控制。令牌保持定时器可以包括在环成员中，该环成员定义了在ROB线上接收到另一个总线参与者想要总线的通知之后，成员可以持续多长时间。

68. 发明申请

US20080098177A1 Data Processing System and Method for Efficient L3 Cache Directory Management 有权
标题翻译：数据处理系统和高效L3缓存目录管理方法
公开(公告)号：US20080098177A1
公开(公告)日：2008-04-24
申请号：US11956112
申请日：2007-12-13
申请人： Guy Guthrie , William Starke , Derek Williams , Philip Williams
发明人： Guy Guthrie , William Starke , Derek Williams , Philip Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/128 , G06F2212/2542
摘要： A system and method for cache management in a data processing system having a memory hierarchy of upper memory and lower memory cache. A lower memory cache controller accesses a coherency state table to determine replacement policies of coherency states for cache lines present in the lower memory cache when receiving a cast-in request from one of the upper memory caches. The coherency state table implements a replacement policy that retains the more valuable cache coherency state information between the upper and lower memory caches for a particular cache line contained in both levels of memory at the time of cast-out from the upper memory cache.
摘要翻译：一种用于在具有上部存储器和下部存储器高速缓存的存储器层级的数据处理系统中的高速缓存管理的系统和方法。较低的存储器高速缓存控制器访问一致性状态表以确定当从上部存储器高速缓存中的一个接收到转入请求时存在于下部存储器高速缓存中的高速缓存行的一致性状态的替换策略。一致性状态表实现替换策略，其在从上部存储器高速缓存中拔出时，在包含在两个级别的存储器中的特定高速缓存行的上下存储器高速缓存之间保留更有价值的高速缓存一致性状态信息。

69. 发明申请

US20080077740A1 L2 CACHE ARRAY TOPOLOGY FOR LARGE CACHE WITH DIFFERENT LATENCY DOMAINS 有权
标题翻译： L2缓存高速缓存的区别于不同的域名
公开(公告)号：US20080077740A1
公开(公告)日：2008-03-27
申请号：US11947742
申请日：2007-11-29
申请人： Leo Clark , Guy Guthrie , Kirk Livingston , William Starke
发明人： Leo Clark , Guy Guthrie , Kirk Livingston , William Starke
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0822 , G06F12/0824
摘要： A cache memory logically associates a cache line with at least two cache sectors of a cache array wherein different sectors have different output latencies and, for a load hit, selectively enables the cache sectors based on their latency to output the cache line over successive clock cycles. Larger wires having a higher transmission speed are preferably used to output the cache line corresponding to the requested memory block. In the illustrative embodiment the cache is arranged with rows and columns of the cache sectors, and a given cache line is spread across sectors in different columns, with at least one portion of the given cache line being located in a first column having a first latency, and another portion of the given cache line being located in a second column having a second latency greater than the first latency. One set of wires oriented along a horizontal direction may be used to output the cache line, while another set of wires oriented along a vertical direction may be used for maintenance of the cache sectors. A given cache line is further preferably spread across sectors in different rows or cache ways. For example, a cache line can be 128 bytes and spread across four sectors in four different columns, each sector containing 32 bytes of the cache line, and the cache line is output over four successive clock cycles with one sector being transmitted during each of the four cycles.
摘要翻译：缓存存储器逻辑地将高速缓存行与高速缓存阵列的至少两个缓存扇区相关联，其中不同扇区具有不同的输出延迟，并且对于负载命中，基于它们的等待时间来选择性地启用高速缓存扇区以在连续的时钟周期上输出高速缓存行。优选使用具有较高传输速度的较大导线来输出与所请求的存储块相对应的高速缓存行。在说明性实施例中，高速缓存器配置有高速缓存扇区的行和列，并且给定的高速缓存行分布在不同列中的扇区之间，其中给定高速缓存行的至少一部分位于具有第一等待时间的第一列中并且所述给定高速缓存行的另一部分位于具有大于所述第一等待时间的第二等待时间的第二列中。可以使用沿水平方向定向的一组线来输出高速缓存线，而沿着垂直方向定向的另一组线可以用于高速缓存扇区的维护。给定的高速缓存行进一步优选地分布在不同行或高速缓存方式的扇区之间。例如，高速缓存行可以是128字节并且分布在四个不同列中的四个扇区上，每个扇区包含32个字节的高速缓存行，并且高速缓存行在四个连续的时钟周期内被输出，在每个四个周期。

70. 发明申请

US20070226423A1 Processor, data processing system, and method for initializing a memory block in a data processing system having multiple coherency domains 有权
标题翻译：处理器，数据处理系统和用于初始化具有多个相干域的数据处理系统中的存储器块的方法
公开(公告)号：US20070226423A1
公开(公告)日：2007-09-27
申请号：US11388001
申请日：2006-03-23
申请人： Ravi Arimilli , Guy Guthrie , William Starke , Derek Williams
发明人： Ravi Arimilli , Guy Guthrie , William Starke , Derek Williams
IPC分类号： G06F13/28
CPC分类号： G06F12/0822 , G06F12/084
摘要： A data processing system includes at least first and second coherency domains, each including at least one processor core and a memory. In response to an initialization operation by a processor core that indicates a target memory block to be initialized, a cache memory in the first coherency domain determines a coherency state of the target memory block with respect to the cache memory. In response to the determination, the cache memory selects a scope of broadcast of an initialization request identifying the target memory block. A narrower scope including the first coherency domain and excluding the second coherency domain is selected in response to a determination of a first coherency state, and a broader scope including the first coherency domain and the second coherency domain is selected in response to a determination of a second coherency state. The cache memory then broadcasts an initialization request with the selected scope. In response to the initialization request, the target memory block is initialized within a memory of the data processing system to an initialization value.
摘要翻译：数据处理系统至少包括第一和第二相干域，每个域包括至少一个处理器核和存储器。响应于指示要初始化的目标存储器块的处理器核心的初始化操作，第一相干域中的高速缓存存储器确定目标存储器块相对于高速缓冲存储器的一致性状态。响应于该确定，高速缓存存储器选择识别目标存储器块的初始化请求的广播范围。响应于第一相关性状态的确定而选择包括第一相关域并且排除第二相关性域的较窄范围，并且响应于确定第一相关性域的第一相关性域和第二相关域第二一致性状态。然后，高速缓冲存储器播放具有所选范围的初始化请求。响应于初始化请求，将目标存储器块在数据处理系统的存储器内初始化为初始化值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式