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61. 发明申请

WO2013095515A1 PACKED DATA OPERATION MASK REGISTER ARITHMETIC COMBINATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开
标题翻译：包装数据操作面板寄存器算术组合处理器，方法，系统和指令
公开(公告)号：WO2013095515A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066875
申请日：2011-12-22
申请人： INTEL CORPORATION , TOLL, Bret L. , VALENTINE, Robert , SAN ADRIAN, Jesus Corbal , OULD-AHMED-VALL, Elmoustapha , CHARNEY, Mark J.
发明人： TOLL, Bret L. , VALENTINE, Robert , SAN ADRIAN, Jesus Corbal , OULD-AHMED-VALL, Elmoustapha , CHARNEY, Mark J.
IPC分类号： G06F9/06 , G06F9/30
CPC分类号： G06F9/3001 , G06F9/30014 , G06F9/30018 , G06F9/30036
摘要： A method of an aspect includes receiving a packed data operation mask register arithmetic combination instruction. The packed data operation mask register arithmetic combination instruction indicates a first packed data operation mask register, indicates a second packed data operation mask register, and indicates a destination storage location. An arithmetic combination of at least a portion of bits of the first packed data operation mask register and at least a corresponding portion of bits of the second packed data operation mask register is stored in the destination storage location in response to the packed data operation mask register arithmetic combination instruction. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译：一种方面的方法包括接收压缩数据操作屏蔽寄存器算术组合指令。打包数据操作屏蔽寄存器算术组合指令指示第一打包数据操作屏蔽寄存器，指示第二打包数据操作屏蔽寄存器，并指示目的地存储位置。响应于打包数据操作屏蔽寄存器，将第一打包数据操作屏蔽寄存器的位的至少一部分与第二打包数据操作屏蔽寄存器的位的至少相应部分的算术组合存储在目的地存储位置中算术组合指令。公开了其它方法，装置，系统和指令。

62. 发明申请

WO2013095510A1 PACKED DATA OPERATION MASK CONCATENATION PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS 审中-公开
标题翻译：包装数据操作掩模处理器，方法，系统和指令
公开(公告)号：WO2013095510A1
公开(公告)日：2013-06-27
申请号：PCT/US2011/066849
申请日：2011-12-22
申请人： INTEL CORPORATION , TOLL, Bret L. , VALENTINE, Robert , SAN ADRIAN, Jesus Corbal , OULD-AHMED-VALL, Elmoustapha , CHARNEY, Mark J.
发明人： TOLL, Bret L. , VALENTINE, Robert , SAN ADRIAN, Jesus Corbal , OULD-AHMED-VALL, Elmoustapha , CHARNEY, Mark J.
IPC分类号： G06F9/30 , G06F13/14
CPC分类号： G06F9/3017 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/3013 , G06F13/14
摘要： A method of an aspect includes receiving a packed data operation mask concatenation instruction. The packed data operation mask concatenation instruction indicates a first source having a first packed data operation mask, indicates a second source having a second packed data operation mask, and indicates a destination. A result is stored in the destination in response to the packed data operation mask concatenation instruction. The result includes the first packed data operation mask concatenated with the second packed data operation mask. Other methods, apparatus, systems, and instructions are disclosed.
摘要翻译：一种方面的方法包括接收压缩数据操作掩码级联指令。打包数据操作掩码级联指示指示具有第一打包数据操作掩码的第一源，指示具有第二打包数据操作掩码的第二源，并指示目的地。响应于打包数据操作掩码连接指令，结果存储在目的地中。结果包括与第二打包数据操作掩码相连接的第一打包数据操作掩码。公开了其它方法，装置，系统和指令。

63. 发明申请

WO2020190813A1 SYSTEM AND METHODS TO PROVIDE HIERARCHICAL OPEN SECTORING AND VARIABLE SECTOR SIZE FOR CACHE OPERATIONS 审中-公开
公开(公告)号：WO2020190813A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/022851
申请日：2020-03-14
申请人： INTEL CORPORATION
发明人： APPU, Abhishek , STRIRAMASSARMA, Lakshminarayanan , KOKER, Altug , COLEMAN, Sean , GEORGE, Varghese , HUNTER, JR., Arthur , INSKO, Brent , JANUS, Scott , OULD-AHMED-VALL, Elmoustapha , RANGANATHAN, Vasanth , RAY, Joydeep , SINHA, Kamal , SURTI, Prasoonkumar , VAIDYANATHAN, Karthik
IPC分类号： G06F12/12 , G06F12/128 , G06F12/0886 , G06F12/0862 , G06F9/38
摘要： Graphics processors of the present design provide hierarchical open sectors and variable cache sizes for cache operations. In one embodiment, a graphics processor comprises a cache memory having a hierarchical open sector design including a first hierarchy of upper and lower regions with each region including a second hierarchy of sectors. A cache controller is configured to initially open a first sector of the lower region, to receive a memory request that does not match an address in the first sector, and to open a second sector of the lower region.

64. 发明申请

WO2020190807A1 SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE 审中-公开
公开(公告)号：WO2020190807A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/022845
申请日：2020-03-14
申请人： INTEL CORPORATION
发明人： SURTI, Prasoonkumar , MAIYURAN, Subramaniam , ANDREI, Valentin , APPU, Abhishek , GEORGE, Varghese , KOKER, Altug , MACPHERSON, Mike , OULD-AHMED-VALL, Elmoustapha , RANGANATHAN, Vasanth , RAY, Joydeep , STRIRAMASSARMA, Lakshminarayanan , KIM, SungYe
IPC分类号： G06F9/30
摘要： Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides techniques to optimize training and inference on a systolic array when using sparse data. One embodiment provides techniques to use decompression information when performing sparse compute operations. One embodiment enables the disaggregation of special function compute arrays via a shared reg file. One embodiment enables packed data compress and expand operations on a GPGPU. One embodiment provides techniques to exploit block sparsity within the cache hierarchy of a GPGPU.

65. 发明申请

WO2020190797A1 SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU CONFIGURATION 审中-公开
公开(公告)号：WO2020190797A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/022835
申请日：2020-03-14
申请人： INTEL CORPORATION
发明人： KOKER, Altug , RAY, Joydeep , ANANTARAMAN, Aravindh , ANDREI, Valentin , APPU, Abhishek , COLEMAN, Sean , GALOPPO VON BORRIES, Nicolas , GEORGE, Varghese , K, Pattabhiraman , KIM, SungYe , MACPHERSON, Mike , MAIYURAN, Subramaniam , OULD-AHMED-VALL, Elmoustapha , RANGANATHAN, Vasanth , VALERIO, James
IPC分类号： G06F12/0811 , G06F12/0875
摘要： Systems and methods for updating remote memory side caches in a multi-GPU configuration are disclosed herein. A graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) (2810) having a first memory (2870-1), a first memory side cache memory (2880-1), a first communication fabric (2860-1), and a first memory management unit (MMU) (2855-1). The graphics processor includes a second GPU (2820) having a second memory (2870-2), a second memory side cache memory (2880-2), a second MMU (2855-2), and a second communication fabric (2860-2) that is communicatively coupled to the first communication fabric. The first MMU is configured to control memory requests for the first memory, to update content in the first memory, to update content in the first memory side cache memory, and to determine whether to update the content in the second memory side cache memory.

66. 发明申请

WO2020190796A1 SYSTEMS AND METHODS FOR CACHE OPTIMIZATION 审中-公开
公开(公告)号：WO2020190796A1
公开(公告)日：2020-09-24
申请号：PCT/US2020/022833
申请日：2020-03-14
申请人： INTEL CORPORATION
发明人： KOKER, Altug , RAY, Joydeep , OULD-AHMED-VALL, Elmoustapha , APPU, Abhishek , ANANTARAMAN, Aravindh , ANDREI, Valentin , BILAGI, Durgaprasad , GEORGE, Varghese , INSKO, Brent , JAHAGIRDAR, Sanjeev , JANUS, Scott , K, Pattabhiraman , KIM, SungYe , MAIYURAN, Subramaniam , RANGANATHAN, Vasanth , STRIRAMASSARMA, Lakshminarayanan , TIAN, Xinmin
IPC分类号： G06F9/38 , G06F12/0862 , G06F9/30 , G06F12/123 , G06F12/126
摘要： Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received.

67. 发明申请

WO2019005130A1 APPARATUS AND METHOD FOR MULTIPLICATION AND ACCUMULATION OF COMPLEX VALUES 审中-公开
公开(公告)号：WO2019005130A1
公开(公告)日：2019-01-03
申请号：PCT/US2017/040408
申请日：2017-06-30
申请人： INTEL CORPORATION
发明人： OULD-AHMED-VALL, Elmoustapha , MADDURI, Venkateswara R.
IPC分类号： G06F9/30 , G06F7/48
摘要： An apparatus and method for accumulating complex numbers. For example, one embodiment of a processor comprises: a first source register to store a first plurality of real and imaginary components of a first set of complex numbers; a second source register to store a second plurality of real and imaginary components of a second set of complex numbers; wherein the real and imaginary components of the first and second plurality of are to be stored as packed data elements within the first and second source registers; and execution circuitry comprising: multiplier circuitry to multiply selected real and imaginary values from the first source register with selected real and imaginary values from the second source register to generate a first plurality of values, adder circuitry to add and subtract selected combinations of the first plurality of values to generate a second plurality of values, and accumulation circuitry to combine the second plurality of values with a third set of complex numbers stored in a destination register to generate an accumulated result, the accumulated result to be written to the destination register.

68. 发明申请

WO2018174930A1 SYSTEMS, METHODS, AND APPARATUSES FOR MATRIX ADD, SUBTRACT, AND MULTIPLY 审中-公开
公开(公告)号：WO2018174930A1
公开(公告)日：2018-09-27
申请号：PCT/US2017/040540
申请日：2017-07-01
申请人： INTEL CORPORATION
发明人： VALENTINE, Robert , BAUM, Dan , SPERBER, Zeev , CORBAL, Jesus , OULD-AHMED-VALL, Elmoustapha , TOLL, Bret L. , CHARNEY, Mark J. , ZIV, Barukh , HEINECKE, Alexander , GIRKAR, Milind , RUBANOVICH, Simon
IPC分类号： G06F9/30
摘要： Embodiments detailed herein relate to matrix operations. In particular, support for matrix (tile) addition, subtraction, and multiplication is described. For example, circuitry to support instructions for element-by-element matrix (tile) addition, subtraction, and multiplication are detailed. In some embodiments, for matrix (tile) addition, decode circuitry is to decode an instruction having fields for an opcode, a first source matrix operand identifier, a second source matrix operand identifier, and a destination matrix operand identifier; and execution circuitry is to execute the decoded instruction to, for each data element position of the identified first source matrix operand: add a first data value at that data element position to a second data value at a corresponding data element position of the identified second source matrix operand, and store a result of the addition into a corresponding data element position of the identified destination matrix operand.

69. 发明申请

WO2018174925A1 SYSTEMS, METHODS, AND APPARATUSES FOR DOT PRODUCTION OPERATIONS 审中-公开
公开(公告)号：WO2018174925A1
公开(公告)日：2018-09-27
申请号：PCT/US2017/040534
申请日：2017-07-01
申请人： INTEL CORPORATION
发明人： VALENTINE, Robert , BAUM, Dan , SPERBER, Zeev , CORBAL, Jesus , OULD-AHMED-VALL, Elmoustapha , TOLL, Bret L. , CHARNEY, Mark J. , ADELMAN, Menachem , ZIV, Barukh , HEINECKE, Alexander , RUBANOVICH, Simon
IPC分类号： G06F9/30
摘要： Embodiments detailed herein relate to matrix operations. For example, embodiments of instruction support for matrix (tile) dot product operations are detailed. Exemplary instructions including computing a dot product of signed words and accumulating in a double word with saturation; computing a dot product of bytes and accumulating in to a dword with saturation, where the input bytes can be signed or unsigned and the dword accumulation has output saturation; etc.

70. 发明申请

WO2018063513A1 SYSTEMS AND METHODS FOR EXECUTING A FUSED MULTIPLY-ADD INSTRUCTION FOR COMPLEX NUMBERS 审中-公开
标题翻译：用于执行复合数字的融合乘法指令的系统和方法
公开(公告)号：WO2018063513A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/046036
申请日：2017-08-09
申请人： INTEL CORPORATION
发明人： DUBTSOV, Roman S. , VALENTINE, Robert , CORBAL, Jesus , GIRKAR, Milind , OULD-AHMED-VALL, Elmoustapha
IPC分类号： G06F9/30 , G06F7/48
CPC分类号： G06F9/30036 , G06F9/3001
摘要： Disclosed embodiments relate to executing a vector-complex fused multiply-add Instruction. In one example, a method includes fetching an instruction, a format of the instruction including an opcode, a first source operand identifier, a second source operand identifier, and a destination operand identifier, wherein each of the identifiers is to identify a location storing a packed data comprising at least one complex number, decoding the instruction, retrieving data associated with the first and second source operand identifiers, and executing the decoded instruction to, for each packed data element position of the identified first and second source operands, cross-multiply the real and imaginary components to generate four products: a product of real components, a product of imaginary components, and two mixed products, to generate a complex result by summing the four products according to the instruction, and to store a result to the corresponding position of the identified destination operand.
摘要翻译：所公开的实施例涉及执行向量复数融合乘加指令。在一个示例中，一种方法包括获取指令，包括操作码的指令的格式，第一源操作数标识符，第二源操作数标识符和目的地操作数标识符，其中每个标识符用于标识存储打包所述数据，所述打包数据包括至少一个复数，解码所述指令，检索与所述第一和第二源操作数标识符相关联的数据，以及执行所解码的指令，以针对所识别的第一和第二源操作数的每个打包数据元素位置，生成四种产品的实部和虚部：真实组件的产品，虚拟组件的产品和两种混合产品，通过根据指令对四种产品进行求和来生成一个复杂结果，并将结果存储到相应的确定的目标操作数的位置。

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