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61. 发明申请

WO2018160185A1 FLOATING SHIELD COPLANAR WAVEGUIDE TRANSMISSION LINE STRUCTURES FOR QUBITS 审中-公开
公开(公告)号：WO2018160185A1
公开(公告)日：2018-09-07
申请号：PCT/US2017/020562
申请日：2017-03-03
申请人： INTEL CORPORATION
发明人： ROBERTS, Jeanette M. , PELLERANO, Stefano , YOSCOVITS, Zachary R. , CAUDILLO, Roman , CLARKE, James S. , ELSHERBINI, Adel A. , MICHALAK, David J. , PILLARISETTY, Ravi , GEORGE, Hubert C. , THOMAS, Nicole K. , SINGH, Kanwaljit
IPC分类号： H01P3/00 , H01P3/12 , H01P3/16
CPC分类号： H01P3/006
摘要： Described herein are new transmission line structures for use as resonators and non-resonant transmission lines in quantum circuits. In one aspect of the disclosure, a proposed structure includes a conductive shield structure provided over or in the substrate, a dielectric layer provided over the conductive shield structure, a first and a second ground plane structures provided over the dielectric layer, and a signal line structure provided over the dielectric layer, between the first and second ground plane structures. The conductive shield structure is electrically floating and each of the first and second ground plane structures and the signal line are provided opposite a respective portion of the conductive shield structure. Transmission line structures as proposed herein could be used for providing microwave connectivity to, from, or/and between the qubits, or to control the qubits. Methods for fabricating such structures are disclosed as well.

62. 发明申请

WO2018084878A1 QUANTUM DOT DEVICES 审中-公开
标题翻译：量子点设备
公开(公告)号：WO2018084878A1
公开(公告)日：2018-05-11
申请号：PCT/US2016/068603
申请日：2016-12-24
申请人： INTEL CORPORATION
发明人： CLARKE, James S. , THOMAS, Nicole K. , YOSCOVITS, Zachary R. , GEORGE, Hubert C. , ROBERTS, Jeanette M. , PILLARISETTY, Ravi
IPC分类号： G06N99/00 , B82Y10/00
摘要： Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gates above the quantum well stack; and a plurality of second gates above the quantum well stack; wherein the plurality of first gates are arranged in electrically continuous rows extending in a first direction, and the plurality of second gates are arranged in electrically continuous rows extending in a second direction perpendicular to the first direction.
摘要翻译：本文公开了量子点器件以及相关的系统和方法。在一些实施例中，量子点器件可以包括量子阱堆叠; 量子阱堆叠之上的多个第一栅极; 以及量子阱堆叠之上的多个第二栅极; 其中所述多个第一栅极排列成在第一方向上延伸的电连续行，并且所述多个第二栅极排列成沿垂直于所述第一方向的第二方向延伸的电连续行。

63. 发明申请

WO2018063206A1 ON-CHIP CONTROL LOGIC FOR QUBITS 审中-公开
标题翻译：用于QUBITS的片上控制逻辑
公开(公告)号：WO2018063206A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054296
申请日：2016-09-29
申请人： INTEL CORPORATION
发明人： THOMAS, Nicole K. , PILLARISETTY, Ravi , ROBERTS, Jeanette M. , GEORGE, Hubert C. , CLARKE, James S.
IPC分类号： H01L27/06 , H01L29/775 , H01L29/12 , H01L29/66
CPC分类号： H01L27/0629 , B82Y10/00 , B82Y40/00 , G06N10/00 , H01L21/823412 , H01L27/0617 , H01L27/088 , H01L27/18 , H01L29/127 , H01L29/66 , H01L29/66977 , H01L29/7613 , H01L29/775 , H01L29/778 , H01L39/223 , H01L39/2493
摘要： Described herein are quantum integrated circuit (IC) assemblies that include quantum circuit components comprising a plurality of qubits and control logic coupled to the quantum circuit components and configured to control operation of those components, where the quantum circuit component(s) and the control logic are provided on a single die. By implementing control logic on the same die as the quantum circuit component(s), more functionality can be provided on-chip, thus integrating more of signal chain on-chip. Integration can greatly reduce complexity and lower the cost of quantum computing devices, reduce interfacing bandwidth, and provide an approach that can be efficiently used in large scale manufacturing. Methods for fabricating such assemblies are also disclosed.
摘要翻译：这里描述的是包括量子电路部件的量子集成电路（IC）组件，该量子电路部件包括多个量子位和耦合到量子电路部件并且被配置为控制这些部件的操作的控制逻辑，其中量子电路组件和控制逻辑被提供在单个管芯上。通过在与量子电路组件相同的管芯上实施控制逻辑，可以在芯片上提供更多的功能，从而将更多的信号链集成在芯片上。集成可以大大降低复杂度并降低量子计算设备的成本，减少接口带宽，并提供可以在大规模制造中有效使用的方法。还公开了制造这种组件的方法。

64. 发明申请

WO2018063205A1 ON-CHIP WIRELESS COMMUNICATION DEVICES FOR QUBITS 审中-公开
标题翻译：用于QUBITS的芯片上无线通信设备
公开(公告)号：WO2018063205A1
公开(公告)日：2018-04-05
申请号：PCT/US2016/054295
申请日：2016-09-29
申请人： INTEL CORPORATION
发明人： PILLARISETTY, Ravi , DASGUPTA, Sansaptak , THEN, Han Wui , RADOSAVLJEVIC, Marko , ROBERTS, Jeanette M. , THOMAS, Nicole K. , GEORGE, Hubert C. , CLARKE, James S.
IPC分类号： H01L29/66 , H01L27/02 , H01L29/80
CPC分类号： B82Y10/00 , H01L27/18 , H01L29/0673 , H01L29/127 , H01L29/165 , H01L29/423 , H01L29/42376 , H01L29/66 , H01L29/66977 , H01L29/7613 , H01L29/775 , H01L29/80
摘要： Embodiments of the present disclosure provide quantum integrated circuit assemblies. An exemplary assembly includes a quantum circuit component that includes a plurality of qubits, a control logic coupled to the quantum circuit component and configured to control operation of the component, and a wireless communication device configured to enable the control logic to wirelessly receive and/or transmit data, all provided on a single die. By implementing control logic and the wireless communication device on the same die as the quantum circuit component(s), more functionality can be provided on-chip, enabling wireless control of the qubits. Integration can greatly reduce complexity and lower the cost of quantum computing devices, reduce interfacing bandwidth, and provide an approach that can be efficiently used in large-scale manufacturing. Methods for fabricating such assemblies are also disclosed.
摘要翻译：本公开的实施例提供了量子集成电路组件。示例性组件包括量子电路组件，该量子电路组件包括多个量子位，耦合到量子电路组件的控制逻辑并且被配置为控制组件的操作，以及无线通信设备，被配置为使控制逻辑能够无线接收和/或传输数据，全部在单个芯片上提供。通过在与量子电路组件相同的管芯上实现控制逻辑和无线通信设备，可以在芯片上提供更多的功能，从而实现量子位的无线控制。集成可以大大降低复杂性，降低量子计算设备的成本，减少接口带宽，并提供可以有效用于大规模制造的方法。还公开了制造这种组件的方法。

65. 发明申请

WO2018057024A1 SINTERED SILVER HEAT EXCHANGER FOR QUBITS 审中-公开
标题翻译：用于QUBITS的烧结银热交换器
公开(公告)号：WO2018057024A1
公开(公告)日：2018-03-29
申请号：PCT/US2016/053637
申请日：2016-09-26
申请人： INTEL CORPORATION
发明人： PILLARISETTY, Ravi , GEORGE, Hubert C. , ROBERTS, Jeanette M. , THOMAS, Nicole K. , CLARKE, James S.
IPC分类号： H01L23/49 , H01L23/492 , H01L23/00 , H01L29/12 , H01L29/775
摘要： Described herein are qubit device packages which incorporate portions of electrical connections for supporting transport of charge carriers to/from the qubits. An exemplary package includes a die and a package substrate. The die includes a qubit device and has a first face with a plurality of conductive contacts. An opposing second face of the die is mechanically attached to a first face of the package substrate. The package further includes qubit level interconnects, i.e. conductive pathways provided within the same package as qubits of the qubit device of the die, electrically coupling conductive contacts at the first face of the die with associated conductive contacts at the first face of the package substrate. Providing qubit level interconnects ensures that these interconnects are kept at the same temperature level as the qubits of the die, advantageously allowing cooling of the charge carriers injected into the qubit device.
摘要翻译：这里描述的是量子比特器件封装，其包含电连接的部分用于支持电荷载流子向/从量子位的运输。示例性封装包括管芯和封装衬底。模具包括量子位器件并具有带有多个导电触点的第一面。管芯的相对的第二面机械地附接到封装衬底的第一面。该封装还包括量子比特级互连，即与裸片的量子位器件的量子位在同一封装内提供的导电通路，将裸片第一面上的导电触点与封装衬底第一面上的相关导电触点电耦合。提供量子比特互连确保这些互连保持在与管芯的量子位相同的温度水平，有利地允许冷却注入到量子比特器件中的电荷载流子。

66. 发明申请

WO2018057023A1 QUANTUM DOT QUBITS WITH III-V COMPOUNDS 审中-公开
标题翻译：用III-V族化合物量子点QUBITS
公开(公告)号：WO2018057023A1
公开(公告)日：2018-03-29
申请号：PCT/US2016/053621
申请日：2016-09-25
申请人： INTEL CORPORATION
发明人： PILLARISETTY, Ravi , ROBERTS, Jeanette M. , THOMAS, Nicole K. , GEORGE, Hubert C. , CLARKE, James S.
IPC分类号： H01L29/775 , H01L29/12 , H01L29/15 , H01L29/778 , H01L29/786 , H01L29/66
摘要： Described herein are quantum dot devices, as well as related computing devices and methods of operation thereof. For example, in some embodiments, a quantum dot device may include a base, a fin extending away from the base and including a quantum well layer made from III-V semiconductors, and one or more gates disposed on the fin. Using III-V semiconductors to form a quantum well layer may be advantageous because of stronger confinement of charge carriers in a quantum well and improved charge carrier mobility. Methods for fabricating such devices are also disclosed.
摘要翻译：这里描述的是量子点器件以及相关的计算设备及其操作方法。例如，在一些实施例中，量子点器件可以包括基底，远离基底延伸并包括由III-V族半导体制成的量子阱层的鳍以及设置在鳍上的一个或多个栅极。使用III-V半导体形成量子阱层可能是有利的，因为量子阱中电荷载流子的更强的约束和改善的电荷载流子迁移率。还公开了制造这种装置的方法。

67. 发明申请

WO2018031007A1 QUANTUM DOT ARRAY DEVICES 审中-公开
标题翻译：量子点阵器件
公开(公告)号：WO2018031007A1
公开(公告)日：2018-02-15
申请号：PCT/US2016/046236
申请日：2016-08-10
申请人： INTEL CORPORATION
发明人： CLARKE, James S. , BRISTOL, Robert L. , PILLARISETTY, Ravi , ROBERTS, Jeanette M. , GEORGE, Hubert C. , THOMAS, Nicole K.
IPC分类号： H01L29/66 , H01L29/12 , H01L29/80
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; a plurality of gates disposed above the quantum well stack, wherein at least two of the gates are spaced apart in a first dimension above the quantum well stack, at least two of the gates are spaced apart in a second dimension above the quantum well stack, and the first and second dimensions are perpendicular; and an insulating material disposed above the quantum well stack, wherein the insulating material extends between at least two of the gates spaced apart in the first dimension, and the insulating material extends between at least two of the gates spaced apart in the second dimension.
摘要翻译：这里公开的是量子点器件以及相关的计算设备和方法。例如，在一些实施例中，量子点器件可以包括：包括量子阱层的量子阱堆; 设置在量子阱堆叠上方的多个栅极，其中至少两个栅极在量子阱堆叠上方的第一维度上间隔开，至少两个栅极在量子阱堆叠上方的第二维度间隔开，并且第一和第二尺寸是垂直的; 以及设置在所述量子阱堆叠上方的绝缘材料，其中所述绝缘材料在所述第一维度上间隔开的至少两个所述栅极之间延伸，并且所述绝缘材料在所述第二维度间隔开的至少两个栅极之间延伸。 / p>

68. 发明申请

WO2018004636A1 INTERCONNECTS BELOW QUBIT PLANE BY SUBSTRATE BONDING 审中-公开
标题翻译：通过衬底结合在坠落平面之下进行互连
公开(公告)号：WO2018004636A1
公开(公告)日：2018-01-04
申请号：PCT/US2016/040603
申请日：2016-07-01
申请人： INTEL CORPORATION
发明人： MICHALAK, David J. , PILLARISETTY, Ravi , YOSCOVITS, Zachary R. , ROBERTS, Jeanette M. , CLARKE, James S.
IPC分类号： H01L29/66 , H01L29/12
摘要： Described herein are structures that include interconnects for providing electrical connectivity in superconducting quantum circuits. One structure includes a first and a second interconnects provided over a surface of an interconnect support layer, e.g. a substrate, on which superconducting qubits are provided, a lower interconnect provided below such surface (i.e. below-plane interconnect), and vias for providing electrical interconnection between the lower interconnect and each of the first and second interconnects. Providing below-plane interconnects in superconducting quantum circuits allows realizing superconducting and mechanically stable interconnects. Implementing below-plane interconnects by bonding of two substrates, material for which could be selected, allows minimizing the amount of spurious two-level systems in the areas surrounding below-plane interconnects while allowing different choices of materials to be used. Methods for fabricating such structures are disclosed as well.
摘要翻译：这里描述的是包括用于在超导量子电路中提供电连接的互连的结构。一种结构包括设置在互连支撑层的表面上的第一和第二互连，例如，其上提供超导量子位的衬底，设置在该表面下方的下互连（即，下平面互连）以及用于提供下互连与第一和第二互连中的每一个之间的电互连的通孔。在超导量子电路中提供低于平面的互连允许实现超导和机械稳定的互连。通过键合两个基板（可选择材料）实现底平面互连，可以最大限度地减少下平面互连周围区域中的伪二电平系统的数量，同时允许使用不同的材料选择。也公开了制造这种结构的方法。

69. 发明申请

WO2017217961A1 JOSEPHSON JUNCTIONS MADE FROM REFRACTORY AND NOBLE METALS 审中-公开
标题翻译： JOSEPHSON JUNCTIONS由耐火材料和贵金属制成
公开(公告)号：WO2017217961A1
公开(公告)日：2017-12-21
申请号：PCT/US2016/037135
申请日：2016-06-13
申请人： INTEL CORPORATION
发明人： YOSCOVITS, Zachary R. , ROBERTS, Jeanette M. , PILLARISETTY, Ravi , CLARKE, James S. , MICHALAK, David J.
IPC分类号： H01L39/04 , H01L39/12 , H01L39/24
摘要： Described herein are structures that include Josephson Junctions (JJs) to be used in superconducting qubits of quantum circuits disposed on a substrate. The JJs of these structures are fabricated using an approach that allows a wide selection of suitable materials for use in JJs and that can be efficiently used in large scale manufacturing. Thus, proposed fabrication techniques provide a substantial improvement with respect to conventional approaches, such as e.g. double-angle shadow evaporation approach, which are limited in their choice of materials and include fabrications steps that are not manufacturable at the larger wafer sizes used by leading edge device manufactures. In one aspect of the present disclosure, resulting Josephson Junctions may include base and/or top electrodes made from refractory and/or noble metals. Furthermore, tunnel barrier layers of such Josephson Junctions are not limited to oxides of the electrode materials.
摘要翻译：这里描述的结构包括用于设置在衬底上的量子电路的超导量子位中的约瑟夫森结（JJs）。这些结构的JJ通过使用允许在JJ中使用的适当材料的广泛选择并且可以有效用于大规模制造的方法来制造。因此，所提出的制造技术相对于常规方法提供了实质性改进，例如，双角度阴影蒸发方法，这些方法在材料的选择上受到限制，并且包括在前沿器件制造商使用的较大晶圆尺寸下无法制造的制造步骤。在本公开的一个方面中，所得约瑟夫逊结可包括由耐火材料和/或贵金属制成的基极和/或顶电极。此外，这种约瑟夫森结的隧道势垒层不限于电极材料的氧化物。

70. 发明申请

WO2017217960A1 JOSEPHSON JUNCTION DAMASCENE FABRICATION 审中-公开
标题翻译：约瑟夫森结大理石的制作
公开(公告)号：WO2017217960A1
公开(公告)日：2017-12-21
申请号：PCT/US2016/037134
申请日：2016-06-13
申请人： INTEL CORPORATION
发明人： YOSCOVITS, Zachary R. , MICHALAK, David J. , ROBERTS, Jeanette M. , PILLARISETTY, Ravi , CLARKE, James S.
IPC分类号： H01L39/02 , H01L39/24 , H01L39/12
摘要： Described herein are structures that include Josephson Junctions (JJs) to be used in superconducting qubits of quantum circuits disposed on a substrate. The JJs of these structures are fabricated using an approach that can be efficiently used in large scale manufacturing, providing a substantial improvement with respect to conventional approaches which include fabrications steps which are not manufacturable. In one aspect of the present disclosure, the proposed approach includes providing a patterned superconductor layer over a substrate, providing a layer of surrounding dielectric over the patterned superconductor layer, and providing a via opening in the layer of surrounding dielectric over a first portion of the patterned superconductor layer. The proposed approach further includes depositing in the via opening a first superconductor, a barrier dielectric, and a second superconductor to form, respectively, a base electrode, a tunnel barrier layer, and a top electrode of the JJ.
摘要翻译：这里描述的结构包括用于设置在衬底上的量子电路的超导量子位中的约瑟夫森结（JJs）。这些结构的JJ使用可以有效用于大规模制造的方法制造，相对于包括不可制造的制造步骤的常规方法提供实质性改进。在本公开的一个方面中，所提出的方法包括在衬底上提供图案化的超导体层，在图案化的超导层上提供围绕电介质层，并且在围绕电介质层的第一部分上提供通孔开口图案化的超导体层。所提出的方法进一步包括在通孔开口中沉积第一超导体，势垒电介质和第二超导体以分别形成JJ的基极电极，隧道势垒层和顶电极。

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