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61. 发明申请

US20100322027A1 MEMORY USING MULTIPLE SUPPLY VOLTAGES 有权
标题翻译：使用多个电源电压的存储器
公开(公告)号：US20100322027A1
公开(公告)日：2010-12-23
申请号：US12487791
申请日：2009-06-19
申请人： Andrew C. Russell , Prashant U. Kenkare , Shayan Zhang
发明人： Andrew C. Russell , Prashant U. Kenkare , Shayan Zhang
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C5/145
摘要： A memory has a method of operating that includes performing operations of a first type and a second type. A first voltage is coupled to a power supply node of a first memory cell of a memory array during a first operation of the first type. The first voltage is decoupled from the power supply node in response to terminating the first operation of the first type so as to allow the power supply node to drift. If the power supply node drifts to a second voltage, a power supply source is coupled to the power supply node. This is useful in reducing power in the circuit that produces the first voltage.
摘要翻译：存储器具有操作的方法，包括执行第一类型和第二类型的操作。在第一类型的第一操作期间，第一电压耦合到存储器阵列的第一存储器单元的电源节点。响应于终止第一类型的第一操作，第一电压与电源节点解耦，以允许电源节点漂移。如果电源节点漂移到第二电压，则电源被耦合到电源节点。这有助于降低产生第一电压的电路中的功率。

62. 发明申请

US20100302837A1 MEMORY WITH READ CYCLE WRITE BACK 有权
标题翻译：带循环读写的内存
公开(公告)号：US20100302837A1
公开(公告)日：2010-12-02
申请号：US12474078
申请日：2009-05-28
申请人： Shayan Zhang , Jack M. Higman , Prashant U. Kenkare , Pelley H. Perry , Andrew C. Russell
发明人： Shayan Zhang , Jack M. Higman , Prashant U. Kenkare , Pelley H. Perry , Andrew C. Russell
IPC分类号： G11C11/00 , G11C7/00 , G11C7/06
CPC分类号： G11C11/413 , G11C7/106 , G11C7/12
摘要： A memory has a first bit line, a second bit line, and a word line. A memory cell is coupled to the word line and the first and second bit lines. A sense amplifier has a first input, a second input, a first output, and a second output. A pair of coupling transistors includes a first transistor and a second transistor. In one embodiment, the first transistor is coupled between the first bit line and the first input of the sense amplifier and the second transistor is coupled between the second bit line and the second input of the sense amplifier. A write back circuit is coupled to an output of the sense amplifier. The write back circuit writes back to the memory cell a value read from the memory cell during a read cycle.
摘要翻译：存储器具有第一位线，第二位线和字线。存储单元耦合到字线和第一和第二位线。读出放大器具有第一输入，第二输入，第一输出和第二输出。一对耦合晶体管包括第一晶体管和第二晶体管。在一个实施例中，第一晶体管耦合在第一位线和读出放大器的第一输入端之间，第二晶体管耦合在第二位线和读出放大器的第二输入端之间。写回电路耦合到读出放大器的输出端。写回电路在读周期期间将从存储单元读取的值写回到存储器单元。

63. 发明申请

US20100246297A1 INTEGRATED CIRCUIT HAVING AN EMBEDDED MEMORY AND METHOD FOR TESTING THE MEMORY 有权
标题翻译：具有嵌入式存储器的集成电路和测试存储器的方法
公开(公告)号：US20100246297A1
公开(公告)日：2010-09-30
申请号：US12414758
申请日：2009-03-31
申请人： Shayan Zhang , James D. Burnett , Kent P. Fancher , Andrew C. Russell , Michael D. Snyder
发明人： Shayan Zhang , James D. Burnett , Kent P. Fancher , Andrew C. Russell , Michael D. Snyder
IPC分类号： G11C29/00 , G11C5/14
CPC分类号： G11C29/24 , G11C5/147 , G11C11/41 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/83
摘要： A memory system has a first memory having an array of memory cells that includes a redundant column. The redundant column substitutes for a first column in the array. The first column includes a test memory cell. The array receives a power supply voltage. The test memory cell becomes non-functional at a higher power supply voltage than the memory cells of the array. A memory controller is coupled to the first memory and is for determining if the test memory cell is functional at a first value for the power supply voltage. This is useful in making decisions concerning the value of the power supply voltage applied to the array.
摘要翻译：存储器系统具有包括冗余列的存储器单元阵列的第一存储器。冗余列替代数组中的第一列。第一列包括测试存储单元。阵列接收电源电压。测试存储单元在比阵列的存储单元更高的电源电压下变得不起作用。存储器控制器耦合到第一存储器，并且用于确定测试存储器单元是否以电源电压的第一值起作用。这对于对应用于阵列的电源电压的值做出决定是有用的。

64. 发明授权

US07684264B2 Memory system with RAM array and redundant RAM memory cells having a different designed cell circuit topology than cells of non redundant RAM array 有权
标题翻译：具有RAM阵列和冗余RAM存储单元的存储器系统具有与非冗余RAM阵列的单元不同的设计单元电路拓扑
公开(公告)号：US07684264B2
公开(公告)日：2010-03-23
申请号：US11627445
申请日：2007-01-26
申请人： Bradford L. Hunter , James D. Burnett , Andrew C. Russell , Shayan Zhang
发明人： Bradford L. Hunter , James D. Burnett , Andrew C. Russell , Shayan Zhang
IPC分类号： G11C7/00
CPC分类号： G11C29/846 , G11C11/41 , G11C11/412 , G11C29/816
摘要： A memory system including a random access memory (RAM) array and a corresponding redundant RAM array which stores information redundant to the RAM array, where a designed cell circuit topology of cells within the redundant RAM array differs from a designed cell circuit topology of cells within the RAM array. The redundant RAM array is selectively accessed when accessing the RAM array to store data to the redundant RAM array for failed cells of the RAM array.
摘要翻译：一种存储器系统，包括随机存取存储器（RAM）阵列和相应的冗余RAM阵列，其存储对RAM阵列冗余的信息，其中冗余RAM阵列内的单元的设计单元电路拓扑不同于设计的单元的单元电路拓扑 RAM阵列。当访问RAM阵列时，有选择地访问冗余RAM阵列，以将数据存储到RAM阵列的故障单元的冗余RAM阵列中。

65. 发明授权

US07523373B2 Minimum memory operating voltage technique 有权
标题翻译：最低内存工作电压技术
公开(公告)号：US07523373B2
公开(公告)日：2009-04-21
申请号：US11468458
申请日：2006-08-30
申请人： Andrew C. Russell , David R. Bearden , Bradford L. Hunter , Shayan Zhang
发明人： Andrew C. Russell , David R. Bearden , Bradford L. Hunter , Shayan Zhang
IPC分类号： G01R31/30
CPC分类号： G11C5/147 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/50016 , G11C2029/5004
摘要： A method includes an integrated circuit with a memory. The memory operates with an operating voltage. A value of a minimum operating voltage of the memory is determined. The value of the minimum operating voltage is stored in a non-volatile memory location that maybe a non-volatile register. This minimum operating voltage information can then be used in determining when an alternative power supply voltage may be switched to the memory or ensuring that the minimum voltage is otherwise met. The minimum voltage can be used only internal to the integrated circuit or also provided externally to a user.
摘要翻译：一种方法包括具有存储器的集成电路。存储器工作在工作电压。确定存储器的最小工作电压值。最小工作电压的值存储在可能是非易失性寄存器的非易失性存储器位置。然后可以使用该最小工作电压信息来确定什么时候可以将替代电源电压切换到存储器或确保以其他方式满足最小电压。最小电压只能用于集成电路内部，也可以在用户外部使用。

66. 发明授权

US07443745B2 Byte writeable memory with bit-column voltage selection and column redundancy 有权
标题翻译：字节可写存储器，具有位列电压选择和列冗余
公开(公告)号：US07443745B2
公开(公告)日：2008-10-28
申请号：US11612626
申请日：2006-12-19
申请人： Andrew C. Russell
发明人： Andrew C. Russell
IPC分类号： G11C29/00
CPC分类号： G11C29/83 , G11C11/41
摘要： A method for accessing a memory comprising a first set of bit columns, a second set of bit columns, and a redundant set of bit columns, wherein any one of the redundant set of bit columns can be substituted for one of the first set of bit columns or one of the second set of bit columns and wherein each of the bit columns can receive a read voltage or a write voltage, is provided. The method includes during a write operation to the first set of bit columns, providing the write voltage to one of the redundant set of bit columns, if the one of the redundant set of bit columns has been substituted for one of the first set of bit columns, otherwise providing the read voltage to the redundant set of bit columns.
摘要翻译：一种用于访问存储器的方法，所述存储器包括第一组位列，第二组位列和冗余的位列集合，其中所述冗余位列集合中的任何一个可以代替所述第一组位列或第二组位列中的一个，并且其中每个位列可以接收读取电压或写入电压。该方法包括在对第一组位列的写入操作期间，将写入电压提供给冗余的一组比特列中的一个，如果冗余的一组比特列已被代替第一组比特列中的一个列，否则将读取电压提供给冗余的位列集合。

67. 发明授权

US08400819B2 Integrated circuit having variable memory array power supply voltage 有权
标题翻译：具有可变存储阵列电源电压的集成电路
公开(公告)号：US08400819B2
公开(公告)日：2013-03-19
申请号：US12714079
申请日：2010-02-26
申请人： Andrew C. Russell
发明人： Andrew C. Russell
IPC分类号： G11C11/00
CPC分类号： G11C7/04 , G11C7/02 , G11C7/14 , G11C11/412
摘要： An integrated circuit comprises a memory array and a bias circuit. The memory array comprises a plurality of memory cells arranged in a grid of rows and columns. A first conductor is coupled to a power supply voltage terminal of each of the plurality of memory cells. A second conductor is coupled to receive a power supply voltage. The memory array also includes a plurality of dummy cells. A transistor of one or more of the plurality of dummy cells has a first current electrode coupled to the first conductor, a second current electrode coupled to the second conductor, and a control electrode. The bias circuit is coupled to the control electrode of the transistor.
摘要翻译：集成电路包括存储器阵列和偏置电路。存储器阵列包括以行和列格网排列的多个存储单元。第一导体耦合到多个存储单元中的每一个的电源电压端子。第二导体被耦合以接收电源电压。存储器阵列还包括多个虚拟单元。多个虚设单元中的一个或多个的晶体管具有耦合到第一导体的第一电流电极，耦合到第二导体的第二电流电极和控制电极。偏置电路耦合到晶体管的控制电极。

68. 发明授权

US08059482B2 Memory using multiple supply voltages 有权
标题翻译：内存使用多个电源电压
公开(公告)号：US08059482B2
公开(公告)日：2011-11-15
申请号：US12487791
申请日：2009-06-19
申请人： Andrew C. Russell , Prashant U. Kenkare , Shayan Zhang
发明人： Andrew C. Russell , Prashant U. Kenkare , Shayan Zhang
IPC分类号： G11C5/14
CPC分类号： G11C11/413 , G11C5/145
摘要： A memory has a method of operating that includes performing operations of a first type and a second type. A first voltage is coupled to a power supply node of a first memory cell of a memory array during a first operation of the first type. The first voltage is decoupled from the power supply node in response to terminating the first operation of the first type so as to allow the power supply node to drift. If the power supply node drifts to a second voltage, a power supply source is coupled to the power supply node. This is useful in reducing power in the circuit that produces the first voltage.
摘要翻译：存储器具有操作的方法，包括执行第一类型和第二类型的操作。在第一类型的第一操作期间，第一电压耦合到存储器阵列的第一存储器单元的电源节点。响应于终止第一类型的第一操作，第一电压与电源节点解耦，以允许电源节点漂移。如果电源节点漂移到第二电压，则电源被耦合到电源节点。这有助于降低产生第一电压的电路中的功率。

69. 发明授权

US07525866B2 Memory circuit 有权
标题翻译：存储电路
公开(公告)号：US07525866B2
公开(公告)日：2009-04-28
申请号：US11406585
申请日：2006-04-19
申请人： Andrew C. Russell
发明人： Andrew C. Russell
IPC分类号： G11C8/00
CPC分类号： G11C5/14 , G11C5/025
摘要： A memory includes a plurality of memory arrays. Each of the plurality of memory arrays includes a plurality of sub-arrays. A plurality of power supply conductors are provided over the memory for supplying power to the plurality of memory arrays. When accessing the memory to simultaneously read a plurality of bits from the memory, the sub-arrays are accessed so as to provide a relatively uniform current demand on the plurality of power supply conductors. In one embodiment, the accessed sub-arrays are organized so that sides, or edges, of each accessed sub-array are not adjacent to each other.
摘要翻译：存储器包括多个存储器阵列。多个存储器阵列中的每一个包括多个子阵列。多个电源导体设置在存储器上用于向多个存储器阵列供电。当访问存储器以同时从存储器读取多个位时，子阵列被访问以便在多个电源导体上提供相对均匀的电流需求。在一个实施例中，所访问的子阵列被组织成使得每个被访问的子阵列的边或边不彼此相邻。

70. 发明授权

US07492627B2 Memory with increased write margin bitcells 有权
标题翻译：具有增加的写入边沿位单元的存储器
公开(公告)号：US07492627B2
公开(公告)日：2009-02-17
申请号：US11561255
申请日：2006-11-17
申请人： Andrew C. Russell , Prashant U. Kenkare , Perry H. Pelley
发明人： Andrew C. Russell , Prashant U. Kenkare , Perry H. Pelley
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C8/16
摘要： A memory comprising a first bit line, a second bit line, a word line, a first pair of cross-coupled inverters having a first input/output node and a second input/output node, a first power supply node and a second power supply node, wherein the first power supply node is coupled to a first power supply terminal, is provided. The memory further comprises a first gating transistor coupled between a second power supply terminal and the second power supply node, the first gating transistor receiving a first write enable signal that gates the gating transistor to a non-conductive condition during a write of the first pair of cross-coupled inverters. The memory further comprises a first pass transistor coupled to the first word line, the first input/output node, and the first bit line and a second pass transistor coupled to the first word line, the second input/output node, and the second bit line.
摘要翻译：一种存储器，包括第一位线，第二位线，字线，具有第一输入/输出节点和第二输入/输出节点的第一对交叉耦合的反相器，第一电源节点和第二电源节点，其中所述第一电源节点耦合到第一电源端子。存储器还包括耦合在第二电源端子和第二电源节点之间的第一门控晶体管，第一门控晶体管在第一对写入期间接收将门控晶体管栅极导入非导通状态的第一写使能信号的交叉耦合逆变器。存储器还包括耦合到第一字线，第一输入/输出节点和第一位线的第一传输晶体管和耦合到第一字线的第二传输晶体管，第二输入/输出节点和第二位线。

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