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61. 发明申请

US20110298053A1 MANUFACTURING METHOD OF GATE STACK AND SEMICONDUCTOR DEVICE 有权
标题翻译：栅极堆叠和半导体器件的制造方法
公开(公告)号：US20110298053A1
公开(公告)日：2011-12-08
申请号：US12997625
申请日：2010-09-19
申请人： Huicai Zhong , Zhijiong Luo , Qingqing Liang
发明人： Huicai Zhong , Zhijiong Luo , Qingqing Liang
IPC分类号： H01L29/78 , H01L21/3205 , B82Y40/00 , B82Y99/00
CPC分类号： H01L29/513 , H01L21/28176 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/78
摘要： A manufacturing method of a gate stack with sacrificial oxygen-scavenging metal spacers includes: forming a gate stack structure consisting of an interfacial oxide layer, a high-K dielectric layer and a metal gate electrode, on a semiconductor substrate; conformally depositing a metal layer covering the semiconductor substrate and the gate stack structure; and selectively etching the metal layer to remove the portions of the metal layer covering the top surface of the gate stack structure and the semiconductor substrate, so as to only keep the sacrificial oxygen-scavenging metal spacers surrounding the gate stack structure in the outer periphery of the gate stack structure. A semiconductor device manufactured by this process.
摘要翻译：具有牺牲氧清除金属间隔物的栅极堆叠的制造方法包括：在半导体衬底上形成由界面氧化物层，高K电介质层和金属栅电极组成的栅叠层结构; 保形地沉积覆盖半导体衬底和栅极堆叠结构的金属层; 并且选择性地蚀刻金属层以去除覆盖栅极堆叠结构和半导体衬底的顶表面的金属层的部分，以便仅将围绕栅极堆叠结构的牺牲氧清除金属间隔物保持在外部周边门堆栈结构。通过该方法制造的半导体器件。

62. 发明申请

US20150236134A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20150236134A1
公开(公告)日：2015-08-20
申请号：US14412237
申请日：2012-07-18
申请人： Huicai Zhong , Qingqing Liang , Chao Zhao
发明人： Huicai Zhong , Qingqing Liang , Chao Zhao
IPC分类号： H01L29/66
CPC分类号： H01L29/66795 , H01L21/268 , H01L21/76283 , H01L29/665 , H01L29/785
摘要： A method of manufacturing a FinFET semiconductor device is provided, wherein the semiconductor fins are formed in a parallel arrangement which intersects the gates arranged in parallel. The polycrystalline silicon layer is deposited and then converted into a single crystal silicon layer such that the single crystal silicon layer and the semiconductor fins are integrated in essence, i.e., the source/drain region in the semiconductor fins is raised and the top area of the semiconductor fins is extended. Subsequently, the single crystal silicon layer above the top of the semiconductor fins is converted into a metal silicide so as to form a source/drain region contact. The source/drain region contact in the present invention has a larger area than that in a conventional FinFET, which decreases the contact resistance and facilitates the formation of a self-aligned metal plug in the follow-up process.
摘要翻译：提供一种制造FinFET半导体器件的方法，其中半导体鳍片形成为与并行布置的栅极相交的平行布置。沉积多晶硅层，然后转换为单晶硅层，使得单晶硅层和半导体鳍片本质上是集成的，即半导体鳍片中的源极/漏极区域被升高，并且顶部区域半导体鳍片延伸。随后，将半导体鳍片顶部上方的单晶硅层转换为金属硅化物，以形成源极/漏极区域接触。本发明中的源极/漏极区域的接触面积大于传统的FinFET的面积，这在以后的过程中降低了接触电阻并且有利于形成自对准的金属插塞。

63. 发明授权

US08748983B2 Embedded source/drain MOS transistor 有权
标题翻译：嵌入式源极/漏极MOS晶体管
公开(公告)号：US08748983B2
公开(公告)日：2014-06-10
申请号：US13380828
申请日：2011-08-12
申请人： Huicai Zhong , Chao Zhao , Qingqing Liang
发明人： Huicai Zhong , Chao Zhao , Qingqing Liang
IPC分类号： H01L27/12 , H01L21/70
CPC分类号： H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： An embedded source/drain MOS transistor and a formation method thereof are provided. The embedded source/drain MOS transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source/drain stack embedded in the semiconductor substrate at both sides of the gate structure with an upper surface of the source/drain stack being exposed, wherein the source/drain stack comprises a dielectric layer and a semiconductor layer above the dielectric layer. The present invention can cut off the path for the leakage current from the source region and the drain region to the semiconductor substrate, thereby reducing the leakage current from the source region and the drain region to the semiconductor substrate.
摘要翻译：提供一种嵌入式源极/漏极MOS晶体管及其形成方法。嵌入式源极/漏极MOS晶体管包括：半导体衬底; 半导体衬底上的栅极结构; 以及在源极/漏极叠层的上表面被暴露的栅极结构的两侧嵌入在半导体衬底中的源极/漏极堆叠，其中源极/漏极叠层包括电介质层和介电层上方的半导体层。本发明可以切断从源极区域和漏极区域到半导体衬底的漏电流的路径，从而减少从源极区域和漏极区域到半导体衬底的漏电流。

64. 发明申请

US20130228893A1 TRENCH ISOLATION STRUCTURE AND METHOD FOR FORMING THE SAME 有权
标题翻译： TRENCH隔离结构及其形成方法
公开(公告)号：US20130228893A1
公开(公告)日：2013-09-05
申请号：US13145301
申请日：2011-04-22
申请人： Huicai Zhong , Chao Zhao , Qingqing Liang
发明人： Huicai Zhong , Chao Zhao , Qingqing Liang
IPC分类号： H01L21/762 , H01L29/02
CPC分类号： H01L21/76224 , H01L21/76232 , H01L29/02
摘要： A trench isolation structure and a method of forming the same are provided. The trench isolation structure includes: a semiconductor substrate, and trenches formed on the surface of the semiconductor substrate and filled with a dielectric layer, wherein the material of the dielectric layer is a crystalline material. By using the present invention, the size of the divot can be reduced, and device performances can be improved.
摘要翻译：提供了沟槽隔离结构及其形成方法。沟槽隔离结构包括：半导体衬底和形成在半导体衬底的表面上并填充有电介质层的沟槽，其中电介质层的材料是结晶材料。通过使用本发明，可以减小纹路的尺寸，并且可以提高器件性能。

65. 发明申请

US20120273886A1 EMBEDDED SOURCE/DRAIN MOS TRANSISTOR AND METHOD FOR FORMING THE SAME 有权
标题翻译：嵌入式源/漏极MOS晶体管及其形成方法
公开(公告)号：US20120273886A1
公开(公告)日：2012-11-01
申请号：US13380828
申请日：2011-08-12
申请人： Huicai Zhong , Chao Zhao , Qingqing Liang
发明人： Huicai Zhong , Chao Zhao , Qingqing Liang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： An embedded source/drain MOS transistor and a formation method thereof are provided. The embedded source/drain MOS transistor comprises: a semiconductor substrate; a gate structure on the semiconductor substrate; and a source/drain stack embedded in the semiconductor substrate at both sides of the gate structure with an upper surface of the source/drain stack being exposed, wherein the source/drain stack comprises a dielectric layer and a semiconductor layer above the dielectric layer. The present invention can cut off the path for the leakage current from the source region and the drain region to the semiconductor substrate, thereby reducing the leakage current from the source region and the drain region to the semiconductor substrate.
摘要翻译：提供一种嵌入式源极/漏极MOS晶体管及其形成方法。嵌入式源极/漏极MOS晶体管包括：半导体衬底; 半导体衬底上的栅极结构; 以及在源极/漏极叠层的上表面被暴露的栅极结构的两侧嵌入在半导体衬底中的源极/漏极堆叠，其中源极/漏极叠层包括电介质层和介电层上方的半导体层。本发明可以切断从源极区域和漏极区域到半导体衬底的漏电流的路径，从而减少从源极区域和漏极区域到半导体衬底的漏电流。

66. 发明申请

US20120261727A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING LOCAL INTERCONNECT STRUCTURE THEREOF 有权
标题翻译：半导体器件及其制造方法本地互连结构
公开(公告)号：US20120261727A1
公开(公告)日：2012-10-18
申请号：US13380061
申请日：2011-02-27
申请人： Huicai Zhong , Qingqing Liang
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L29/772 , H01L21/768
CPC分类号： H01L29/78 , H01L21/76895 , H01L21/76897
摘要： A semiconductor device and a method for manufacturing a local interconnect structure for a semiconductor device is provided. The method includes forming removable sacrificial sidewall spacers between sidewall spacers and outer sidewall spacers on two sides of a gate on a semiconductor substrate, and forming contact through-holes at source/drain regions in the local interconnect structure between the sidewall spacer and the outer sidewall spacer on the same side of the gate immediately after removing the sacrificial sidewall spacers. Once the source/drain through-holes are filled with a conductive material to form contact vias, the height of the contact vias shall be same as the height of the gate. The contact through-holes, which establish the electrical connection between a subsequent first layer of metal wiring and the source/drain regions or the gate region at a lower level in the local interconnect structure, shall be made in the same depth.
摘要翻译：提供半导体器件和用于制造半导体器件的局部互连结构的方法。该方法包括在半导体衬底上的栅极的两侧上的侧壁间隔件和外侧壁间隔件之间形成可移除的牺牲侧壁间隔件，以及在侧壁间隔件和外侧壁之间的局部互连结构中的源极/漏极区域处形成接触通孔在去除牺牲侧壁间隔物之后立即在栅极的同一侧上间隔开。一旦源极/漏极通孔填充有导电材料以形成接触孔，接触孔的高度应与栅极的高度相同。在本地互连结构中，建立后续的第一金属布线层和源极/漏极区域或较低电平的栅极区域之间的电连接的接触通孔应制成相同的深度。

67. 发明申请

US20120220097A1 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20120220097A1
公开(公告)日：2012-08-30
申请号：US13061824
申请日：2010-09-26
申请人： Huicai Zhong , Qingqing Liang
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/3086 , H01L21/76897 , H01L29/41783 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/7843 , H01L29/7848
摘要： A method of manufacturing a semiconductor device is provided, in which after forming a gate stack and a first spacer thereof, a second spacer and a third spacer are formed; and then an opening is formed between the first spacer and the third spacer by removing the second spacer. The range of the formation for the raised active area 220 is limited by forming an opening 214 between the first spacer 208 and the third spacer 212. The raised active area 220 is formed in the opening 214 in a self-aligned manner, so that a better profile of the raised active area 220 may be achieved and the possible shorts between adjacent devices caused by an unlimited manner may be avoided. Moreover, based on such a manufacturing method, it is easy to make the gate electrode 204 to be flushed with the raised active area 220, and is also easy to implement the dual stress nitride process so as to increase the mobility of the device.
摘要翻译：提供一种制造半导体器件的方法，其中在形成栅极堆叠及其第一间隔物之后，形成第二间隔物和第三间隔物; 然后通过移除第二间隔件在第一间隔件和第三间隔件之间形成开口。通过在第一间隔件208和第三间隔件212之间形成开口214来限制凸起的有效区域220的形成范围。凸起的有源区域220以自对准的方式形成在开口214中，使得可以实现凸起的有效区域220的更好的轮廓，并且可以避免由无限制的方式引起的相邻设备之间的可能的短路。此外，基于这样的制造方法，可以容易地利用凸起的有源区域220冲洗栅电极204，并且也容易实施双应力氮化物工艺，以增加器件的移动性。

68. 发明申请

US20120149181A1 METHOD FOR MANUFACTURING SEMICONDUCTOR WAFER 有权
标题翻译：制造半导体波形的方法
公开(公告)号：US20120149181A1
公开(公告)日：2012-06-14
申请号：US13201125
申请日：2011-02-25
申请人： Huicai Zhong , Qingqing Liang , Chao Zhao
发明人： Huicai Zhong , Qingqing Liang , Chao Zhao
IPC分类号： H01L21/24
CPC分类号： H01L21/3221
摘要： There is provided a method for manufacturing a semiconductor wafer, comprising: performing heating so that metals dissolve into semiconductors of the wafer to form a semiconductor-metal compound; and performing cooling so that the formed semiconductor-metal compound retrogradely melt to form a mixture of the metals and the semiconductors. According to embodiments of the present invention, it is possible to achieve wafers of a high purity applicable to the semiconductor manufacture.
摘要翻译：提供了一种制造半导体晶片的方法，包括：进行加热，使得金属溶解到晶片的半导体中以形成半导体 - 金属化合物; 并进行冷却，使得所形成的半导体 - 金属化合物逆向熔融以形成金属和半导体的混合物。根据本发明的实施例，可以实现适用于半导体制造的高纯度晶片。

69. 发明授权

US09607877B2 Substrate structure, semiconductor device, and method for manufacturing the same 有权
公开(公告)号：US09607877B2
公开(公告)日：2017-03-28
申请号：US13376731
申请日：2011-03-04
申请人： Huicai Zhong , Qingqing Liang
发明人： Huicai Zhong , Qingqing Liang
IPC分类号： H01L23/34 , H01L27/12 , H05K7/20 , H01L21/762 , H01L27/06 , H01L27/088
CPC分类号： H01L21/76224 , H01L21/76283 , H01L27/0694 , H01L27/088
摘要： The present invention provides a substrate structure, a semiconductor device, and a manufacturing method thereof. The substrate structure comprises: a semiconductor substrate; and a first isolation region, wherein the first isolation region comprises: a first trench extending through the semiconductor substrate; and a first dielectric layer filling the first trench. Due to the isolation region extending through the substrate, it is possible to make device structures on both surfaces of the substrate, so as to increase the utilization of the substrate and the integration degree of the devices.

70. 发明授权

US09070719B2 Semiconductor device structure, method for manufacturing the same, and method for manufacturing Fin 有权
标题翻译：半导体装置结构及其制造方法以及制造方法
公开(公告)号：US09070719B2
公开(公告)日：2015-06-30
申请号：US13577942
申请日：2011-11-18
申请人： Huicai Zhong , Qingqing Liang , Jun Luo , Chao Zhao
发明人： Huicai Zhong , Qingqing Liang , Jun Luo , Chao Zhao
IPC分类号： H01L21/762 , H01L21/336 , H01L29/78 , H01L29/66 , H01L21/8234 , H01L21/8238 , H01L29/06 , H01L21/84
CPC分类号： H01L29/66795 , H01L21/823431 , H01L21/823481 , H01L21/823821 , H01L21/823878 , H01L21/845 , H01L29/0649 , H01L29/66545 , H01L29/785
摘要： A semiconductor device structure, a method for manufacturing the same, and a method for manufacturing a semiconductor fin are disclosed. In one embodiment, the method for manufacturing the semiconductor device structure comprises: forming a fin in a first direction on a semiconductor substrate; forming a gate line in a second direction, the second direction crossing the first direction on the semiconductor substrate, and the gate line intersecting the fin with a gate dielectric layer sandwiched between the gate line and the fin; forming a dielectric spacer surrounding the gate line; and performing inter-device electrical isolation at a predetermined position, wherein isolated portions of the gate line form independent gate electrodes of respective devices.
摘要翻译：公开了一种半导体器件结构，其制造方法和半导体鳍片的制造方法。在一个实施例中，制造半导体器件结构的方法包括：在半导体衬底上沿第一方向形成翅片; 在第二方向上形成栅极线，在半导体衬底上与第一方向交叉的第二方向和与鳍状物交叉的栅极线与夹在栅极线和鳍之间的栅极电介质层形成栅极线; 形成围绕所述栅极线的介电隔离层; 以及在预定位置执行器件间电隔离，其中所述栅极线的隔离部分形成各个器件的独立栅电极。

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