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61. 发明申请

US20080142946A1 WAFER LEVEL PACKAGE WITH GOOD CTE PERFORMANCE 审中-公开
标题翻译：具有良好CTE性能的WAFER LEVEL PACKAGE
公开(公告)号：US20080142946A1
公开(公告)日：2008-06-19
申请号：US11609970
申请日：2006-12-13
申请人： Wen-Kun Yang , Tung-Chuan Wang , Chao-Nan Chou , Chih-Wei Lin
发明人： Wen-Kun Yang , Tung-Chuan Wang , Chao-Nan Chou , Chih-Wei Lin
IPC分类号： H01L23/48 , H01L21/56
CPC分类号： H01L23/3128 , H01L21/6835 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/82 , H01L24/97 , H01L2224/04105 , H01L2224/20 , H01L2224/24227 , H01L2224/32225 , H01L2224/73267 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01059 , H01L2924/01068 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/181 , H01L2924/19043 , H01L2924/351 , H01L2224/82 , H01L2924/00
摘要： The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the redistribution built up layer. Terminal Conductive bumps are coupled to the UBM.
摘要翻译：本发明提供了一种包装结构，其包括具有预先形成的模具容纳空腔的基板和/或形成在基板的上表面内的端接触金属焊盘。通过粘合将模具设置在模具接收腔内，并且在模具和基板上形成介电层。在电介质层上形成至少一个重新分配建立层（RDL），并通过接触焊盘与芯片耦合。连接结构，例如，UBM形成在再分配建立层上。端子导电凸块耦合到UBM。

62. 发明授权

US07224061B2 Package structure 有权
标题翻译：包装结构
公开(公告)号：US07224061B2
公开(公告)日：2007-05-29
申请号：US10918416
申请日：2004-08-16
申请人： Wen-Kun Yang , Shih-Li Chen , Wen-Bin Sun , Ming-Hui Lin , Chao-Nan Chou , Chih-Wei Lin
发明人： Wen-Kun Yang , Shih-Li Chen , Wen-Bin Sun , Ming-Hui Lin , Chao-Nan Chou , Chih-Wei Lin
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/3114 , H01L23/3128 , H01L24/19 , H01L2224/05001 , H01L2224/05026 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05548 , H01L2224/12105 , H01L2924/01029 , H01L2924/09701 , H01L2924/10253 , H01L2924/15311 , H01L2924/181 , H01L2924/18162 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/3025 , H01L2924/00 , H01L2924/00014
摘要： A package structure including a device, an interconnecting element, a pad and a protecting element is provided. The device connects with a first end of the interconnecting element through the pad. The protecting element covers the pad and the first end of the interconnecting element.
摘要翻译：提供包括器件，互连元件，焊盘和保护元件的封装结构。该装置通过焊盘与互连元件的第一端连接。保护元件覆盖焊盘和互连元件的第一端。

63. 发明申请

US20150018484A1 POLYIMIDE FILM AND FABRICATION METHOD THEREOF 有权
标题翻译：聚酰亚胺膜及其制造方法
公开(公告)号：US20150018484A1
公开(公告)日：2015-01-15
申请号：US14249702
申请日：2014-04-10
申请人： Chih-Wei Lin , Meng-Ying Tsai
发明人： Chih-Wei Lin , Meng-Ying Tsai
IPC分类号： C08J5/18 , B29C39/00
CPC分类号： C08J5/18 , B29C39/003 , B29K2079/08 , B29K2105/0032 , C08G73/1067 , C08G73/1071 , C08J2379/08 , C09D179/08
摘要： A polyimide film includes a polyimide polymer forming a main molecular structure of the polyimide film, and polyimide particles present in the polyimide film at a weight ratio between about 15 wt % and 30 wt % of a total weight of the polyimide film, the polyimide particles having an average diameter between about 3 μm and 8 μm. The polyimide film can have a 60° gloss value equal to or smaller than 10, a haze equal to or higher than 90%, and a Young's modulus equal to or higher than 280 kgf/mm2. In some embodiments, methods of fabricating the polyimide film are also described.
摘要翻译：聚酰亚胺膜包括形成聚酰亚胺膜的主要分子结构的聚酰亚胺聚合物和以聚酰亚胺膜的总重量的约15重量％至30重量％的重量比存在于聚酰亚胺膜中的聚酰亚胺颗粒，聚酰亚胺颗粒平均直径约3μm至8μm。聚酰亚胺膜可以具有等于或小于10的60°光泽值，雾度等于或高于90％，杨氏模量等于或高于280kgf / mm2。在一些实施例中，还描述了制造聚酰亚胺膜的方法。

64. 发明申请

US20120181669A1 FRAME CELL FOR SHOT LAYOUT FLEXIBILITY 有权
标题翻译：用于拍摄布局灵活性的框架单元
公开(公告)号：US20120181669A1
公开(公告)日：2012-07-19
申请号：US13409517
申请日：2012-03-01
申请人： Chin-Ming LIN , Chia-hung Huang , Chi-Ming Yang , Chin-Hsiang Lin , Yung-Cheng Chen , Chih-Wei Lin
发明人： Chin-Ming LIN , Chia-hung Huang , Chi-Ming Yang , Chin-Hsiang Lin , Yung-Cheng Chen , Chih-Wei Lin
IPC分类号： H01L23/544 , G06F17/50
CPC分类号： G03F7/70433
摘要： A method includes establishing an initial shot layout in which a number of shots are arranged in vertically aligned columns and horizontally aligned rows to cover a semiconductor wafer. At least one of a row of shots or a column of shots is shifted relative to an adjacent row or column of shots to establish at least one additional shot layout that differs from the initial shot layout in that shots in the at least one shifted row or column of shots are not aligned with the shots in the adjacent row or column of shots with which they were aligned in the initial shot layout. One of the initial shot layout and the at least one additional shot layout is selected as a final shot layout. The wafer is exposed to light using the final shot layout.
摘要翻译：一种方法包括建立初始照片布局，其中多个照片布置在垂直排列的列和水平排列的行中以覆盖半导体晶片。一排照片或一列照片中的至少一列相对于相邻的行或列发射位移，以建立与至少一个移位行中的拍摄中的初始镜头布局不同的至少一个附加镜头布局，或一列照片不与在初始镜头布局中对齐的相邻行或照片列中的镜头对齐。选择初始镜头布局和至少一个附加镜头布局之一作为最终镜头布局。使用最终镜头布局将晶片曝光。

65. 发明授权

US07956375B2 Light emitting diode structure having a textured package lens 有权
标题翻译：具有纹理化封装透镜的发光二极管结构
公开(公告)号：US07956375B2
公开(公告)日：2011-06-07
申请号：US12485237
申请日：2009-06-16
申请人： Yueh-Han Li , Po-Tang Hsu , Chien-Ming Ko , Hung-Ching Lee , Chih-Wei Lin
发明人： Yueh-Han Li , Po-Tang Hsu , Chien-Ming Ko , Hung-Ching Lee , Chih-Wei Lin
IPC分类号： H01L29/22 , H01L29/227 , H01L33/00 , H01L31/0203
CPC分类号： H01L33/54 , H01L33/58
摘要： A light emitting diode structure and a light emitting diode structure forming method are provided. The light emitting diode structure includes a base, a diode chip, and a package lens. The diode chip is mounted on the base. The package lens covers the diode chip. The surface of the package lens includes a plurality of dot structures. The steps of the method include mounting a light-emitting diode chip on a base, assembling a package lens to cover the light emitting diodes chip, and forming a plurality of dot structures on the surface of the package lens.
摘要翻译：提供了发光二极管结构和发光二极管结构形成方法。发光二极管结构包括基座，二极管芯片和封装透镜。二极管芯片安装在基座上。封装透镜覆盖二极管芯片。封装透镜的表面包括多个点结构。该方法的步骤包括将发光二极管芯片安装在基座上，组装封装透镜以覆盖发光二极管芯片，以及在封装透镜的表面上形成多个点状结构。

66. 发明授权

US07883240B2 Light emitting diode based light source assembly 有权
标题翻译：基于发光二极管的光源组件
公开(公告)号：US07883240B2
公开(公告)日：2011-02-08
申请号：US11967034
申请日：2007-12-29
申请人： Pei-Chin Lee , Chih-Wei Lin , Hung-Kuang Hsu
发明人： Pei-Chin Lee , Chih-Wei Lin , Hung-Kuang Hsu
IPC分类号： F21S4/00
CPC分类号： F21V29/763 , F21K9/00 , F21V19/0055 , F21V29/004 , F21V29/74 , F21V29/89 , F21Y2115/10 , H01L2924/0002 , H01L2924/00
摘要： An LED based light source assembly (10) comprises a circuit board (11), a plurality of LEDs (13), a heat sink (15) and a plurality of fasteners (17). The circuit board comprises a first surface (12) and a second surface (14) opposite to the first surface. The first surface is provided with electrical conductive traces (118). The plurality of LEDs are arranged on the first surface of the circuit board and electrically connecting with the electrical wires of the circuit board. The heat sink thermally contacts the second surface of the circuit board. The plurality of fasteners each comprise a first end (172) and a second end (174) opposite to the first end. The first end of each of the fasteners abuts on the first surface of the circuit board. The second end of each of the fasteners extends through the circuit board to be secured to the heat sink.
摘要翻译：一种基于LED的光源组件（10）包括电路板（11），多个LED（13），散热片（15）和多个紧固件（17）。电路板包括与第一表面相对的第一表面（12）和第二表面（14）。第一表面设有导电迹线（118）。多个LED布置在电路板的第一表面上并与电路板的电线电连接。散热片与电路板的第二表面热接触。多个紧固件各自包括与第一端相对的第一端（172）和第二端（174）。每个紧固件的第一端邻接在电路板的第一表面上。每个紧固件的第二端延伸穿过电路板以固定到散热器。

67. 发明授权

US07876963B2 Symbol recognition method 有权
标题翻译：符号识别方法
公开(公告)号：US07876963B2
公开(公告)日：2011-01-25
申请号：US11846628
申请日：2007-08-29
申请人： Ming-Hung Lin , Chih-Wei Lin
发明人： Ming-Hung Lin , Chih-Wei Lin
IPC分类号： G06K9/48 , G06K9/62
CPC分类号： G06K9/2054 , G06K2209/01
摘要： A symbol recognition method for increasing the symbol recognition speed by the processor includes the steps of obtaining a pixel density value and an aspect ratio of the symbol image. Then, the center-point value and the corresponding radius value are obtained by a partitional clustering algorithm. In sequence, a pixel density value and the aspect ratio of the under recognized image are obtained, and compared with the values of the symbol image to determine whether the under recognized image is a single symbol image or not.
摘要翻译：用于通过处理器增加符号识别速度的符号识别方法包括以下步骤：获得符号图像的像素密度值和宽高比。然后，通过分数聚类算法获得中心点值和对应的半径值。顺序地，获得像素密度值和未识别图像的长宽比，并且与符号图像的值进行比较，以确定未识别的图像是否是单个符号图像。

68. 发明授权

US07655501B2 Wafer level package with good CTE performance 有权
标题翻译：晶圆级封装具有良好的CTE性能
公开(公告)号：US07655501B2
公开(公告)日：2010-02-02
申请号：US12141138
申请日：2008-06-18
申请人： Wen-Kun Yang , Tung-Chuan Wang , Chao-Nan Chou , Chih-Wei Lin
发明人： Wen-Kun Yang , Tung-Chuan Wang , Chao-Nan Chou , Chih-Wei Lin
IPC分类号： H01L21/00
CPC分类号： H01L23/3128 , H01L21/6835 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/82 , H01L24/97 , H01L2224/04105 , H01L2224/20 , H01L2224/24227 , H01L2224/32225 , H01L2224/73267 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01059 , H01L2924/01068 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/181 , H01L2924/19043 , H01L2924/351 , H01L2224/82 , H01L2924/00
摘要： The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the re-distribution built up layer. Terminal Conductive bumps are coupled to the UBM.
摘要翻译：本发明提供了一种包装结构，其包括具有预先形成的模具容纳空腔的基板和/或形成在基板的上表面内的端接触金属焊盘。通过粘合将模具设置在模具接收腔内，并且在模具和基板上形成介电层。在电介质层上形成至少一个重新分配建立层（RDL），并通过接触焊盘与芯片耦合。连接结构，例如UBM形成在重新分配建立的层上。端子导电凸块耦合到UBM。

69. 发明申请

US20090327771A1 POWER SUPPLY SYSTEM AND POWER SUPPLYING CONTROL METHOD 有权
标题翻译：电源系统和供电控制方法
公开(公告)号：US20090327771A1
公开(公告)日：2009-12-31
申请号：US12483941
申请日：2009-06-12
申请人： Chih-Wei Lin , Chih-Wan Hsu , Nung-Te Huang
发明人： Chih-Wei Lin , Chih-Wan Hsu , Nung-Te Huang
IPC分类号： G06F1/00
CPC分类号： G06F1/263
摘要： A power supplying control method of a computer system for use with a first power supply and a second power supply both providing a first specific voltage to a motherboard, including steps of: detecting whether the first power supply and the second power supply, outputting the first specific voltage, are at a stable state; outputting the first specific voltage to a first pin when the first power supply is at the stable state; outputting the first specific voltage to the first pin when the second power supply is at the stable state; and outputting the first specific voltage to the motherboard via the first pin.
摘要翻译：一种与向主板提供第一特定电压的第一电源和第二电源一起使用的计算机系统的供电控制方法，包括以下步骤：检测第一电源和第二电源，输出第一电源具体电压处于稳定状态; 当第一电源处于稳定状态时，将第一特定电压输出到第一引脚; 当第二电源处于稳定状态时，将第一特定电压输出到第一引脚; 以及经由所述第一引脚将所述第一特定电压输出到所述母板。

70. 发明申请

US20080248614A1 WAFER LEVEL PACKAGE WITH GOOD CTE PERFORMANCE 有权
标题翻译：具有良好CTE性能的WAFER LEVEL PACKAGE
公开(公告)号：US20080248614A1
公开(公告)日：2008-10-09
申请号：US12141138
申请日：2008-06-18
申请人： Wen-Kun Yang , Tung-Chuan Wang , Chao-Nan Chou , Chih-Wei Lin
发明人： Wen-Kun Yang , Tung-Chuan Wang , Chao-Nan Chou , Chih-Wei Lin
IPC分类号： H01L21/58
CPC分类号： H01L23/3128 , H01L21/6835 , H01L23/5389 , H01L24/19 , H01L24/24 , H01L24/82 , H01L24/97 , H01L2224/04105 , H01L2224/20 , H01L2224/24227 , H01L2224/32225 , H01L2224/73267 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01059 , H01L2924/01068 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/09701 , H01L2924/10253 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/157 , H01L2924/15787 , H01L2924/181 , H01L2924/19043 , H01L2924/351 , H01L2224/82 , H01L2924/00
摘要： The present invention provides a structure of package comprising a substrate with a pre-formed die receiving cavity formed and/or terminal contact metal pads formed within an upper surface of the substrate. A die is disposed within the die receiving cavity by adhesion and a dielectric layer formed on the die and the substrate. At least one re-distribution built up layer (RDL) is formed on the dielectric layer and coupled to the die via contact pad. Connecting structure, for example, UBM is formed over the re-distribution built up layer. Terminal Conductive bumps are coupled to the UBM.
摘要翻译：本发明提供了一种包装结构，其包括具有预先形成的模具容纳空腔的基板和/或形成在基板的上表面内的端接触金属焊盘。通过粘合将模具设置在模具接收腔内，并且在模具和基板上形成介电层。在电介质层上形成至少一个重新分配建立层（RDL），并通过接触焊盘与芯片耦合。连接结构，例如UBM形成在重新分配建立的层上。端子导电凸块耦合到UBM。

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