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61. 发明授权

US5330928A Method for fabricating stacked capacitors with increased capacitance in a DRAM cell 失效
标题翻译：用于在DRAM单元中制造具有增加的电容的叠层电容器的方法
公开(公告)号：US5330928A
公开(公告)日：1994-07-19
申请号：US951794
申请日：1992-09-28
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10817
摘要： A method is described for fabricating a dynamic random access memory having a high capacitance stacked capacitor. Gate structures and associated source/drain structures are formed within the device areas. A first silicon oxide layer is formed over the device and field oxide areas. The stacked capacitors are now formed by first depositing a thick second polysilicon layer over the device and field oxide areas. Openings are formed to the desired source/drain structures by etching through the second oxide, second polysilicon, and first oxide layers. Cavities are formed between the first and second oxide layers by laterally etching the second polysilicon layer. A third polysilicon layer is deposited over the device and field oxide areas. The second and third polysilicon layers and the first and second oxide layers are patterned so as to have their remaining portions over the planned capacitor areas. The layers are etched leaving the third polysilicon layer as the bottom storage node electrode contacting the source/drain structures. The remaining second and third polysilicon layers form the storage node of the capacitor. A capacitor dielectric layer is formed over the bottom electrode polysilicon layer. A contact polysilicon layer is deposited as the top plate electrode and the contact polysilicon layer and the dielectric layer are patterned to complete the stacked capacitor.
摘要翻译：描述了一种用于制造具有高电容堆叠电容器的动态随机存取存储器的方法。栅极结构和相关的源极/漏极结构形成在器件区域内。在器件和场氧化物区域上形成第一氧化硅层。现在通过首先在器件和场氧化物区域上沉积厚的第二多晶硅层来形成堆叠的电容器。通过蚀刻通过第二氧化物，第二多晶硅和第一氧化物层，将所希望的源极/漏极结构形成开口。通过横向蚀刻第二多晶硅层，在第一和第二氧化物层之间形成空穴。在器件和场氧化物区域上沉积第三多晶硅层。图案化第二和第三多晶硅层以及第一和第二氧化物层，使其剩余部分在规划的电容器区域上。当底部存储节点电极接触源极/漏极结构时，这些层被蚀刻离开第三多晶硅层。剩余的第二和第三多晶硅层形成电容器的存储节点。电容器电介质层形成在底部电极多晶硅层上。沉积接触多晶硅层作为顶板电极，并且对接触多晶硅层和电介质层进行图案化以完成叠层电容器。

62. 发明授权

US5126916A Stacked capacitor dram cell and method of fabricating 失效
标题翻译：堆叠电容器电容器及其制造方法
公开(公告)号：US5126916A
公开(公告)日：1992-06-30
申请号：US810832
申请日：1991-12-20
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L27/108
CPC分类号： H01L27/10817
摘要： A DRAM having stacked high capacitance capacitors formed by depositing a thick undoped polysilicon layer over field oxide areas thereon, patterning the polysilicon layer so as to have portions over the planned stacked capacitor areas, forming a silicon oxide layer on the exposed surface of the polysilicon, removing the silicon oxide layer from horizontal surfaces of the polysilicon layer by anisotropic etching, removing the polysilicon layer by isotropic etching leaving vertical silicon oxide structures, and forming openings to desired source/drain structures of the DRAM using lithography and etching. A bottom electrode polysilicon layer is deposited over the device and field oxide areas to make contact to the source/drain structures. A capacitor dielectric layer is formed over the bottom electrode polysilicon layer. A contact polysilicon layer is deposited as the top storage node electrode and the contact polysilicon layer and the dielectric layers are patterned.
摘要翻译：通过在其上的场氧化物区域上沉积厚的未掺杂的多晶硅层而形成堆叠的高电容电容器的DRAM，对多晶硅层进行构图以便在预定的叠层电容器区域上形成部分，在多晶硅的暴露表面上形成氧化硅层，通过各向异性蚀刻从多晶硅层的水平表面去除氧化硅层，通过各向同性蚀刻去除多晶硅层，留下垂直的氧化硅结构，以及使用光刻和蚀刻在DRAM的所需源极/漏极结构上形成开口。底部电极多晶硅层沉积在器件和场氧化物区域上以与源极/漏极结构接触。电容器电介质层形成在底部电极多晶硅层上。沉积接触多晶硅层作为顶部存储节点电极，并且接触多晶硅层和电介质层被图案化。

63. 发明授权

US08368220B2 Anchored damascene structures 有权
标题翻译：锚定镶嵌结构
公开(公告)号：US08368220B2
公开(公告)日：2013-02-05
申请号：US11252498
申请日：2005-10-18
申请人： David Lu , Horng-Huei Tseng , Syun-Ming Jang
发明人： David Lu , Horng-Huei Tseng , Syun-Ming Jang
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76802 , H01L21/76807 , H01L21/76816 , H01L21/76831 , H01L23/5226 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An anchored conductive damascene buried in a multi-density dielectric layer and method for forming the same, the anchored conductive damascene including a dielectric layer with an opening extending through a thickness of the dielectric layer; wherein the dielectric layer comprises at least one relatively higher density portion and a relatively lower density portion, the relatively lower density portion forming a contiguous major portion of the dielectric layer; and, wherein the opening in the relatively lower density portion has a lateral dimension relatively larger compared to the relatively higher density portion to form anchoring steps.
摘要翻译：埋置在多密度电介质层中的锚定导电镶嵌体及其形成方法，所述锚定导电镶嵌体包括具有延伸穿过介电层厚度的开口的介电层; 其中所述电介质层包括至少一个相对较高密度的部分和相对较低的密度部分，所述较低密度部分形成所述电介质层的连续主要部分; 并且其中相对较低密度部分中的开口具有与相对较高密度部分相比较大的横向尺寸以形成锚固步骤。

64. 发明授权

US08034711B2 Bonding structure and fabrication thereof 有权
标题翻译：粘结结构及其制造
公开(公告)号：US08034711B2
公开(公告)日：2011-10-11
申请号：US11964195
申请日：2007-12-26
申请人： Chen-Hua Yu , Horng-Huei Tseng
发明人： Chen-Hua Yu , Horng-Huei Tseng
IPC分类号： H01L21/4763
CPC分类号： H01L24/05 , H01L21/76849 , H01L21/76867 , H01L21/76886 , H01L23/53233 , H01L23/5329 , H01L24/03 , H01L24/13 , H01L24/45 , H01L2224/0401 , H01L2224/04042 , H01L2224/05147 , H01L2224/05647 , H01L2224/05681 , H01L2224/05684 , H01L2224/13101 , H01L2224/13144 , H01L2224/45124 , H01L2224/45144 , H01L2224/48647 , H01L2224/48684 , H01L2224/48747 , H01L2224/48784 , H01L2924/01014 , H01L2924/01019 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2224/48781 , H01L2224/48681
摘要： A bonding structure and the method of fabricating the same are disclosed. The bonding structure of the invention includes a copper-based pad formed in an insulator layer and a protection layer substantially covering top surface of the copper-based pad. The protection layer is self-aligned formed and the material thereof is selected from a group consisting of metal nitride, copper alloy, copper compounds, and a combination thereof.
摘要翻译：公开了一种接合结构及其制造方法。本发明的接合结构包括形成在绝缘体层中的铜基焊盘和基本上覆盖铜基焊盘顶表面的保护层。保护层是自对准的，其材料选自金属氮化物，铜合金，铜化合物及其组合。

65. 发明授权

US07221584B2 MRAM cell having shared configuration 有权
标题翻译：具有共享配置的MRAM单元
公开(公告)号：US07221584B2
公开(公告)日：2007-05-22
申请号：US11053379
申请日：2005-02-08
申请人： Chi-Wen Liu , Kuo-Ching Chiang , Horng-Huei Tseng , Denny D. Tang
发明人： Chi-Wen Liu , Kuo-Ching Chiang , Horng-Huei Tseng , Denny D. Tang
IPC分类号： G11C11/00 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L27/228
摘要： A magnetic memory includes two first magnetic layers each oriented over a substrate, a second magnetic layer interposing the two first magnetic layers, and two dielectric layers each contacting the second magnetic layer and interposing the second magnetic layer and one of the two first magnetic layers. Each of the first and second magnetic layers and the dielectric layers may be oriented substantially perpendicular to the substrate or at an acute angle relative to the substrate.
摘要翻译：磁存储器包括两个分别定向在衬底上的第一磁性层，插入两个第一磁性层的第二磁性层和与第二磁性层接触并插入第二磁性层和两个第一磁性层之一的两个电介质层。第一和第二磁性层和电介质层中的每一个可以基本上垂直于衬底取向或相对于衬底成锐角。

66. 发明申请

US20060163735A1 Damascene process at semiconductor substrate level 有权
标题翻译：半导体衬底级的镶嵌工艺
公开(公告)号：US20060163735A1
公开(公告)日：2006-07-27
申请号：US11357697
申请日：2006-02-17
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L21/76846 , H01L21/76802 , H01L21/76807 , H01L21/76831 , H01L21/76864 , H01L21/76877 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： A damascene structure and process at semiconductor substrate level. A pre-metal dielectric layer is provided on a semiconductor substrate with an opening exposing a contact region on the substrate. A buffer metal layer is provided on the exposed contact region, and a barrier layer is provided on the interior of the opening. A conductor is provided on the buffer metal layer, substantially filling the opening to electrically connect to the contact region.
摘要翻译：半导体衬底级别的镶嵌结构和工艺。在半导体衬底上设置预金属电介质层，该开口露出衬底上的接触区域。在暴露的接触区域上设置有缓冲金属层，在开口的内部设有阻挡层。导体设置在缓冲金属层上，基本上填充开口以电连接到接触区域。

67. 发明申请

US20060043463A1 Floating gate having enhanced charge retention 审中-公开
标题翻译：浮动门具有增强的电荷保持
公开(公告)号：US20060043463A1
公开(公告)日：2006-03-02
申请号：US10932198
申请日：2004-09-01
申请人： Chi-Wen Liu , Kuo-Ching Chiang , Horng-Huei Tseng , Wen-Tin Chu
发明人： Chi-Wen Liu , Kuo-Ching Chiang , Horng-Huei Tseng , Wen-Tin Chu
IPC分类号： H01L29/788
CPC分类号： H01L21/28194 , H01L21/28202 , H01L27/115 , H01L29/42324 , H01L29/517 , H01L29/518
摘要： A semiconductor device includes a source and a drain formed in a substrate, a tunneling dielectric formed on the substrate between the source and the drain, and a floating gate disposed over the tunneling dielectric having a band-gap energy less than the energy band-gap of silicon.
摘要翻译：半导体器件包括形成在衬底中的源极和漏极，形成在源极和漏极之间的衬底上的隧道电介质，以及设置在隧道电介质上的浮置栅极，其带隙能量小于能带隙能量的硅。

68. 发明申请

US20060033133A1 MRAM cell having shared configuration 有权
标题翻译：具有共享配置的MRAM单元
公开(公告)号：US20060033133A1
公开(公告)日：2006-02-16
申请号：US11053379
申请日：2005-02-08
申请人： Chi-Wen Liu , Kuo-Ching Chiang , Horng-Huei Tseng , Denny Tang
发明人： Chi-Wen Liu , Kuo-Ching Chiang , Horng-Huei Tseng , Denny Tang
IPC分类号： H01L29/94
CPC分类号： H01L27/228
摘要： A magnetic memory includes two first magnetic layers each oriented over a substrate, a second magnetic layer interposing the two first magnetic layers, and two dielectric layers each contacting the second magnetic layer and interposing the second magnetic layer and one of the two first magnetic layers. Each of the first and second magnetic layers and the dielectric layers may be oriented substantially perpendicular to the substrate or at an acute angle relative to the substrate.
摘要翻译：磁存储器包括两个分别定向在衬底上的第一磁性层，插入两个第一磁性层的第二磁性层和与第二磁性层接触并插入第二磁性层和两个第一磁性层之一的两个电介质层。第一和第二磁性层和电介质层中的每一个可以基本上垂直于衬底取向或相对于衬底成锐角。

69. 发明申请

US20060028626A1 Megasonic immersion lithography exposure apparatus and method 有权
标题翻译：超声波浸没式光刻曝光装置及方法
公开(公告)号：US20060028626A1
公开(公告)日：2006-02-09
申请号：US10910480
申请日：2004-08-03
申请人： Ching-Yu Chang , Chien-Hung Lin , Chin-Hsiang Lin , David Lu , Horng-Huei Tseng , Burn-Jeng Lin
发明人： Ching-Yu Chang , Chien-Hung Lin , Chin-Hsiang Lin , David Lu , Horng-Huei Tseng , Burn-Jeng Lin
IPC分类号： G03B27/52
CPC分类号： G03F7/70341
摘要： A megasonic immersion lithography exposure apparatus and method for substantially eliminating microbubbles from an exposure liquid in immersion lithography is disclosed. The apparatus includes an optical system for projecting light through a mask and onto a wafer. An optical transfer chamber is provided adjacent to the optical system for containing an exposure liquid. At least one megasonic plate operably engages the optical transfer chamber for inducing sonic waves in and eliminating microbubbles from the exposure liquid.
摘要翻译：公开了一种用于在浸没式光刻中基本上消除曝光液体中的微泡的兆声浸没式光刻曝光装置和方法。该装置包括用于通过掩模将光投射到晶片上的光学系统。光学传递室邻近光学系统设置，用于容纳曝光液体。至少一个兆欧表板可操作地接合光学传递室，用于在曝光液体中引入声波并消除微泡。

70. 发明申请

US20050286030A1 Immersion optical projection system 有权
标题翻译：浸入式光学投影系统
公开(公告)号：US20050286030A1
公开(公告)日：2005-12-29
申请号：US11009505
申请日：2004-12-10
申请人： Jen-Chieh Shih , Burn-Jeng Lin , Tsai-Sheng Gau , Ru-Gun Liu , Chun-Kuang Chen , Chin-Hsiang Lin , Horng-Huei Tseng
发明人： Jen-Chieh Shih , Burn-Jeng Lin , Tsai-Sheng Gau , Ru-Gun Liu , Chun-Kuang Chen , Chin-Hsiang Lin , Horng-Huei Tseng
IPC分类号： G03B27/52 , G03F7/20
CPC分类号： G03F7/70341
摘要： An immersion optical projection system for photolithography is provided. A transparent plate is located between a last lens element and the wafer during a usage of the system. The transparent plate has a lens-side surface and a wafer-side surface. The system is adapted to have a layer of lens-side fluid located between the last lens element and the lens-side surface of the transparent plate, e.g., when the last lens element is operably located over the wafer during a photolithography process. The system is also adapted to have a layer of wafer-side fluid located between the wafer-side surface of the transparent plate and the wafer, during a usage of the system. The wafer-side fluid may or may not be fluidly connected to the lens-side fluid. The wafer-side fluid may or may not differ from the lens-side fluid.
摘要翻译：提供了一种用于光刻的浸没式光学投影系统。在使用系统期间，透明板位于最后一个透镜元件和晶片之间。透明板具有透镜侧表面和晶片侧表面。该系统适于具有位于最后透镜元件和透明板的透镜侧表面之间的透镜侧流体层，例如当光刻工艺期间最后一个透镜元件可操作地位于晶片上方时。该系统还适于在系统的使用期间具有位于透明板的晶片侧表面和晶片之间的晶片侧流体层。晶片侧流体可以或可以不流体地连接到透镜侧流体。晶片侧流体可以或可以不与透镜侧流体不同。

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