会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 61. 发明申请
    • Delay locked operation in semiconductor memory device
    • 在半导体存储器件中延迟锁定操作
    • US20070070731A1
    • 2007-03-29
    • US11523704
    • 2006-09-20
    • Hoon Choi
    • Hoon Choi
    • G11C7/00
    • G11C7/1051G11C7/1057G11C7/1066G11C7/22G11C7/222
    • A semiconductor memory device has a control circuit capable of properly controlling a delay locked loop in a variety of operational modes. The semiconductor memory device includes a clock buffer for externally receiving a system clock to output it as an internal clock, a delay locked loop unit for controlling a delay of the internal clock such that a data output timing is synchronized with the system clock; a data output buffer for synchronizing data with the delay locked internal clock, thereby outputting the data, and a clock buffer control unit, responsive to a previous operation state, for generating an enable signal controlling the on/off switching of the clock buffer.
    • 半导体存储器件具有能够适当地控制各种操作模式中的延迟锁定环路的控制电路。 半导体存储器件包括用于外部接收系统时钟以将其作为内部时钟输出的时钟缓冲器,用于控制内部时钟的延迟以使得数据输出定时与系统时钟同步的延迟锁定环单元; 数据输出缓冲器,用于使数据与延迟锁定的内部时钟同步,从而输出数据;以及时钟缓冲器控制单元,响应于先前的操作状态,用于产生控制时钟缓冲器的接通/断开切换的使能信号。
    • 64. 发明申请
    • Heat reflector and substrate processing apparatus comprising the same
    • 热反射器和包括其的基板处理装置
    • US20060249695A1
    • 2006-11-09
    • US11405563
    • 2006-04-18
    • Hoon Choi
    • Hoon Choi
    • A61N5/00
    • H01L21/67115F27B5/04F27B17/0025Y10T428/24273
    • A substrate processing apparatus includes a process chamber including upper and lower quartz walls, a substrate support disposed in the process chamber, radiant heaters respectively provided above and below the quartz walls of the chamber, and heat reflectors disposed outside the process chamber for reflecting heat towards the substrate support. Each of the heat reflectors has heating has a first thermally reflective section oriented to reflect the heat towards an outer peripheral region of the substrate support and a second thermally reflective section oriented to reflect the heat towards a central region of the substrate support. Each heat reflector also has a reflection angle adjusting mechanism by which an angle at which the second thermally reflective section reflects heat can be adjusted. The angle is adjusted depending on the temperature distribution across the substrate so that the substrate can be processed uniformly.
    • 基板处理装置包括具有上,下石英壁的处理室,设置在处理室中的基板支撑件,分别设置在室的石英壁上方和下方的辐射加热器,以及设置在处理室外部的热反射器,用于将热量反射 衬底支撑。 每个热反射器具有加热,其具有第一热反射部分,其被定向成朝着基板支撑件的外周区域反射热量;以及第二热反射部件,其被定向成朝着基板支撑件的中心区域反射热量。 每个热反射器还具有反射角调节机构,通过该反射角调节机构可以调节第二热反射部分反射热量的角度。 根据衬底上的温度分布来调节角度,使得可以均匀地处理衬底。
    • 67. 发明申请
    • Fibrous composite for tissue engineering
    • 组织工程纤维复合材料
    • US20050226904A1
    • 2005-10-13
    • US10507059
    • 2003-03-14
    • Hoon ChoiI-Wei Chen
    • Hoon ChoiI-Wei Chen
    • A61F2/00A61F2/02A61K9/70A61L27/18A61L27/44C12N20060101
    • A61L27/56A61L27/025A61L27/18A61L27/446A61L27/58C08L67/04
    • Provided are fibrous composites prepared by methods of the present invention, comprising oxides and biodegradable polymers, in which the fibers are made of aerogel-like oxide materials having nanometer-sized pores. The fibrous composition advantageously has, at least, the following characteristics: (i) a very high nanoporous surface area, which also permits nucleation of crystallites; (ii) mesoporous/macroporous interspacial networks between the fibers, providing high bioactivity and a high transport rate; (iii) macropores for natural one-like tissue growth; (iv) good mechanical properties for handling and for implant support; and (v) biodegradability for implant dissolution and time-variable mechanical properties. Further provided are methods for using the bioactive biodegradable fibrous composites as osteogenic composite materials for tissue engineering, tissue re-growth, bone implants, and bone repair, and/or for the delivery of drugs or therapeutic compounds.
    • 提供了通过本发明的方法制备的纤维复合材料,其包括氧化物和可生物降解的聚合物,其中纤维由具有纳米尺寸孔的气凝胶状氧化物材料制成。 纤维组合物有利地至少具有以下特征:(i)非常高的纳米孔表面积,其也允许微晶成核; (ii)纤维之间的介孔/大孔间隙网络,提供高生物活性和高传输速率; (iii)用于天然单样组织生长的大孔; (iv)用于处理和植入支持的良好的机械性能; 和(v)植入物溶解和时变机械性能的生物降解性。 还提供了使用生物活性生物可降解纤维复合材料作为用于组织工程,组织再生长,骨植入物和骨修复,和/或递送药物或治疗化合物的成骨复合材料的方法。
    • 69. 发明授权
    • Metal oxide semiconductor capacitors having uniform C-V characteristics
over an operating range and reduced susceptibility to insulator
breakdown
    • 金属氧化物半导体电容器在工作范围内具有均匀的C-V特性,并降低对绝缘体击穿的敏感性
    • US5793074A
    • 1998-08-11
    • US684464
    • 1996-07-19
    • Hoon ChoiSeung-Cheol Oh
    • Hoon ChoiSeung-Cheol Oh
    • H01L27/04H01L21/822H01L29/94H01L27/108
    • H01L29/94
    • A MOS capacitor has uniform C-V capacitance characteristics across an operating voltage range and has reduced susceptibility to insulator breakdown and includes a semiconductor substrate of first conductivity type, a region of insulating material on an upper surface of the substrate and a well region of second conductivity type extending adjacent the region of insulating material. The well region is spaced from the region of insulating material so that the substrate extends to the upper surface therebetween. A source region of second conductivity type is formed in the well region. An insulating layer is formed on the source region and extends over the region of insulating material. A first electrode is formed on the insulating layer and a second electrode is formed on the source region. The capacitor also includes a P-N junction established between the source region of second conductivity type and the region of insulating material beneath the insulating layer. This P-N junction provides the capacitor with substantially uniform capacitance characteristics when a voltage is applied between the first electrode and the second electrode. Furthermore, because some of the voltage differential is established across the P-N junction during operation, the electric field at the corner of the region of insulating material and the insulating layer is reduced.
    • MOS电容器在工作电压范围内具有均匀的CV电容特性,并且降低了对绝缘体击穿的敏感性,并且包括第一导电类型的半导体衬底,衬底上表面上的绝缘材料区域和第二导电类型的阱区 在绝缘材料的区域附近延伸。 阱区域与绝缘材料的区域隔开,使得衬底延伸到它们之间的上表面。 在阱区中形成第二导电类型的源区。 绝缘层形成在源极区域上并在绝缘材料的区域上延伸。 第一电极形成在绝缘层上,第二电极形成在源极区上。 电容器还包括在第二导电类型的源极区域和绝缘层下方的绝缘材料区域之间建立的P-N结。 当在第一电极和第二电极之间施加电压时,该P-N结为电容器提供基本均匀的电容特性。 此外,由于在工作期间跨越P-N结建立了一些电压差,所以绝缘材料区域和绝缘层的拐角处的电场减小。
    • 70. 发明授权
    • Integrated circuits including power supply boosters and methods of
operating same
    • 集成电路,包括电源增压器和操作方法
    • US5754075A
    • 1998-05-19
    • US649427
    • 1996-05-16
    • Seung-Cheol OhHoon Choi
    • Seung-Cheol OhHoon Choi
    • G11C11/407G11C5/14G11C8/08G05F1/10
    • G11C5/145G11C8/08
    • An integrated circuit provides a power supply voltage, a first boosted voltage, and a second boosted voltage which is preferably equal to or greater than the first boosted voltage, to the integrated circuit transistors, such that the integrated circuit transistors operate using the power supply voltage, the first boosted voltage and the second boosted voltage. The integrated circuit includes a first boosting circuit which boosts the power supply voltage to a first boosted voltage and a second boosting circuit which boosts the power supply voltage to a second boosted voltage. The first boosting circuit is preferably responsive to application of the power supply voltage to the integrated circuit and the second boosting circuit is preferably responsive to application of the power supply voltage to the integrated circuit and to an enable signal. Preferably, the first boosting circuit applies the first boosted voltage to the bulk region of selected PMOS transistors in the integrated circuit and the second boosting circuit applies the second boosting voltage to the source regions of selected PMOS transistors. In one embodiment, the first and second boosted voltages are applied to the word line driver of an integrated circuit memory device such that the second boosted voltage is applied to the source of the word line driver PMOS transistors in response to a row address strobe signal. High speed operations are thereby provided with reduced susceptibility to bridging defect errors.
    • 集成电路向集成电路晶体管提供优选等于或大于第一升压电压的电源电压,第一升压电压和第二升压电压,使得集成电路晶体管使用电源电压 ,第一升压电压和第二升压电压。 集成电路包括将电源电压升高到第一升压电压的第一升压电路和将电源电压升高到第二升压电压的第二升压电路。 第一升压电路优选地响应于向集成电路施加电源电压,并且第二升压电路优选地响应于将电源电压施加到集成电路和使能信号。 优选地,第一升压电路将第一升压电压施加到集成电路中所选择的PMOS晶体管的体区,并且第二升压电路将第二升压电压施加到所选PMOS晶体管的源极区。 在一个实施例中,第一和第二升压电压被施加到集成电路存储器件的字线驱动器,使得响应于行地址选通信号将第二升压电压施加到字线驱动器PMOS晶体管的源极。 因此,提供了高速度操作,降低了对桥接缺陷错误的敏感性。