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61. 发明申请

US20110277682A1 DIRECTIONAL SOLID PHASE CRYSTALLIZATION OF THIN AMORPHOUS SILICON FOR SOLAR CELL APPLICATIONS 审中-公开
标题翻译：用于太阳能电池应用的薄膜非晶硅的方向固定相结晶
公开(公告)号：US20110277682A1
公开(公告)日：2011-11-17
申请号：US13184295
申请日：2011-07-15
申请人： Virnedra V. RANA , Robert Z. Bachrach
发明人： Virnedra V. RANA , Robert Z. Bachrach
IPC分类号： C30B1/06
CPC分类号： H01L21/0262 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02573 , H01L21/02609 , H01L31/068 , H01L31/1804 , H01L31/1872 , Y02E10/547 , Y02P70/521 , Y10T117/10
摘要： Embodiments of the invention provide a system for heat treating a substrate which includes a first processing chamber having a first processing region coupled with a precursor source assembly configured to deliver a silicon containing gas to an upper surface of a substrate disposed within the first processing region in order to form an amorphous silicon film on the upper surface. The system further includes a substrate support having a heating element configured to heat the substrate to a temperature sufficient to crystallize the amorphous silicon film by solid phase crystallization and to create a temperature gradient in which a temperature at the lower surface of the substrate is greater than a temperature at the upper surface of the amorphous silicon film and the temperature gradient is within a range from about 2° C. to about 10° C.
摘要翻译：本发明的实施例提供了一种用于热处理衬底的系统，其包括具有第一处理区域的第一处理区域，该第一处理区域与被构造成将含硅气体输送到设置在第一处理区域内的衬底的上表面的前体源组件耦合为了在上表面形成非晶硅膜。该系统还包括具有加热元件的衬底支撑件，该加热元件被配置为将衬底加热到足以通过固相结晶使非晶硅膜结晶的温度，并产生温度梯度，其中衬底的下表面的温度大于非晶硅膜的上表面的温度和温度梯度在约2℃至约10℃的范围内。

62. 发明申请

US20110021008A1 Directional Solid Phase Crystallization of Thin Amorphous Silicon for Solar Cell Applications 失效
标题翻译：用于太阳能电池应用的薄无定形硅的定向固相结晶
公开(公告)号：US20110021008A1
公开(公告)日：2011-01-27
申请号：US12507761
申请日：2009-07-22
申请人： Virendra V. RANA , Robert Z. Bachrach
发明人： Virendra V. RANA , Robert Z. Bachrach
IPC分类号： H01L21/20 , C23C16/00
CPC分类号： H01L21/0262 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02573 , H01L21/02609 , H01L31/068 , H01L31/1804 , H01L31/1872 , Y02E10/547 , Y02P70/521 , Y10T117/10
摘要： Embodiments of the present invention provide a method for converting a doped amorphous silicon layer deposited onto a crystalline silicon substrate into crystalline silicon having the same grain structure and crystal orientation as the underlying crystalline silicon substrate upon which the amorphous silicon was initially deposited. Additional embodiments of the present invention provide depositing a dielectric passivation layer onto the amorphous silicon layer prior to the conversion. A temperature gradient is provided at a temperature and for a time period sufficient to provide a desired p-n junction depth and dopant profile.
摘要翻译：本发明的实施例提供了一种将沉积在晶体硅衬底上的掺杂非晶硅层转换成具有与初始沉积非晶硅的下面的晶体硅衬底相同的晶粒结构和晶体取向的晶体硅的方法。本发明的另外的实施例提供了在转换之前在非晶硅层上沉积介电钝化层。在足以提供期望的p-n结深度和掺杂剂分布的温度和时间段提供温度梯度。

63. 发明申请

US20100323503A1 INTEGRATED EMITTER FORMATION AND PASSIVATION 审中-公开
标题翻译：集成发射体形成和钝化
公开(公告)号：US20100323503A1
公开(公告)日：2010-12-23
申请号：US12872272
申请日：2010-08-31
申请人： Virendra V. Rana , Robert Z. Bachrach
发明人： Virendra V. Rana , Robert Z. Bachrach
IPC分类号： H01L21/22
CPC分类号： H01L21/02532 , H01L21/02667 , H01L31/02167 , H01L31/1804 , H01L31/1864 , Y02E10/547 , Y02P70/521
摘要： Embodiments of the present invention provide a method for forming an emitter region in a crystalline silicon substrate and passivating the surface thereof by depositing a doped amorphous silicon layer onto the crystalline silicon substrate and thermally annealing the crystalline silicon substrate while oxidizing the surface thereof. In one embodiment, the deposited film is completely converted to oxide. In another embodiment, the doped amorphous silicon layer deposited onto the crystalline silicon substrate is converted into crystalline silicon having the same grain structure and crystal orientation as the underlying crystalline silicon substrate upon which the amorphous silicon was initially deposited during emitter formation. In one embodiment, at least a portion of the converted crystalline silicon is further converted into silicon dioxide during the emitter surface passivation.
摘要翻译：本发明的实施方式提供了一种在晶体硅衬底中形成发射极区域并通过在晶体硅衬底上沉积掺杂的非晶硅层并使晶体硅衬底氧化其表面进行热退火而钝化其表面的方法。在一个实施方案中，沉积的膜完全转化为氧化物。在另一个实施例中，沉积到晶体硅衬底上的掺杂非晶硅层被转换成具有与在发射极形成期间最初沉积非晶硅的下面的晶体硅衬底相同的晶粒结构和晶体取向的晶体硅。在一个实施例中，在发射极表面钝化期间，转化的晶体硅的至少一部分进一步转化成二氧化硅。

64. 发明申请

US20100240172A1 METHODS OF MAKING AN EMITTER HAVING A DESIRED DOPANT PROFILE 失效
标题翻译：制造具有所需眩光配置文件的发射器的方法
公开(公告)号：US20100240172A1
公开(公告)日：2010-09-23
申请号：US12562734
申请日：2009-09-18
申请人： Virendra V.S. Rana , Robert Z. Bachrach
发明人： Virendra V.S. Rana , Robert Z. Bachrach
IPC分类号： H01L31/18
CPC分类号： H01L31/03529 , H01L21/02532 , H01L21/02573 , H01L21/02667 , H01L31/022441 , H01L31/068 , H01L31/0682 , H01L31/1872 , Y02E10/547 , Y02P70/521
摘要： A method for obtaining a desired dopant profile of an emitter for a solar cell which includes depositing a first amorphous silicon layer having a first doping level over an upper surface of the crystalline silicon substrate, depositing a second amorphous silicon layer having a second doping level on the first amorphous silicon layer, and heating the crystalline silicon substrate and the first and second amorphous silicon layers to a temperature sufficient to cause solid phase epitaxial crystallization of the first and second amorphous silicon layers, such that the first and second amorphous silicon layers, after heating, have the same grain structure and crystal orientation as the underlying crystalline silicon substrate
摘要翻译：一种用于获得用于太阳能电池的发射器的期望掺杂物分布的方法，其包括在所述晶体硅衬底的上表面上沉积具有第一掺杂水平的第一非晶硅层，将具有第二掺杂水平的第二非晶硅层沉积在第一非晶硅层，并且将晶体硅衬底和第一和第二非晶硅层加热到足以引起第一和第二非晶硅层的固相外延结晶的温度，使得第一和第二非晶硅层在加热，具有与下面的晶体硅衬底相同的晶粒结构和晶体取向

65. 发明申请

US20100216026A1 Thin film electrochemical energy storage device with three-dimensional anodic structure 有权
标题翻译：具有三维阳极结构的薄膜电化学储能装置
公开(公告)号：US20100216026A1
公开(公告)日：2010-08-26
申请号：US12459313
申请日：2009-06-30
申请人： Sergey D. Lopatin , Dmitri A. Brevnov , Robert Z. Bachrach
发明人： Sergey D. Lopatin , Dmitri A. Brevnov , Robert Z. Bachrach
IPC分类号： H01M2/16 , C25D5/00
CPC分类号： H01M10/0585 , C25D1/00 , C25D1/006 , H01M2/1653 , H01M2/1686 , H01M4/0428 , H01M4/133 , H01M4/1393 , H01M4/364 , H01M4/587 , H01M4/667 , H01M4/70 , H01M6/40 , H01M10/0525 , H01M10/0565 , H01M10/0566 , H01M10/058
摘要： A method for forming a battery from via thin-film deposition processes is disclosed. A mesoporous carbon material is deposited onto a surface of a conductive substrate that has high surface area, conductive micro-structures formed thereon. A porous, dielectric separator layer is then deposited on the layer of mesoporous carbon material to form a half cell of an energy storage device. The mesoporous carbon material is made up of CVD-deposited carbon fullerene “onions” and carbon nano-tubes, and has a high porosity capable of retaining lithium ions in concentrations useful for storing significant quantities of electrical energy. Embodiments of the invention further provide for the formation of an electrode having a high surface area conductive region that is useful in a battery structure. In one configuration the electrode has a high surface area conductive region comprising a porous dendritic structure that can be formed by electroplating, physical vapor deposition, chemical vapor deposition, thermal spraying, and/or electroless plating techniques.
摘要翻译：公开了一种通过薄膜沉积工艺形成电池的方法。在其上形成有高表面积的导电微结构的导电性基板的表面上沉积介孔碳材料。然后将多孔介电分离器层沉积在介孔碳材料层上以形成储能装置的半电池。中孔碳材料由CVD沉积的碳富勒烯“洋葱”和碳纳米管组成，并且具有能够将锂离子保留在用于储存大量电能的浓度的高孔隙率。本发明的实施例还提供了一种用于电池结构的具有高表面积导电区域的电极的形成。在一种配置中，电极具有高的表面积导电区域，其包括通过电镀，物理气相沉积，化学气相沉积，热喷涂和/或化学镀技术形成的多孔树枝状结构。

66. 发明申请

US20100126849A1 APPARATUS AND METHOD FOR FORMING 3D NANOSTRUCTURE ELECTRODE FOR ELECTROCHEMICAL BATTERY AND CAPACITOR 审中-公开
标题翻译：用于电化学电池和电容器的三维纳米结构电极的形成方法
公开(公告)号：US20100126849A1
公开(公告)日：2010-05-27
申请号：US12620788
申请日：2009-11-18
申请人： SERGEY D. LOPATIN , Robert Z. Bachrach
发明人： SERGEY D. LOPATIN , Robert Z. Bachrach
IPC分类号： C25D5/02 , C25D5/08
CPC分类号： C25D5/022 , C25D1/003 , C25D5/08 , C25D7/00 , C25D17/00 , C25D17/10 , H01M4/0438 , Y02E60/13
摘要： Embodiments described herein generally relate to an electrode structure for an electrochemical battery or capacitor, particularly, apparatus and methods of creating a reliable and cost efficient 3D electrode nano structure for an electrochemical battery or capacitor that has an improved lifetime, lower production costs, and improved process performance.
摘要翻译：本文描述的实施方案通常涉及用于电化学电池或电容器的电极结构，特别是为电化学电池或电容器创建可靠且具有成本效益的3D电极纳米结构的设备和方法，其具有改善的寿命，降低生产成本和改进工艺性能。

67. 发明申请

US20100075485A1 INTEGRATED EMITTER FORMATION AND PASSIVATION 有权
公开(公告)号：US20100075485A1
公开(公告)日：2010-03-25
申请号：US12234848
申请日：2008-09-22
申请人： Virendra V. Rana , Robert Z. Bachrach
发明人： Virendra V. Rana , Robert Z. Bachrach
IPC分类号： H01L21/20
CPC分类号： H01L21/02532 , H01L21/02667 , H01L31/02167 , H01L31/1804 , H01L31/1864 , Y02E10/547 , Y02P70/521
摘要： Embodiments of the present invention provide a method for forming an emitter region in a crystalline silicon substrate and passivating the surface thereof by depositing a doped amorphous silicon layer onto the crystalline silicon substrate and thermally annealing the crystalline silicon substrate while oxidizing the surface thereof. In one embodiment, the deposited film is completely converted to oxide. In another embodiment, the doped amorphous silicon layer deposited onto the crystalline silicon substrate is converted into crystalline silicon having the same grain structure and crystal orientation as the underlying crystalline silicon substrate upon which the amorphous silicon was initially deposited during emitter formation. In one embodiment, at least a portion of the converted crystalline silicon is further converted into silicon dioxide during the emitter surface passivation.

68. 发明授权

US07682123B2 Compact apparatus and method for storing and loading semiconductor wafer carriers 失效
标题翻译：用于存储和加载半导体晶片载体的紧凑的装置和方法
公开(公告)号：US07682123B2
公开(公告)日：2010-03-23
申请号：US11764735
申请日：2007-06-18
申请人： Robert Z. Bachrach
发明人： Robert Z. Bachrach
IPC分类号： B65G65/00
CPC分类号： H01L21/67727 , H01L21/6773 , H01L21/67733 , H01L21/67736 , H01L21/67769 , H01L21/67772 , H01L21/67775 , H01L21/67781 , Y10S414/139 , Y10S414/14
摘要： An improved apparatus and method is provided for storing semiconductor wafer carriers, and for loading wafers or wafer carriers to a fabrication tool. The apparatus preferably provides an elevated port for receipt of wafer carriers from an overhead factory transport, allows for local interconnection among a plurality of the inventive apparatuses, and enables independent loading of the factory load port and the tool load port. An inventive wafer handling method which divides a lot of wafers into sublots and distributes the sublots among tools configured to perform the same process is also provided.
摘要翻译：提供了一种改进的装置和方法，用于存储半导体晶片载体，并将晶片或晶片载体装载到制造工具。该设备优选地提供用于从架空工厂运输接收晶片载体的升高端口，允许多个本发明设备之间的本地互连，并且使得能够独立地加载工厂装载端口和工具装载端口。还提供了一种本发明的晶片处理方法，其将大量晶片划分成子图并且在配置为执行相同处理的工具之间分配子图。

69. 发明授权

US07569462B2 Directional crystallization of silicon sheets using rapid thermal processing 失效
标题翻译：使用快速热处理的硅片的定向结晶
公开(公告)号：US07569462B2
公开(公告)日：2009-08-04
申请号：US11610049
申请日：2006-12-13
申请人： Virendra V. Rana , Robert Z. Bachrach
发明人： Virendra V. Rana , Robert Z. Bachrach
IPC分类号： H01L21/36
CPC分类号： H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： The present invention provides a method of recrystallizing a silicon sheet, and in particular recrystallizing a small grained silicon sheet to improve material properties such as grain size and orientation. According to one aspect, the method includes using rapid thermal processing (RTP) to melt and recrystallize one or more entire silicon sheet(s) in one heating sequence. According to another aspect, the method includes directionally controlling a temperature drop across the thickness of the sheet so as to facilitate the production of a small number of nuclei in the melted material and their growth into large grains. According to a further aspect, the invention includes a re-crystallization chamber in an overall process flow that enables high-throughput processing of silicon sheets having desired properties for applications such as photovoltaic modules.
摘要翻译：本发明提供了一种使硅片再结晶的方法，特别是重结晶小晶粒硅片以改善诸如晶粒尺寸和取向的材料性能。根据一个方面，该方法包括使用快速热处理（RTP）在一个加热顺序中熔融和重结晶一个或多个整个硅片。根据另一方面，该方法包括定向地控制跨越板的厚度的温度降，以便于在熔融材料中产生少量的核并且其生长成大的晶粒。根据另一方面，本发明包括在整个工艺流程中的再结晶室，其能够对具有用于诸如光伏模块的应用的所需性能的硅片进行高通量处理。

70. 发明授权

US06698991B1 Fabrication system with extensible equipment sets 失效
标题翻译：具有可扩展设备的制造系统
公开(公告)号：US06698991B1
公开(公告)日：2004-03-02
申请号：US09517227
申请日：2000-03-02
申请人： Robert Z. Bachrach , John C. Moran
发明人： Robert Z. Bachrach , John C. Moran
IPC分类号： B65G4907
CPC分类号： H01L21/67271 , H01L21/67196 , H01L21/67727 , H01L21/67775 , Y10S414/139 , Y10S414/14
摘要： A fabrication system is provided which includes a storage apparatus coupled perpendicularly to a branch transport aisle, and one or more environmentally controlled fabrication tools coupled parallel to the branch transport aisle. The fabrication tools can encompass single chamber units or larger cluster tools with sub mainframes. The storage apparatus has one or more load ports which allow transfer of wafer carriers to or from a factory transport agent. A tool loading platform is positioned to receive a wafer carrier from the storage apparatus and to enable the fabrication tool to access a wafer carrier positioned thereon. A plurality of fabrication tools may be coupled beside each other within the equipment set. Each of the plurality of fabrication tools is coupled to the storage apparatus so that a wafer or wafer carrier may be received from or transferred to a factory transport agent and may travel along the storage apparatus to any of the plurality of fabrication tools coupled thereto. A computer program allows input of the number of tools coupled to a storage apparatus, and adjusts wafer carrier delivery based thereon. A method of reducing initial capital investment is also provided.
摘要翻译：提供了一种制造系统，其包括垂直于分支运输通道耦合的存储装置，以及一个或多个环境受控的制造工具，其与分支运输通道并联耦合。制造工具可以包括单室单元或具有子大型机的更大的集群工具。存储装置具有一个或多个负载端口，其允许将晶片载体传送到工厂运输代理或从工厂运输代理传送。工具装载平台被定位成从存储装置接收晶片载体并且使得制造工具能够访问位于其上的晶片载体。多个制造工具可以在设备组内相互耦合。多个制造工具中的每一个耦合到存储装置，使得晶片或晶片载体可以从工厂运输代理接收或转移到工厂运输代理，并且可以沿着存储设备行进到与其耦合的多个制造工具中的任何一个。计算机程序允许输入耦合到存储装置的工具的数量，并且基于此来调整晶片载体传送。还提供了减少初始资本投资的方法。

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