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61. 发明授权

US6118698A Output multiplexing implementation for a simultaneous operation flash memory device 有权
标题翻译：用于同时运行的闪存设备的输出多路复用实现
公开(公告)号：US6118698A
公开(公告)日：2000-09-12
申请号：US422199
申请日：1999-10-19
申请人： Takao Akaogi , Kazuhiro Kurihara , Tien-Min Chen
发明人： Takao Akaogi , Kazuhiro Kurihara , Tien-Min Chen
IPC分类号： G11C16/26 , G11C16/28 , G11C16/04
CPC分类号： G11C16/26 , G11C16/28
摘要： A flash memory chip including a synchronization circuit for multiplexed sense amplifier output signal paths is disclosed. The synchronization circuit includes a signal generator, sense amplifiers and an output multiplexer. The arrival of data from the sense amplifiers to the output multiplexer is equalized. Equalization is achieved by adjusting the signal path length, and thereby the resistance and capacitance, of the signal paths from the signal generator to the sense amplifiers which carry the signal to cause the sense amplifiers to transmit their data to the output multiplexers.
摘要翻译：公开了一种包括用于复用的读出放大器输出信号路径的同步电路的闪存芯片。同步电路包括信号发生器，读出放大器和输出多路复用器。来自读出放大器的数据到达输出多路复用器是相等的。通过调整信号路径长度，从而从信号发生器到读出放大器的信号路径长度的电阻和电容来实现均衡，该读出放大器承载信号以使读出放大器将其数据传输到输出多路复用器。

62. 发明授权

US5910916A Flash-erasable semiconductor memory device having improved reliability 失效
标题翻译：闪存可擦除半导体存储器件具有改进的可靠性
公开(公告)号：US5910916A
公开(公告)日：1999-06-08
申请号：US986339
申请日：1997-12-05
申请人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
发明人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/00
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.
摘要翻译：闪存可擦除半导体存储器件包括存储单元阵列，其包括多个存储单元晶体管，每个存储单元晶体管具有用于存储信息的绝缘浮动栅极和设置在所述浮置栅极上的控制电极，其中闪存可擦除半导体存储器件包括写入控制电路提供写入控制信号时，写入信息。写入控制电路产生控制信号，使得漏极控制信号的前沿出现在栅极控制信号的前沿之后。此外，栅极控制电路关闭栅极控制信号，使得栅极控制信号的后沿出现在漏极控制信号的后沿之后。

63. 发明授权

US5835416A Flash-erasable semiconductor memory device having an improved reliability 失效
公开(公告)号：US5835416A
公开(公告)日：1998-11-10
申请号：US986338
申请日：1997-12-05
申请人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
发明人： Takao Akaogi , Yasushige Ogawa , Tatsuya Kajita , Hisayoshi Watanabe , Minoru Yamashita
IPC分类号： G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/00 , H01L21/8247 , H01L27/105 , H01L27/115 , G11C16/00
CPC分类号： H01L27/11526 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/30 , G11C16/32 , G11C29/846 , H01L27/105 , H01L27/115 , H01L27/11543
摘要： A flash-erasable semiconductor memory device comprises a memory cell array including a plurality of memory cell transistors each having an insulated floating gate for storing information and a control electrode provided on said floating gate, wherein the flash-erasable semiconductor memory device includes a write control circuit supplied with a write control signal, when writing information. The write control circuit produces a control signal such that a leading edge of the drain control signal appears after a leading edge of the gate control signal. Further, the gate control circuit shuts off the gate control signal such that a trailing edge of the gate control signal appears after a trailing edge of the drain control signal.

64. 发明授权

US5091888A Semiconductor memory device 失效
公开(公告)号：US5091888A
公开(公告)日：1992-02-25
申请号：US552972
申请日：1990-07-12
申请人： Takao Akaogi
发明人： Takao Akaogi
IPC分类号： G11C17/00 , G11C16/06 , G11C16/28
CPC分类号： G11C16/28
摘要： A semiconductor memory device comprises memory cells for storing data, reference cells for storing reference data, and an output part supplied with an output signal from the memory cells and a reference signal from the reference cells for comparing the output signal and the reference signal and producing an output signal of the semiconductor memory device indicative of the data stored in the memory cell means on the basis of the comparison. In the present invention, the reference cell includes a plurality of reference cell transistors connected in parallel with each other for storing the reference data such that a same reference data is stored in each of the reference cell transistors.

65. 发明授权

US08654591B2 Local word line driver and flash memory array device thereof 有权
标题翻译：本地字线驱动器及其闪存阵列器件
公开(公告)号：US08654591B2
公开(公告)日：2014-02-18
申请号：US12980442
申请日：2010-12-29
申请人： Takao Akaogi
发明人： Takao Akaogi
IPC分类号： G11C16/06 , G11C16/08
CPC分类号： G11C16/08 , G11C8/08
摘要： In a local word line driver of an NOR flash memory and its flash memory array device, the local word line driver is provided for driving a local word line in a sector of a memory array, and the local word line driver has two transistors including a first transistor and a second transistors, and the first and second transistors are NMOS transistors, and thus achieving the effects of reducing the area occupied by circuits on the local word line driver and the die size, and saving the area for the use by memory units.
摘要翻译：在NOR闪存的本地字线驱动器及其闪速存储器阵列器件中，提供本地字线驱动器用于驱动存储器阵列的扇区中的本地字线，并且本地字线驱动器具有两个晶体管，包括：第一晶体管和第二晶体管，并且第一和第二晶体管是NMOS晶体管，从而实现减少局部字线驱动器上的电路占用的面积和芯片尺寸的效果，并且保存由存储器单元使用的区域。

66. 发明申请

US20080285354A1 Self reference sensing system and method 审中-公开
标题翻译：自我参考感测系统及方法
公开(公告)号：US20080285354A1
公开(公告)日：2008-11-20
申请号：US11804170
申请日：2007-05-16
申请人： Soo-Yong Park , Takao Akaogi , Michael Van Buskirk
发明人： Soo-Yong Park , Takao Akaogi , Michael Van Buskirk
IPC分类号： G11C11/34 , G11C5/14
CPC分类号： G11C16/28 , G11C16/0458
摘要： A self sensing reference system and method are described. The self sensing reference systems and methods facilitate efficient accurate access to information. In one embodiment, a self sensing reference system includes a main cascode component, a self referencing component, and a comparison verification component. The main cascode component receives input on a first current value and a second current value. The self referencing component establishes a plurality of data indications wherein a first data indication is established based upon a comparison of the first current value to the second current value. A comparison verification component verifies a second data indication.
摘要翻译：描述了自感基准系统和方法。自我检测参考系统和方法有助于有效准确地访问信息。在一个实施例中，自感基准系统包括主共源共栅分量，自参考分量和比较验证分量。主级联组件接收第一电流值和第二电流值的输入。自参考分量建立多个数据指示，其中基于第一当前值与第二当前值的比较来建立第一数据指示。比较验证部件验证第二数据指示。

67. 发明授权

US07260019B1 Memory array 有权
标题翻译：内存阵列
公开(公告)号：US07260019B1
公开(公告)日：2007-08-21
申请号：US11262651
申请日：2005-10-31
申请人： Takao Akaogi
发明人： Takao Akaogi
IPC分类号： G11C8/00 , G11C7/00
CPC分类号： G11C8/12
摘要： A memory array includes a plurality of memory banks, each having a plurality of sectors and a plurality of sector decoders, each sector decoder operatively associated with a sector. A first plurality of lines provides first signals, and a second plurality of lines provides second signals. A first decoder apparatus is operatively associated with the first plurality of lines for receiving the first signals and for providing a first address signal by means of a first single line to a sector decoder of a memory bank. A second decoder apparatus is operatively associated with the second plurality of lines for receiving the second signals and for providing a second address signal by means of a second single line to a sector decoder of a memory bank.
摘要翻译：存储器阵列包括多个存储体，每个存储体具有多个扇区和多个扇区解码器，每个扇区解码器与扇区可操作地相关联。第一组多行提供第一信号，第二组线提供第二信号。第一解码器装置与第一组多个线路可操作地相关联，用于接收第一信号，并通过第一条线路将第一地址信号提供给存储体的扇区解码器。第二解码器装置可操作地与第二多个线路相关联，用于接收第二信号，并且通过第二单线将存储体的扇区解码器提供第二地址信号。

68. 发明授权

US07260014B1 Voltage supply circuit for memory array programming 有权
标题翻译：用于存储器阵列编程的电源电路
公开(公告)号：US07260014B1
公开(公告)日：2007-08-21
申请号：US11250913
申请日：2005-10-14
申请人： Takao Akaogi , Nian Yang
发明人： Takao Akaogi , Nian Yang
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , G11C16/30
摘要： According to one exemplary embodiment, a memory array includes a number of bitlines. The memory array further includes a voltage supply circuit, where the voltage supply circuit is configured to receive an operating voltage and a control signal and to output a low output voltage in a switching mode and a high output voltage in a programming mode. The low output voltage can be approximately equal to the operating voltage in the switching mode. In the programming mode, the high output voltage is greater than the operating voltage. According to this exemplary embodiment, the voltage supply circuit is in the programming mode when one of the bitlines is selected for programming. The voltage supply circuit is in the switching mode if none of the bitlines is selected for programming. The high output voltage can cause a bitline programming voltage to be applied to a selected bitline in the programming mode.
摘要翻译：根据一个示例性实施例，存储器阵列包括多个位线。存储器阵列还包括电压供应电路，其中电压供应电路被配置为接收工作电压和控制信号，并且在编程模式下以开关模式和高输出电压输出低输出电压。低输出电压可以近似等于开关模式下的工作电压。在编程模式下，高输出电压大于工作电压。根据该示例性实施例，当选择其中一个位线用于编程时，电压供应电路处于编程模式。如果没有选择位线进行编程，则电源电路处于开关模式。高输出电压可能导致在编程模式下将位线编程电压施加到选定的位线。

69. 发明授权

US06351420B1 Voltage boost level clamping circuit for a flash memory 有权
标题翻译：用于闪存的电压升压电平钳位电路
公开(公告)号：US06351420B1
公开(公告)日：2002-02-26
申请号：US09595519
申请日：2000-06-16
申请人： Takao Akaogi , Ali K. Al-Shamma , Lee Edward Cleveland , Yong Kim , Jin-Lien Lin , Boon Tang Teh , Kendra Nguyen
发明人： Takao Akaogi , Ali K. Al-Shamma , Lee Edward Cleveland , Yong Kim , Jin-Lien Lin , Boon Tang Teh , Kendra Nguyen
IPC分类号： G11C700
CPC分类号： G11C8/08 , G11C5/145 , G11C16/12 , G11C16/30
摘要： A voltage boost circuit (111) for a flash memory (100) includes a boosting circuit (110), which is capable of boosting a portion of a power supply voltage (VCC) of the flash memory to a word line voltage level adequate for accessing a core cell in a core cell array (102) of the memory. The voltage boost circuit further includes a balancing or clamping circuit (112) for providing a nonzero adjustment voltage (VCL) to the boosting circuit to reduce the portion of the supply voltage that is available for boosting by the boosting circuit when the power supply voltage exceeds a certain value.
摘要翻译：用于闪存（100）的升压电路（111）包括升压电路（110），其能够将闪存的电源电压（VCC）的一部分升压到足以访问的字线电压电平存储器的核心单元阵列（102）中的核心单元。升压电路还包括用于向升压电路提供非零调节电压（VCL）的平衡或钳位电路（112），以在电源电压超过时减小升压电路可用于升压的电源电压部分一定的价值。

70. 发明授权

US06327181B1 Reference cell bitline path architecture for a simultaneous operation flash memory device 有权
标题翻译：用于同时操作闪存器件的参考单元位线路径架构
公开(公告)号：US06327181B1
公开(公告)日：2001-12-04
申请号：US09421775
申请日：1999-10-19
申请人： Takao Akaogi , Tien-Min Chen , Kazuhiro Kurihara
发明人： Takao Akaogi , Tien-Min Chen , Kazuhiro Kurihara
IPC分类号： G11C1604
CPC分类号： G11C16/24
摘要： A dual bank flash memory device including a reference path equalization circuits is disclosed. In the device, each bank includes a read path with an electrical characteristic. The device further includes a reference circuit which comprises a reference cell and reference paths which also have an electrical characteristic. The reference equalization circuits are coupled with the reference circuit which equalizes the read path electrical characteristics with the reference path electrical characteristics.
摘要翻译：公开了一种包括参考路径均衡电路的双银行闪存装置。在设备中，每个存储体包括具有电特性的读取路径。该装置还包括参考电路，其包括参考单元和也具有电特性的参考路径。参考均衡电路与参考电路耦合，该参考电路将读路径电特性与参考路径电特性相等。

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