专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

61. 发明授权

US07795135B2 Method for producing a layer arrangement 有权
标题翻译：层布置方法
公开(公告)号：US07795135B2
公开(公告)日：2010-09-14
申请号：US11639393
申请日：2006-12-14
申请人： Stefan Eckert , Klaus Goller , Hermann Wendt
发明人： Stefan Eckert , Klaus Goller , Hermann Wendt
IPC分类号： H01L21/311
CPC分类号： H01L21/76802 , H01L21/76834
摘要： The invention relates to a method for producing a layer arrangement. An electrically conductive layer is formed and patterned. A sacrificial layer formed on at least part of the patterned electrically conductive layer. An electrically insulating layer is formed on the electrically conductive and sacrificial layers and is patterned in such a manner that one or more surface areas of the sacrificial layer are exposed. The exposed areas of the sacrificial layer are removed to expose one or more surface areas of the patterned electrically conductive layer. The patterned electrically conductive layer is covered with a pattern of electrically conductive material.
摘要翻译：本发明涉及一种生产层布置的方法。形成导电层并构图。形成在图案化导电层的至少一部分上的牺牲层。在导电和牺牲层上形成电绝缘层，并以牺牲层的一个或多个表面区域露出的方式构图。去除牺牲层的暴露区域以暴露图案化导电层的一个或多个表面区域。图案化的导电层被导电材料的图案覆盖。

62. 发明申请

US20100144112A1 Methods of Manufacturing Semiconductor Devices 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20100144112A1
公开(公告)日：2010-06-10
申请号：US12618567
申请日：2009-11-13
申请人： Markus Naujok , Hermann Wendt , Alois Gutmann , Muhammed Shafi Pallachalil
发明人： Markus Naujok , Hermann Wendt , Alois Gutmann , Muhammed Shafi Pallachalil
IPC分类号： H01L21/764 , H01L21/762
CPC分类号： H01L23/5222 , H01L21/7682 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming air gaps between interconnects of integrated circuits and structures thereof are disclosed. A first insulating material is deposited over a workpiece, and a second insulating material having a sacrificial portion is deposited over the first insulating material. Conductive lines are formed in the first and second insulating layers. The second insulating material is treated to remove the sacrificial portion, and at least a portion of the first insulating material is removed, forming air gaps between the conductive lines. The second insulating material is impermeable as deposited and permeable after treating it to remove the sacrificial portion. A first region of the workpiece may be masked during the treatment, so that the second insulating material becomes permeable in a second region of the workpiece yet remains impermeable in the first region, thus allowing the formation of the air gaps in the second region, but not the first region.
摘要翻译：公开了在集成电路的互连和其结构之间形成气隙的方法。第一绝缘材料沉积在工件上方，并且具有牺牲部分的第二绝缘材料沉积在第一绝缘材料上。导电线形成在第一和第二绝缘层中。处理第二绝缘材料以去除牺牲部分，并且去除第一绝缘材料的至少一部分，在导线之间形成气隙。第二绝缘材料在处理它以去除牺牲部分之后是不可渗透的并且是可渗透的。工件的第一区域可以在处理期间被掩蔽，使得第二绝缘材料在工件的第二区域变得可渗透，但在第一区域中仍然不可渗透，从而允许在第二区域中形成气隙，但是不是第一个地区。

63. 发明授权

US07619310B2 Semiconductor interconnect and method of making same 有权
标题翻译：半导体互连及其制作方法
公开(公告)号：US07619310B2
公开(公告)日：2009-11-17
申请号：US11592427
申请日：2006-11-03
申请人： Frank Huebinger , Moosung Chae , Armin Tilke , Hermann Wendt
发明人： Frank Huebinger , Moosung Chae , Armin Tilke , Hermann Wendt
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76834 , H01L21/76835 , H01L21/7684 , H01L21/76849 , H01L23/5222 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit interconnect structure includes a conductive line, a first barrier layer disposed on a bottom surface of conductive line, a second barrier layer disposed on the top surface of the conductive line, and an interlevel dielectric surrounding the conductive line.
摘要翻译：集成电路互连结构包括导线，布置在导线底面上的第一阻挡层，设置在导线上表面的第二阻挡层和围绕导线的层间电介质。

64. 发明申请

US20090203192A1 Crack Stop Trenches 有权
标题翻译：破裂停止沟槽
公开(公告)号：US20090203192A1
公开(公告)日：2009-08-13
申请号：US12030435
申请日：2008-02-13
申请人： Erdem Kaltalioglu , Hermann Wendt
发明人： Erdem Kaltalioglu , Hermann Wendt
IPC分类号： H01L21/00
CPC分类号： H01L21/78 , H01L21/31116
摘要： Structures and methods of forming crack stop trenches are disclosed. The method includes forming active regions disposed in cell regions of a substrate, the cell regions separated by dicing channels, and forming back end of line (BEOL) layers over the substrate, the BEOL layers being formed over the cell regions and the dicing channels. Crack stop trenches are then formed encircling the cell regions by etching a portion of the BEOL layers surrounding the cell regions. The wafer is diced along the dicing channels.
摘要翻译：公开了形成裂纹停止沟槽的结构和方法。该方法包括形成设置在衬底的单元区域中的有源区，由切割通道分离的单元区域，以及在衬底上形成后端（BEOL）层，在单元区域和切割通道上形成BEOL层。然后通过蚀刻围绕单元区域的一部分BEOL层，形成围绕单元区域的裂纹停止沟槽。晶片沿着切割通道切割。

65. 发明申请

US20080258308A1 Method of controlled low-k via etch for Cu interconnections 有权
标题翻译：用于Cu互连的受控低k通孔蚀刻的方法
公开(公告)号：US20080258308A1
公开(公告)日：2008-10-23
申请号：US11788969
申请日：2007-04-23
申请人： Wuping Liu , Johnny Widodo , Teck Jung Tang , Jing Hui Li , Han Wah Ng , Larry A. Clevenger , Hermann Wendt
发明人： Wuping Liu , Johnny Widodo , Teck Jung Tang , Jing Hui Li , Han Wah Ng , Larry A. Clevenger , Hermann Wendt
IPC分类号： H01L21/4763 , H01L21/76 , H01L29/40
CPC分类号： H01L21/76802 , H01L21/02063 , H01L21/31111 , H01L21/31116 , H01L21/31138
摘要： An interconnect stack and a method of manufacturing the same wherein the interconnect has vertical sidewall vias. The interconnect stack includes a substrate, a metal interconnect formed in the substrate, an etch stop formed on the substrate and the metal interconnect, and an interlayer dielectric (ILD) layer having at least one via formed therein extending through a transition layer formed on the etch stop layer. The via is formed by etching the ILD to a first depth and ashing the interconnect stack to modify a portion of the ILD between the portion of the via formed by etching and the transition layer. Ashing converts this portion of the ILD to an oxide material. The method includes wet etching the interconnect to remove the oxide material and a portion of the transition layer to form a via extending through the ILD to the etch stop layer.
摘要翻译：互连堆叠及其制造方法，其中互连具有垂直侧壁通孔。互连堆叠包括衬底，形成在衬底中的金属互连，形成在衬底上的蚀刻阻挡层和金属互连，以及层间电介质（ILD）层，其具有形成在其中的至少一个通孔，其延伸穿过形成在衬底上的过渡层蚀刻停止层。通过将ILD蚀刻到第一深度并且使互连堆叠灰化以修改通过蚀刻形成的通路的部分与过渡层之间的ILD的一部分而形成通孔。灰化将ILD的这部分转化为氧化物材料。该方法包括湿蚀刻互连以去除氧化物材料和过渡层的一部分，以形成延伸穿过ILD到蚀刻停止层的通孔。

66. 发明授权

US06670668B2 Microelectronic structure, method for fabricating it and its use in a memory cell 有权
标题翻译：微电子结构，其制造方法及其在存储单元中的应用
公开(公告)号：US06670668B2
公开(公告)日：2003-12-30
申请号：US09796208
申请日：2001-02-28
申请人： Hermann Wendt
发明人： Hermann Wendt
IPC分类号： H01L27108
CPC分类号： H01L28/60
摘要： A microelectronic structure that is suitable, in particular, as part of a storage capacitor includes a semiconductor structure, a barrier structure, an electrode structure, and a dielectric structure made of a high-epsilon material. The electrode structure has a tensile mechanical layer stress. The microelectronic structure is fabricated, in particular, by sputtering platinum in order to form the electrode structure at a sputtering temperature of at least 200° C.
摘要翻译：特别适用于存储电容器的一部分的微电子结构包括半导体结构，阻挡结构，电极结构和由高ε材料制成的电介质结构。电极结构具有拉伸机械层应力。微电子结构特别是通过溅射铂来制造，以便在至少200℃的溅射温度下形成电极结构。

67. 发明授权

US06656376B1 Process for cleaning CVD units 有权
标题翻译：清洗CVD装置的方法
公开(公告)号：US06656376B1
公开(公告)日：2003-12-02
申请号：US09360944
申请日：1999-07-26
申请人： Elke Fritsch , Christine Dehm , Hermann Wendt , Volker Weinrich
发明人： Elke Fritsch , Christine Dehm , Hermann Wendt , Volker Weinrich
IPC分类号： B44C122
CPC分类号： C23C16/4405 , Y10S438/905
摘要： A cleaning process for cleaning CVD units is disclosed. In the cleaning process, alkaline earth metal and/or metal-containing process residues, which form an amorphous film on reactor walls, are removed using a dry etching medium containing free diketones at a greatly reduced pressure and an elevated temperature. In the process, the free diketones react with the alkaline earth metals or metals to form volatile complexes.
摘要翻译：公开了用于清洁CVD单元的清洁方法。在清洁过程中，在反应器壁上形成非晶膜的碱土金属和/或含金属的工艺残留物使用在大大降低的压力和升高的温度下使用含有游离二酮的干蚀刻介质来除去。在此过程中，游离二酮与碱土金属或金属反应形成挥发性络合物。

68. 发明授权

US06458603B1 Method of fabricating a micro-technical structure, and micro-technical component 失效
公开(公告)号：US06458603B1
公开(公告)日：2002-10-01
申请号：US09974938
申请日：2001-10-10
申请人： Alfred Kersch , Siegfried Schwarzl , Stefan Miethaner , Hermann Wendt
发明人： Alfred Kersch , Siegfried Schwarzl , Stefan Miethaner , Hermann Wendt
IPC分类号： H01L2100
CPC分类号： H01L43/12
摘要： The invention relates to a method for fabricating in particular a TMR element for use in a MRAM, wherein a mask is arranged on a substrate and structured in such a manner that it shadows but does not cover a surface region of the substrate, and wherein material of the structure which is to be fabricated is then deposited on the substrate in a directed deposition process. The invention also relates to a component with a micro-technical structure which has been fabricated in this manner.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式