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61. 发明授权

US08374047B2 Dynamic random access memory device and method for self-refreshing memory cells 有权
标题翻译：动态随机存取存储器件及其自身刷新存储单元的方法
公开(公告)号：US08374047B2
公开(公告)日：2013-02-12
申请号：US13004461
申请日：2011-01-11
申请人： HakJune Oh
发明人： HakJune Oh
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C7/04 , G11C11/40615 , G11C11/40626
摘要： A dynamic random access memory (DRAM) device having memory cells is operated in a self-refresh mode and a normal mode. A mode detector provides a self-refresh mode signal in the self-refresh mode of operation. It includes a free-running oscillator for generating an oscillation signal independent of the self-refresh mode signal. In response to the oscillation signal, a self-request controller provides a self-refresh request signal in the self-refresh mode. The self-refresh signal is asynchoronized with the self-fresh mode signal and is provided to an address circuit to select a wordline for refreshing the memory cells thereof. The self-refresh request controller includes logic circuitry for arbitrating timing between initial active edges of the oscillation signal and the self-refresh mode signal and providing the self-refresh request and ceasing it, regardless of conflict between the self-refresh mode signal and the oscillation signal upon self-refresh mode entry and exit. The DRAM devices perform and achieve reliable self-refresh for variable DRAM cell retention time.
摘要翻译：具有存储单元的动态随机存取存储器（DRAM）装置在自刷新模式和正常模式下操作。模式检测器在自刷新操作模式下提供自刷新模式信号。它包括一个自由运行的振荡器，用于产生独立于自刷新模式信号的振荡信号。响应于振荡信号，自请求控制器在自刷新模式下提供自刷新请求信号。自刷新信号与自清晰模式信号异步化，并被提供给地址电路以选择用于刷新其存储单元的字线。自刷新请求控制器包括逻辑电路，用于仲裁振荡信号的初始有效边沿与自刷新模式信号之间的定时，并提供自刷新请求并停止它，而不管自刷新模式信号和自刷新模式进入和退出时的振荡信号。 DRAM器件执行并实现可变DRAM单元保留时间的可靠的自刷新。

62. 发明申请

US20110258366A1 STATUS INDICATION IN A SYSTEM HAVING A PLURALITY OF MEMORY DEVICES 审中-公开
标题翻译：在具有大量存储器件的系统中的状态指示
公开(公告)号：US20110258366A1
公开(公告)日：2011-10-20
申请号：US13023838
申请日：2011-02-09
申请人： Roland Schuetz , HakJune Oh , Hong Beom Pyeon
发明人： Roland Schuetz , HakJune Oh , Hong Beom Pyeon
IPC分类号： G06F12/00
CPC分类号： G11C7/1063 , G11C16/06
摘要： Status indication in a system having a plurality of memory devices is disclosed. A memory device in the system includes a plurality of data pins for connection to a data bus. The memory device also includes a status pin for connection to a status line that is independent from the data bus. The memory device also includes first circuitry for generating, upon completion of a memory operation having a first duration, a strobe pulse of a second duration much shorter than the first duration. The strobe pulse provides an indication of the completion of the memory operation. The memory device also includes second circuitry for outputting the strobe pulse onto the status line via the status pin.
摘要翻译：公开了具有多个存储器件的系统中的状态指示。系统中的存储器件包括用于连接到数据总线的多个数据引脚。存储器件还包括用于连接到独立于数据总线的状态线的状态引脚。存储器件还包括第一电路，用于在完成具有第一持续时间的存储器操作时产生比第一持续时间短得多的第二持续时间的选通脉冲。选通脉冲提供存储器操作完成的指示。存储器件还包括用于经由状态引脚将选通脉冲输出到状态线上的第二电路。

63. 发明申请

US20110122719A1 PRE-CHARGE VOLTAGE GENERATION AND POWER SAVING MODES 有权
标题翻译：预充电电压和节电模式
公开(公告)号：US20110122719A1
公开(公告)日：2011-05-26
申请号：US13019100
申请日：2011-02-01
申请人： Valerie L. Lines , HakJune Oh
发明人： Valerie L. Lines , HakJune Oh
IPC分类号： G11C5/14
CPC分类号： G11C5/148 , G11C5/147 , G11C7/1048 , G11C7/1078 , G11C7/1096 , G11C8/08 , G11C2207/2227
摘要： A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set to a power-saving mode. According to one embodiment, the input adjusts a magnitude of the pre-charge voltage signal produced by the voltage generator. Such an embodiment is useful over conventional methods because adjusting the pre-charge voltage can result in power savings. As an example, when in the power-saving mode, the voltage generator circuit can adjust the pre-charge voltage to a value that reduces an amount of leakage current associated with a pre-charge voltage. Reducing the leakage with respect to the pre-charge voltage means that the saved power can be used for other useful purposes.
摘要翻译：系统包括电压发生器，以产生用于对存储器电路中的一个或多个信号进行预充电的预充电电压信号。一个或多个信号可以是用于访问存储器的数据总线。电压发生器可以包括指示存储器电路是否被设置为省电模式的输入。根据一个实施例，输入调节由电压发生器产生的预充电电压信号的幅度。这种实施例对于常规方法是有用的，因为调节预充电电压可导致功率节省。例如，在省电模式下，电压发生器电路可以将预充电电压调整为减小与预充电电压相关联的漏电流量的值。减少相对于预充电电压的泄漏意味着所节省的功率可以用于其他有用的目的。

64. 发明申请

US20100202224A1 MEMORY WITH DATA CONTROL 有权
标题翻译：数据控制记忆
公开(公告)号：US20100202224A1
公开(公告)日：2010-08-12
申请号：US12699627
申请日：2010-02-03
申请人： HakJune Oh
发明人： HakJune Oh
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C7/1078 , G11C7/109 , G11C7/22 , G11C16/102 , G11C2207/107 , G11C2216/30
摘要： In an embodiment, a memory device comprises memory, a first data link, a first input, a second input, a second data link, a first output and a second output. The first data link is configured to input one or more packets into the memory device. The first input is configured to input command strobe signals into the memory device that delineate command packets that are input into the memory device via the first data link. The second input is configured to input data strobe signals into the memory device that delineate data packets that are input into the memory device via the first data link. The first and second outputs are configured to output the command strobe signal and data strobe signal, respectively. The second data link is configured to output packets from the memory device.
摘要翻译：在一个实施例中，存储器设备包括存储器，第一数据链路，第一输入，第二输入，第二数据链路，第一输出和第二输出。第一数据链路被配置为将一个或多个分组输入到存储器设备中。第一输入被配置为将命令选通信号输入到描绘经由第一数据链路输入存储器件的命令分组的存储器件中。第二输入被配置为将数据选通信号输入到通过第一数据链路描绘输入存储器件的数据分组的存储器件中。第一和第二输出被配置为分别输出命令选通信号和数据选通信号。第二数据链路被配置为从存储设备输出分组。

65. 发明申请

US20100157714A1 APPARATUS AND METHOD FOR SELF-REFRESHING DYNAMIC RANDOM ACCESS MEMORY CELLS 失效
标题翻译：用于自动修复动态随机存取存储器的装置和方法
公开(公告)号：US20100157714A1
公开(公告)日：2010-06-24
申请号：US12715641
申请日：2010-03-02
申请人： HakJune Oh
发明人： HakJune Oh
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C2211/4061
摘要： A dynamic random access memory (DRAM) having DRAM cells coupled to wordlines and bitlines. In a self-refresh mode, the cells coupled with the even numbered rows retain main data previously stored therein and the assistant data, which is logically opposite to the main data, is overwritten into the cells coupled with the wordlines of the odd numbered rows. When the DRAM enters the self-refresh mode, a starting refresh address for the self-refresh mode is detected. If the detected starting refresh address does not match with a predetermined correct address set for the self-refresh operation mode, a dummy refresh cycle will be established in an entry-burst self-refresh period. During the dummy refresh cycle, a dummy refresh command is added to increment an internal row address counter that provides row addresses for self-refreshing the cells of the selected wordlines within the cell array.
摘要翻译：具有耦合到字线和位线的DRAM单元的动态随机存取存储器（DRAM）。在自刷新模式中，与偶数行耦合的单元保留先前存储在其中的主数据，并且与主数据逻辑上相反的辅助数据被覆盖到与奇数行的字线耦合的单元中。当DRAM进入自刷新模式时，检测到用于自刷新模式的起始刷新地址。如果检测到的起始刷新地址与为自刷新操作模式设置的预定正确地址不匹配，则将在入口突发自刷新周期中建立虚拟刷新周期。在虚拟刷新周期期间，添加虚拟刷新命令以增加内部行地址计数器，该内部行地址计数器提供行地址以便自动刷新单元阵列内所选字线的单元。

66. 发明授权

US07492658B2 Apparatus and method for self-refreshing dynamic random access memory cells 失效
标题翻译：用于自动刷新动态随机存取存储器单元的装置和方法
公开(公告)号：US07492658B2
公开(公告)日：2009-02-17
申请号：US11930292
申请日：2007-10-31
申请人： HakJune Oh
发明人： HakJune Oh
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C2211/4061
摘要： A dynamic random access memory (DRAM) having DRAM cells coupled to wordlines and bitlines. In a self-refresh mode, the cells coupled with the even numbered rows retain main data previously stored therein and the assistant data, which is logically opposite to the main data, is overwritten into the cells coupled with the wordlines of the odd numbered rows. When the DRAM enters the self-refresh mode, a starting refresh address for the self-refresh mode is detected. If the detected starting refresh address does not match with a predetermined correct address set for the self-refresh operation mode, a dummy refresh cycle will be established in an entry-burst self-refresh period. During the dummy refresh cycle, a dummy refresh command is added to increment an internal row address counter that provides row addresses for self-refreshing the cells of the selected wordlines within the cell array.
摘要翻译：具有耦合到字线和位线的DRAM单元的动态随机存取存储器（DRAM）。在自刷新模式下，与偶数行耦合的单元保留先前存储在其中的主数据，并且与主数据逻辑上相反的辅助数据被覆盖到与奇数行的字线耦合的单元中。当DRAM进入自刷新模式时，检测到用于自刷新模式的起始刷新地址。如果检测到的起始刷新地址与为自刷新操作模式设置的预定正确地址不匹配，则将在入口突发自刷新周期中建立虚拟刷新周期。在虚拟刷新周期期间，添加虚拟刷新命令以增加内部行地址计数器，该内部行地址计数器提供行地址以便自动刷新单元阵列内所选字线的单元。

67. 发明申请

US20080080492A1 Packet based ID generation for serially interconnected devices 有权
标题翻译：用于串行互连设备的基于分组的ID生成
公开(公告)号：US20080080492A1
公开(公告)日：2008-04-03
申请号：US11529293
申请日：2006-09-29
申请人： Hong Beom Pyeon , HakJune Oh
发明人： Hong Beom Pyeon , HakJune Oh
IPC分类号： H04J1/16 , H04L12/56
CPC分类号： G06F1/12 , G06F1/04 , G11C5/00 , G11C5/066 , G11C7/20
摘要： Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory devices. The IDs are generated synchronously with clock. Command data and previously generated ID data are synchronously registered. The registered data is synchronously output and provided as parallel data for calculation of a new ID for the neighboring device. The calculation is an addition or subtraction by one. The IDs are generated in a packet basis by interpreting serial packet-basis commands received at the serial input in response to clocks. A clock latency is controlled in response to the interpreted ID and the clock. In accordance with the controlled clock latency, a new ID is provided in a packet basis. In high frequency generation applications (e.g., 1 GHz), two adjacent devices connected in daisy chain fashion are guaranteed enough time margin to perform the interpretation of packet commands.
摘要翻译：各种存储器件（例如，DRAM，闪存）串联连接。存储器件需要其标识符（ID）。每个存储器件产生相邻存储器件的ID。 ID与时钟同步生成。命令数据和先前生成的ID数据被同步地注册。注册的数据被同步输出并作为用于计算相邻设备的新ID的并行数据提供。计算是一个加法或减法。通过解释响应于时钟在串行输入端接收的基于串行数据包的命令，以分组的形式生成ID。响应于解释的ID和时钟来控制时钟延迟。根据受控时钟延迟，以分组为基础提供新的ID。在高频产生应用（例如，1GHz）中，以菊链方式连接的两个相邻设备保证足够的时间余量来执行分组命令的解释。

68. 发明授权

US08700818B2 Packet based ID generation for serially interconnected devices 有权
标题翻译：用于串行互连设备的基于分组的ID生成
公开(公告)号：US08700818B2
公开(公告)日：2014-04-15
申请号：US11529293
申请日：2006-09-29
申请人： Hong Beom Pyeon , HakJune Oh
发明人： Hong Beom Pyeon , HakJune Oh
IPC分类号： G06F3/00 , G06F1/12
CPC分类号： G06F1/12 , G06F1/04 , G11C5/00 , G11C5/066 , G11C7/20
摘要： Various memory devices (e.g., DRAMs, flash memories) are serially interconnected. The memory devices need their identifiers (IDs). Each of the memory devices generates IDs for neighboring memory devices. The IDs are generated synchronously with clock. Command data and previously generated ID data are synchronously registered. The registered data is synchronously output and provided as parallel data for calculation of a new ID for the neighboring device. The calculation is an addition or subtraction by one. The IDs are generated in a packet basis by interpreting serial packet-basis commands received at the serial input in response to clocks. A clock latency is controlled in response to the interpreted ID and the clock. In accordance with the controlled clock latency, a new ID is provided in a packet basis. In high frequency generation applications (e.g., 1 GHz), two adjacent devices connected in daisy chain fashion are guaranteed enough time margin to perform the interpretation of packet commands.
摘要翻译：各种存储器件（例如，DRAM，闪存）串联连接。存储器件需要它们的标识符（ID）。每个存储器件产生相邻存储器件的ID。 ID与时钟同步生成。命令数据和先前生成的ID数据被同步地注册。注册的数据被同步输出并作为用于计算相邻设备的新ID的并行数据提供。计算是一个加法或减法。通过解释响应于时钟在串行输入端接收的基于串行数据包的命令，以分组的形式生成ID。响应于解释的ID和时钟来控制时钟延迟。根据受控时钟延迟，以分组为基础提供新的ID。在高频产生应用（例如，1GHz）中，以菊链方式连接的两个相邻设备保证足够的时间余量来执行分组命令的解释。

69. 发明授权

US08045365B2 Apparatus and method for self-refreshing dynamic random access memory cells 失效
标题翻译：用于自动刷新动态随机存取存储器单元的装置和方法
公开(公告)号：US08045365B2
公开(公告)日：2011-10-25
申请号：US12715641
申请日：2010-03-02
申请人： HakJune Oh
发明人： HakJune Oh
IPC分类号： G11C11/24
CPC分类号： G11C11/406 , G11C2211/4061
摘要： A dynamic random access memory (DRAM) having DRAM cells coupled to wordlines and bitlines. In a self-refresh mode, the cells coupled with the even numbered rows retain main data previously stored therein and the assistant data, which is logically opposite to the main data, is overwritten into the cells coupled with the wordlines of the odd numbered rows. When the DRAM enters the self-refresh mode, a starting refresh address for the self-refresh mode is detected. If the detected starting refresh address does not match with a predetermined correct address set for the self-refresh operation mode, a dummy refresh cycle will be established in an entry-burst self-refresh period. During the dummy refresh cycle, a dummy refresh command is added to increment an internal row address counter that provides row addresses for self-refreshing the cells of the selected wordlines within the cell array.
摘要翻译：具有耦合到字线和位线的DRAM单元的动态随机存取存储器（DRAM）。在自刷新模式中，与偶数行耦合的单元保留先前存储在其中的主数据，并且与主数据逻辑上相反的辅助数据被覆盖到与奇数行的字线耦合的单元中。当DRAM进入自刷新模式时，检测到用于自刷新模式的起始刷新地址。如果检测到的起始刷新地址与为自刷新操作模式设置的预定正确地址不匹配，则将在入口突发自刷新周期中建立虚拟刷新周期。在虚拟刷新周期期间，添加虚拟刷新命令以增加内部行地址计数器，该内部行地址计数器提供行地址以便自动刷新单元阵列内所选字线的单元。

70. 发明授权

US07903477B2 Pre-charge voltage generation and power saving modes 有权
标题翻译：预充电电压和省电模式
公开(公告)号：US07903477B2
公开(公告)日：2011-03-08
申请号：US12181115
申请日：2008-07-28
申请人： Valerie L. Lines , HakJune Oh
发明人： Valerie L. Lines , HakJune Oh
IPC分类号： G11C5/14
CPC分类号： G11C5/148 , G11C5/147 , G11C7/1048 , G11C7/1078 , G11C7/1096 , G11C8/08 , G11C2207/2227
摘要： A system includes a voltage generator to produce a pre-charge voltage signal for pre-charging one or more signals in a memory circuit. The one or more signals can be data bus lines used to access memory. The voltage generator can include an input indicating whether the memory circuit is set to a power-saving mode. The input can be used to determine whether to adjust a magnitude of the pre-charge voltage signal produced by the voltage generator. Adjusting the pre-charge voltage can result in power savings. That is, when in the power-saving mode, the voltage generator circuit can adjust the pre-charge voltage to a value that reduces an amount of leakage current associated with a pre-charge voltage. Reducing the leakage with respect to the pre-charge voltage means that the saved power can be used for other useful purposes.
摘要翻译：系统包括电压发生器，以产生用于对存储器电路中的一个或多个信号进行预充电的预充电电压信号。一个或多个信号可以是用于访问存储器的数据总线。电压发生器可以包括指示存储器电路是否被设置为省电模式的输入。输入可用于确定是否调整由电压发生器产生的预充电电压信号的幅度。调整预充电电压可以节省电力。也就是说，在省电模式时，电压发生器电路可以将预充电电压调节到减小与预充电电压相关联的漏电流量的值。减少相对于预充电电压的泄漏意味着所节省的功率可以用于其他有用的目的。

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